mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-10-01 14:24:20 +03:00
update ath9k to latest git version
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12079 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
a264622c7d
commit
a4c1d0a1d4
@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=ath9k
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PKG_NAME:=ath9k
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PKG_VERSION:=20080731
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PKG_VERSION:=20080803
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PKG_RELEASE:=1
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PKG_RELEASE:=1
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include $(INCLUDE_DIR)/package.mk
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include $(INCLUDE_DIR)/package.mk
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File diff suppressed because it is too large
Load Diff
@ -29,10 +29,10 @@
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static int ath_beaconq_config(struct ath_softc *sc)
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static int ath_beaconq_config(struct ath_softc *sc)
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{
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{
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struct ath_hal *ah = sc->sc_ah;
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struct ath_hal *ah = sc->sc_ah;
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struct hal_txq_info qi;
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struct ath9k_txq_info qi;
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ath9k_hw_gettxqueueprops(ah, sc->sc_bhalq, &qi);
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ath9k_hw_gettxqueueprops(ah, sc->sc_bhalq, &qi);
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if (sc->sc_opmode == HAL_M_HOSTAP) {
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if (sc->sc_opmode == ATH9K_M_HOSTAP) {
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/* Always burst out beacon and CAB traffic. */
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/* Always burst out beacon and CAB traffic. */
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qi.tqi_aifs = 1;
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qi.tqi_aifs = 1;
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qi.tqi_cwmin = 0;
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qi.tqi_cwmin = 0;
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@ -70,11 +70,11 @@ static void ath_beacon_setup(struct ath_softc *sc,
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struct ath_hal *ah = sc->sc_ah;
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struct ath_hal *ah = sc->sc_ah;
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struct ath_desc *ds;
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struct ath_desc *ds;
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int flags, antenna;
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int flags, antenna;
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const struct hal_rate_table *rt;
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const struct ath9k_rate_table *rt;
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u_int8_t rix, rate;
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u8 rix, rate;
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int ctsrate = 0;
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int ctsrate = 0;
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int ctsduration = 0;
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int ctsduration = 0;
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struct hal_11n_rate_series series[4];
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struct ath9k_11n_rate_series series[4];
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DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
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DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
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__func__, skb, skb->len);
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__func__, skb, skb->len);
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@ -82,11 +82,11 @@ static void ath_beacon_setup(struct ath_softc *sc,
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/* setup descriptors */
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/* setup descriptors */
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ds = bf->bf_desc;
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ds = bf->bf_desc;
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flags = HAL_TXDESC_NOACK;
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flags = ATH9K_TXDESC_NOACK;
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if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
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if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport) {
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ds->ds_link = bf->bf_daddr; /* self-linked */
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ds->ds_link = bf->bf_daddr; /* self-linked */
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flags |= HAL_TXDESC_VEOL;
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flags |= ATH9K_TXDESC_VEOL;
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/* Let hardware handle antenna switching. */
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/* Let hardware handle antenna switching. */
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antenna = 0;
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antenna = 0;
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} else {
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} else {
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@ -114,10 +114,10 @@ static void ath_beacon_setup(struct ath_softc *sc,
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ath9k_hw_set11n_txdesc(ah, ds
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ath9k_hw_set11n_txdesc(ah, ds
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, skb->len + FCS_LEN /* frame length */
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, skb->len + FCS_LEN /* frame length */
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, HAL_PKT_TYPE_BEACON /* Atheros packet type */
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, ATH9K_PKT_TYPE_BEACON /* Atheros packet type */
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, avp->av_btxctl.txpower /* txpower XXX */
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, avp->av_btxctl.txpower /* txpower XXX */
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, HAL_TXKEYIX_INVALID /* no encryption */
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, ATH9K_TXKEYIX_INVALID /* no encryption */
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, HAL_KEY_TYPE_CLEAR /* no encryption */
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, ATH9K_KEY_TYPE_CLEAR /* no encryption */
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, flags /* no ack, veol for beacons */
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, flags /* no ack, veol for beacons */
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);
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);
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@ -129,11 +129,11 @@ static void ath_beacon_setup(struct ath_softc *sc,
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, ds /* first descriptor */
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, ds /* first descriptor */
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);
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);
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memzero(series, sizeof(struct hal_11n_rate_series) * 4);
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memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
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series[0].Tries = 1;
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series[0].Tries = 1;
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series[0].Rate = rate;
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series[0].Rate = rate;
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series[0].ChSel = sc->sc_tx_chainmask;
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series[0].ChSel = sc->sc_tx_chainmask;
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series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
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series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
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ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
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ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
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ctsrate, ctsduration, series, 4, 0);
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ctsrate, ctsduration, series, 4, 0);
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}
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}
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@ -325,7 +325,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
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/*
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/*
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* Setup a h/w transmit queue for beacons.
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* Setup a h/w transmit queue for beacons.
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*
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*
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* This function allocates an information structure (struct hal_txq_info)
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* This function allocates an information structure (struct ath9k_txq_info)
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* on the stack, sets some specific parameters (zero out channel width
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* on the stack, sets some specific parameters (zero out channel width
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* min/max, and enable aifs). The info structure does not need to be
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* min/max, and enable aifs). The info structure does not need to be
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* persistant.
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* persistant.
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@ -333,14 +333,14 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
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int ath_beaconq_setup(struct ath_hal *ah)
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int ath_beaconq_setup(struct ath_hal *ah)
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{
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{
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struct hal_txq_info qi;
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struct ath9k_txq_info qi;
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memzero(&qi, sizeof(qi));
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memzero(&qi, sizeof(qi));
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qi.tqi_aifs = 1;
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qi.tqi_aifs = 1;
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qi.tqi_cwmin = 0;
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qi.tqi_cwmin = 0;
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qi.tqi_cwmax = 0;
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qi.tqi_cwmax = 0;
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/* NB: don't enable any interrupts */
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/* NB: don't enable any interrupts */
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return ath9k_hw_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
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return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
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}
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}
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@ -373,7 +373,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
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struct ath_buf, list);
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struct ath_buf, list);
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list_del(&avp->av_bcbuf->list);
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list_del(&avp->av_bcbuf->list);
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if (sc->sc_opmode == HAL_M_HOSTAP ||
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if (sc->sc_opmode == ATH9K_M_HOSTAP ||
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!sc->sc_ah->ah_caps.halVEOLSupport) {
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!sc->sc_ah->ah_caps.halVEOLSupport) {
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int slot;
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int slot;
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/*
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/*
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@ -433,7 +433,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
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* following the header.
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* following the header.
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*/
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*/
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if (avp->av_bslot > 0) {
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if (avp->av_bslot > 0) {
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u_int64_t tsfadjust;
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u64 tsfadjust;
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__le64 val;
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__le64 val;
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int intval;
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int intval;
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@ -539,19 +539,19 @@ void ath_beacon_free(struct ath_softc *sc)
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void ath9k_beacon_tasklet(unsigned long data)
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void ath9k_beacon_tasklet(unsigned long data)
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{
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{
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#define TSF_TO_TU(_h,_l) \
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#define TSF_TO_TU(_h,_l) \
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((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
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((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
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struct ath_softc *sc = (struct ath_softc *)data;
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struct ath_softc *sc = (struct ath_softc *)data;
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struct ath_hal *ah = sc->sc_ah;
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struct ath_hal *ah = sc->sc_ah;
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struct ath_buf *bf = NULL;
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struct ath_buf *bf = NULL;
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int slot, if_id;
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int slot, if_id;
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u_int32_t bfaddr;
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u32 bfaddr;
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u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
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u32 rx_clear = 0, rx_frame = 0, tx_frame = 0;
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u_int32_t show_cycles = 0;
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u32 show_cycles = 0;
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u_int32_t bc = 0; /* beacon count */
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u32 bc = 0; /* beacon count */
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u_int64_t tsf;
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u64 tsf;
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u_int32_t tsftu;
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u32 tsftu;
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u_int16_t intval;
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u16 intval;
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if (sc->sc_noreset) {
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if (sc->sc_noreset) {
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show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
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show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
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@ -739,11 +739,11 @@ void ath_bstuck_process(struct ath_softc *sc)
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void ath_beacon_config(struct ath_softc *sc, int if_id)
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void ath_beacon_config(struct ath_softc *sc, int if_id)
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{
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{
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#define TSF_TO_TU(_h,_l) \
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#define TSF_TO_TU(_h,_l) \
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((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
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((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
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struct ath_hal *ah = sc->sc_ah;
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struct ath_hal *ah = sc->sc_ah;
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u_int32_t nexttbtt, intval;
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u32 nexttbtt, intval;
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struct ath_beacon_config conf;
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struct ath_beacon_config conf;
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enum hal_opmode av_opmode;
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enum ath9k_opmode av_opmode;
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if (if_id != ATH_IF_ID_ANY)
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if (if_id != ATH_IF_ID_ANY)
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av_opmode = sc->sc_vaps[if_id]->av_opmode;
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av_opmode = sc->sc_vaps[if_id]->av_opmode;
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@ -768,7 +768,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
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nexttbtt = TSF_TO_TU(LE_READ_4(conf.u.last_tstamp + 4),
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nexttbtt = TSF_TO_TU(LE_READ_4(conf.u.last_tstamp + 4),
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LE_READ_4(conf.u.last_tstamp));
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LE_READ_4(conf.u.last_tstamp));
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/* XXX conditionalize multi-bss support? */
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/* XXX conditionalize multi-bss support? */
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if (sc->sc_opmode == HAL_M_HOSTAP) {
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if (sc->sc_opmode == ATH9K_M_HOSTAP) {
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/*
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/*
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* For multi-bss ap support beacons are either staggered
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* For multi-bss ap support beacons are either staggered
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* evenly over N slots or burst together. For the former
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* evenly over N slots or burst together. For the former
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@ -776,10 +776,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
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* Slots that are not occupied will generate nothing.
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* Slots that are not occupied will generate nothing.
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*/
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*/
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/* NB: the beacon interval is kept internally in TU's */
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/* NB: the beacon interval is kept internally in TU's */
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intval = conf.beacon_interval & HAL_BEACON_PERIOD;
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intval = conf.beacon_interval & ATH9K_BEACON_PERIOD;
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intval /= ATH_BCBUF; /* for staggered beacons */
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intval /= ATH_BCBUF; /* for staggered beacons */
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} else {
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} else {
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intval = conf.beacon_interval & HAL_BEACON_PERIOD;
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intval = conf.beacon_interval & ATH9K_BEACON_PERIOD;
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}
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}
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if (nexttbtt == 0) /* e.g. for ap mode */
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if (nexttbtt == 0) /* e.g. for ap mode */
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@ -788,11 +788,11 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
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nexttbtt = roundup(nexttbtt, intval);
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nexttbtt = roundup(nexttbtt, intval);
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DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
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DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
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__func__, nexttbtt, intval, conf.beacon_interval);
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__func__, nexttbtt, intval, conf.beacon_interval);
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/* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
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/* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */
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if (sc->sc_opmode == HAL_M_STA) {
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if (sc->sc_opmode == ATH9K_M_STA) {
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struct hal_beacon_state bs;
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struct ath9k_beacon_state bs;
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u_int64_t tsf;
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u64 tsf;
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u_int32_t tsftu;
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u32 tsftu;
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int dtimperiod, dtimcount, sleepduration;
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int dtimperiod, dtimcount, sleepduration;
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int cfpperiod, cfpcount;
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int cfpperiod, cfpcount;
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@ -901,24 +901,24 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_set_sta_beacon_timers(ah, &bs);
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ath9k_hw_set_sta_beacon_timers(ah, &bs);
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sc->sc_imask |= HAL_INT_BMISS;
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sc->sc_imask |= ATH9K_INT_BMISS;
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ath9k_hw_set_interrupts(ah, sc->sc_imask);
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ath9k_hw_set_interrupts(ah, sc->sc_imask);
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} else {
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} else {
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u_int64_t tsf;
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u64 tsf;
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u_int32_t tsftu;
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u32 tsftu;
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ath9k_hw_set_interrupts(ah, 0);
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ath9k_hw_set_interrupts(ah, 0);
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if (nexttbtt == intval)
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if (nexttbtt == intval)
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intval |= HAL_BEACON_RESET_TSF;
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intval |= ATH9K_BEACON_RESET_TSF;
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if (sc->sc_opmode == HAL_M_IBSS) {
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if (sc->sc_opmode == ATH9K_M_IBSS) {
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/*
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/*
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* Pull nexttbtt forward to reflect the current
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* Pull nexttbtt forward to reflect the current
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* TSF .
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* TSF .
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*/
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*/
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#define FUDGE 2
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#define FUDGE 2
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if (!(intval & HAL_BEACON_RESET_TSF)) {
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if (!(intval & ATH9K_BEACON_RESET_TSF)) {
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tsf = ath9k_hw_gettsf64(ah);
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tsf = ath9k_hw_gettsf64(ah);
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tsftu = TSF_TO_TU((u_int32_t)(tsf>>32),
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tsftu = TSF_TO_TU((u32)(tsf>>32),
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(u_int32_t)tsf) + FUDGE;
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(u32)tsf) + FUDGE;
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do {
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do {
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nexttbtt += intval;
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nexttbtt += intval;
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} while (nexttbtt < tsftu);
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} while (nexttbtt < tsftu);
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@ -927,7 +927,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
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DPRINTF(sc, ATH_DBG_BEACON,
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DPRINTF(sc, ATH_DBG_BEACON,
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"%s: IBSS nexttbtt %u intval %u (%u)\n",
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"%s: IBSS nexttbtt %u intval %u (%u)\n",
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__func__, nexttbtt,
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__func__, nexttbtt,
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intval & ~HAL_BEACON_RESET_TSF,
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intval & ~ATH9K_BEACON_RESET_TSF,
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conf.beacon_interval);
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conf.beacon_interval);
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/*
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/*
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@ -937,17 +937,17 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
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* self-linked tx descriptor and let the hardware
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* self-linked tx descriptor and let the hardware
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* deal with things.
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* deal with things.
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*/
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*/
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intval |= HAL_BEACON_ENA;
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intval |= ATH9K_BEACON_ENA;
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if (!ah->ah_caps.halVEOLSupport)
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if (!ah->ah_caps.halVEOLSupport)
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sc->sc_imask |= HAL_INT_SWBA;
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sc->sc_imask |= ATH9K_INT_SWBA;
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ath_beaconq_config(sc);
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ath_beaconq_config(sc);
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} else if (sc->sc_opmode == HAL_M_HOSTAP) {
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} else if (sc->sc_opmode == ATH9K_M_HOSTAP) {
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/*
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/*
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* In AP mode we enable the beacon timers and
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* In AP mode we enable the beacon timers and
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* SWBA interrupts to prepare beacon frames.
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* SWBA interrupts to prepare beacon frames.
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*/
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*/
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intval |= HAL_BEACON_ENA;
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intval |= ATH9K_BEACON_ENA;
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sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
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sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */
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ath_beaconq_config(sc);
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ath_beaconq_config(sc);
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}
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}
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ath9k_hw_beaconinit(ah, nexttbtt, intval);
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ath9k_hw_beaconinit(ah, nexttbtt, intval);
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@ -957,7 +957,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
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* When using a self-linked beacon descriptor in
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* When using a self-linked beacon descriptor in
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* ibss mode load it once here.
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* ibss mode load it once here.
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*/
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*/
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if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
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if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport)
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ath_beacon_start_adhoc(sc, 0);
|
ath_beacon_start_adhoc(sc, 0);
|
||||||
}
|
}
|
||||||
#undef TSF_TO_TU
|
#undef TSF_TO_TU
|
||||||
|
@ -21,23 +21,23 @@
|
|||||||
|
|
||||||
static int ath_outdoor; /* enable outdoor use */
|
static int ath_outdoor; /* enable outdoor use */
|
||||||
|
|
||||||
static const u_int8_t ath_bcast_mac[ETH_ALEN] =
|
static const u8 ath_bcast_mac[ETH_ALEN] =
|
||||||
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
||||||
|
|
||||||
static u_int32_t ath_chainmask_sel_up_rssi_thres =
|
static u32 ath_chainmask_sel_up_rssi_thres =
|
||||||
ATH_CHAINMASK_SEL_UP_RSSI_THRES;
|
ATH_CHAINMASK_SEL_UP_RSSI_THRES;
|
||||||
static u_int32_t ath_chainmask_sel_down_rssi_thres =
|
static u32 ath_chainmask_sel_down_rssi_thres =
|
||||||
ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
|
ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
|
||||||
static u_int32_t ath_chainmask_sel_period =
|
static u32 ath_chainmask_sel_period =
|
||||||
ATH_CHAINMASK_SEL_TIMEOUT;
|
ATH_CHAINMASK_SEL_TIMEOUT;
|
||||||
|
|
||||||
/* return bus cachesize in 4B word units */
|
/* return bus cachesize in 4B word units */
|
||||||
|
|
||||||
static void bus_read_cachesize(struct ath_softc *sc, int *csz)
|
static void bus_read_cachesize(struct ath_softc *sc, int *csz)
|
||||||
{
|
{
|
||||||
u_int8_t u8tmp;
|
u8 u8tmp;
|
||||||
|
|
||||||
pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u_int8_t *)&u8tmp);
|
pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
|
||||||
*csz = (int)u8tmp;
|
*csz = (int)u8tmp;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -60,7 +60,7 @@ static void bus_read_cachesize(struct ath_softc *sc, int *csz)
|
|||||||
|
|
||||||
static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
|
static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
|
||||||
{
|
{
|
||||||
const struct hal_rate_table *rt;
|
const struct ath9k_rate_table *rt;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
|
memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
|
||||||
@ -68,11 +68,11 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
|
|||||||
BUG_ON(!rt);
|
BUG_ON(!rt);
|
||||||
|
|
||||||
for (i = 0; i < rt->rateCount; i++)
|
for (i = 0; i < rt->rateCount; i++)
|
||||||
sc->sc_rixmap[rt->info[i].rateCode] = (u_int8_t) i;
|
sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
|
||||||
|
|
||||||
memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
|
memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
|
||||||
for (i = 0; i < 256; i++) {
|
for (i = 0; i < 256; i++) {
|
||||||
u_int8_t ix = rt->rateCodeToIndex[i];
|
u8 ix = rt->rateCodeToIndex[i];
|
||||||
|
|
||||||
if (ix == 0xff)
|
if (ix == 0xff)
|
||||||
continue;
|
continue;
|
||||||
@ -110,7 +110,7 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
|
|||||||
static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
|
static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
const struct hal_rate_table *rt;
|
const struct ath9k_rate_table *rt;
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
case WIRELESS_MODE_11a:
|
case WIRELESS_MODE_11a:
|
||||||
@ -168,60 +168,89 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* Set up channel list
|
* Set up channel list
|
||||||
*
|
*/
|
||||||
* Determines the proper set of channelflags based on the selected mode,
|
static int ath_setup_channels(struct ath_softc *sc)
|
||||||
* allocates a channel array, and passes it to the HAL for initialization.
|
|
||||||
* If successful, the list is passed to the upper layer, then de-allocated.
|
|
||||||
*/
|
|
||||||
|
|
||||||
static int ath_getchannels(struct ath_softc *sc,
|
|
||||||
u_int cc,
|
|
||||||
bool outDoor,
|
|
||||||
bool xchanMode)
|
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
struct hal_channel *chans;
|
int nchan, i, a = 0, b = 0;
|
||||||
int nchan;
|
u8 regclassids[ATH_REGCLASSIDS_MAX];
|
||||||
u_int8_t regclassids[ATH_REGCLASSIDS_MAX];
|
u32 nregclass = 0;
|
||||||
u_int nregclass = 0;
|
struct ieee80211_supported_band *band_2ghz;
|
||||||
|
struct ieee80211_supported_band *band_5ghz;
|
||||||
chans = kmalloc(ATH_CHAN_MAX * sizeof(struct hal_channel), GFP_KERNEL);
|
struct ieee80211_channel *chan_2ghz;
|
||||||
if (chans == NULL) {
|
struct ieee80211_channel *chan_5ghz;
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
struct ath9k_channel *c;
|
||||||
"%s: unable to allocate channel table\n", __func__);
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
/* Fill in ah->ah_channels */
|
||||||
if (!ath9k_regd_init_channels(ah,
|
if (!ath9k_regd_init_channels(ah,
|
||||||
chans,
|
|
||||||
ATH_CHAN_MAX,
|
ATH_CHAN_MAX,
|
||||||
(u_int *)&nchan,
|
(u32 *)&nchan,
|
||||||
regclassids,
|
regclassids,
|
||||||
ATH_REGCLASSIDS_MAX,
|
ATH_REGCLASSIDS_MAX,
|
||||||
&nregclass,
|
&nregclass,
|
||||||
cc,
|
CTRY_DEFAULT,
|
||||||
ATH9K_MODE_SEL_ALL,
|
ATH9K_MODE_SEL_ALL,
|
||||||
outDoor,
|
false,
|
||||||
xchanMode)) {
|
1)) {
|
||||||
u_int32_t rd = ah->ah_currentRD;
|
u32 rd = ah->ah_currentRD;
|
||||||
|
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: unable to collect channel list from hal; "
|
"%s: unable to collect channel list; "
|
||||||
"regdomain likely %u country code %u\n",
|
"regdomain likely %u country code %u\n",
|
||||||
__func__, rd, cc);
|
__func__, rd, CTRY_DEFAULT);
|
||||||
kfree(chans);
|
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
ath_setup_channel_list(sc,
|
band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
|
||||||
CLIST_UPDATE,
|
band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
|
||||||
chans,
|
chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
|
||||||
nchan,
|
chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
|
||||||
regclassids,
|
|
||||||
nregclass,
|
for (i = 0; i < nchan; i++) {
|
||||||
CTRY_DEFAULT);
|
c = &ah->ah_channels[i];
|
||||||
|
if (IS_CHAN_2GHZ(c)) {
|
||||||
|
chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
|
||||||
|
chan_2ghz[a].center_freq = c->channel;
|
||||||
|
chan_2ghz[a].max_power = c->maxTxPower;
|
||||||
|
|
||||||
|
if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
|
||||||
|
chan_2ghz[a].flags |=
|
||||||
|
IEEE80211_CHAN_NO_IBSS;
|
||||||
|
if (c->channelFlags & CHANNEL_PASSIVE)
|
||||||
|
chan_2ghz[a].flags |=
|
||||||
|
IEEE80211_CHAN_PASSIVE_SCAN;
|
||||||
|
|
||||||
|
band_2ghz->n_channels = ++a;
|
||||||
|
|
||||||
|
DPRINTF(sc, ATH_DBG_CONFIG,
|
||||||
|
"%s: 2MHz channel: %d, "
|
||||||
|
"channelFlags: 0x%x\n",
|
||||||
|
__func__,
|
||||||
|
c->channel,
|
||||||
|
c->channelFlags);
|
||||||
|
} else if (IS_CHAN_5GHZ(c)) {
|
||||||
|
chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
|
||||||
|
chan_5ghz[b].center_freq = c->channel;
|
||||||
|
chan_5ghz[b].max_power = c->maxTxPower;
|
||||||
|
|
||||||
|
if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
|
||||||
|
chan_5ghz[b].flags |=
|
||||||
|
IEEE80211_CHAN_NO_IBSS;
|
||||||
|
if (c->channelFlags & CHANNEL_PASSIVE)
|
||||||
|
chan_5ghz[b].flags |=
|
||||||
|
IEEE80211_CHAN_PASSIVE_SCAN;
|
||||||
|
|
||||||
|
band_5ghz->n_channels = ++b;
|
||||||
|
|
||||||
|
DPRINTF(sc, ATH_DBG_CONFIG,
|
||||||
|
"%s: 5MHz channel: %d, "
|
||||||
|
"channelFlags: 0x%x\n",
|
||||||
|
__func__,
|
||||||
|
c->channel,
|
||||||
|
c->channelFlags);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
kfree(chans);
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -233,29 +262,25 @@ static int ath_getchannels(struct ath_softc *sc,
|
|||||||
* exist, the lowest mode (11b) is selected.
|
* exist, the lowest mode (11b) is selected.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static enum wireless_mode ath_chan2mode(struct hal_channel *chan)
|
static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
if ((chan->channelFlags & CHANNEL_A) == CHANNEL_A)
|
if (chan->chanmode == CHANNEL_A)
|
||||||
return WIRELESS_MODE_11a;
|
return WIRELESS_MODE_11a;
|
||||||
else if ((chan->channelFlags & CHANNEL_G) == CHANNEL_G)
|
else if (chan->chanmode == CHANNEL_G)
|
||||||
return WIRELESS_MODE_11g;
|
return WIRELESS_MODE_11g;
|
||||||
else if ((chan->channelFlags & CHANNEL_B) == CHANNEL_B)
|
else if (chan->chanmode == CHANNEL_B)
|
||||||
return WIRELESS_MODE_11b;
|
return WIRELESS_MODE_11b;
|
||||||
else if ((chan->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20)
|
else if (chan->chanmode == CHANNEL_A_HT20)
|
||||||
return WIRELESS_MODE_11NA_HT20;
|
return WIRELESS_MODE_11NA_HT20;
|
||||||
else if ((chan->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20)
|
else if (chan->chanmode == CHANNEL_G_HT20)
|
||||||
return WIRELESS_MODE_11NG_HT20;
|
return WIRELESS_MODE_11NG_HT20;
|
||||||
else if ((chan->channelFlags & CHANNEL_A_HT40PLUS) ==
|
else if (chan->chanmode == CHANNEL_A_HT40PLUS)
|
||||||
CHANNEL_A_HT40PLUS)
|
|
||||||
return WIRELESS_MODE_11NA_HT40PLUS;
|
return WIRELESS_MODE_11NA_HT40PLUS;
|
||||||
else if ((chan->channelFlags & CHANNEL_A_HT40MINUS) ==
|
else if (chan->chanmode == CHANNEL_A_HT40MINUS)
|
||||||
CHANNEL_A_HT40MINUS)
|
|
||||||
return WIRELESS_MODE_11NA_HT40MINUS;
|
return WIRELESS_MODE_11NA_HT40MINUS;
|
||||||
else if ((chan->channelFlags & CHANNEL_G_HT40PLUS) ==
|
else if (chan->chanmode == CHANNEL_G_HT40PLUS)
|
||||||
CHANNEL_G_HT40PLUS)
|
|
||||||
return WIRELESS_MODE_11NG_HT40PLUS;
|
return WIRELESS_MODE_11NG_HT40PLUS;
|
||||||
else if ((chan->channelFlags & CHANNEL_G_HT40MINUS) ==
|
else if (chan->chanmode == CHANNEL_G_HT40MINUS)
|
||||||
CHANNEL_G_HT40MINUS)
|
|
||||||
return WIRELESS_MODE_11NG_HT40MINUS;
|
return WIRELESS_MODE_11NG_HT40MINUS;
|
||||||
|
|
||||||
/* NB: should not get here */
|
/* NB: should not get here */
|
||||||
@ -269,7 +294,7 @@ static enum wireless_mode ath_chan2mode(struct hal_channel *chan)
|
|||||||
* the current operating mode for the new channel.
|
* the current operating mode for the new channel.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static void ath_chan_change(struct ath_softc *sc, struct hal_channel *chan)
|
static void ath_chan_change(struct ath_softc *sc, struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
enum wireless_mode mode;
|
enum wireless_mode mode;
|
||||||
|
|
||||||
@ -332,8 +357,8 @@ static int ath_stop(struct ath_softc *sc)
|
|||||||
void ath_scan_start(struct ath_softc *sc)
|
void ath_scan_start(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
u_int32_t rfilt;
|
u32 rfilt;
|
||||||
u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
|
u32 now = (u32) jiffies_to_msecs(get_timestamp());
|
||||||
|
|
||||||
sc->sc_scanning = 1;
|
sc->sc_scanning = 1;
|
||||||
rfilt = ath_calcrxfilter(sc);
|
rfilt = ath_calcrxfilter(sc);
|
||||||
@ -357,8 +382,8 @@ void ath_scan_start(struct ath_softc *sc)
|
|||||||
void ath_scan_end(struct ath_softc *sc)
|
void ath_scan_end(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
u_int32_t rfilt;
|
u32 rfilt;
|
||||||
u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
|
u32 now = (u32) jiffies_to_msecs(get_timestamp());
|
||||||
|
|
||||||
sc->sc_scanning = 0;
|
sc->sc_scanning = 0;
|
||||||
/* Request for a full reset due to rx packet filter changes */
|
/* Request for a full reset due to rx packet filter changes */
|
||||||
@ -378,11 +403,11 @@ void ath_scan_end(struct ath_softc *sc)
|
|||||||
* by reseting the chip. To accomplish this we must first cleanup any pending
|
* by reseting the chip. To accomplish this we must first cleanup any pending
|
||||||
* DMA, then restart stuff after a la ath_init.
|
* DMA, then restart stuff after a la ath_init.
|
||||||
*/
|
*/
|
||||||
int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
|
int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
bool fastcc = true, stopped;
|
bool fastcc = true, stopped;
|
||||||
enum hal_ht_macmode ht_macmode;
|
enum ath9k_ht_macmode ht_macmode;
|
||||||
|
|
||||||
if (sc->sc_invalid) /* if the device is invalid or removed */
|
if (sc->sc_invalid) /* if the device is invalid or removed */
|
||||||
return -EIO;
|
return -EIO;
|
||||||
@ -401,7 +426,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
|
|||||||
if (hchan->channel != sc->sc_curchan.channel ||
|
if (hchan->channel != sc->sc_curchan.channel ||
|
||||||
hchan->channelFlags != sc->sc_curchan.channelFlags ||
|
hchan->channelFlags != sc->sc_curchan.channelFlags ||
|
||||||
sc->sc_update_chainmask || sc->sc_full_reset) {
|
sc->sc_update_chainmask || sc->sc_full_reset) {
|
||||||
enum hal_status status;
|
int status;
|
||||||
/*
|
/*
|
||||||
* This is only performed if the channel settings have
|
* This is only performed if the channel settings have
|
||||||
* actually changed.
|
* actually changed.
|
||||||
@ -580,7 +605,7 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
|
|||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
struct ath_vap *avp;
|
struct ath_vap *avp;
|
||||||
u_int32_t rfilt = 0;
|
u32 rfilt = 0;
|
||||||
DECLARE_MAC_BUF(mac);
|
DECLARE_MAC_BUF(mac);
|
||||||
|
|
||||||
avp = sc->sc_vaps[if_id];
|
avp = sc->sc_vaps[if_id];
|
||||||
@ -595,12 +620,12 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* update ratectrl about the new state */
|
/* update ratectrl about the new state */
|
||||||
ath_rate_newstate(sc, avp, 0);
|
ath_rate_newstate(sc, avp);
|
||||||
|
|
||||||
rfilt = ath_calcrxfilter(sc);
|
rfilt = ath_calcrxfilter(sc);
|
||||||
ath9k_hw_setrxfilter(ah, rfilt);
|
ath9k_hw_setrxfilter(ah, rfilt);
|
||||||
|
|
||||||
if (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS) {
|
if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) {
|
||||||
memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
|
memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
|
||||||
ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
|
ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
|
||||||
} else
|
} else
|
||||||
@ -616,8 +641,8 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
|
|||||||
* Disable BMISS interrupt when we're not associated
|
* Disable BMISS interrupt when we're not associated
|
||||||
*/
|
*/
|
||||||
ath9k_hw_set_interrupts(ah,
|
ath9k_hw_set_interrupts(ah,
|
||||||
sc->sc_imask & ~(HAL_INT_SWBA | HAL_INT_BMISS));
|
sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
|
||||||
sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
|
sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
|
||||||
/* need to reconfigure the beacons when it moves to RUN */
|
/* need to reconfigure the beacons when it moves to RUN */
|
||||||
sc->sc_beacons = 0;
|
sc->sc_beacons = 0;
|
||||||
|
|
||||||
@ -627,7 +652,7 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
|
|||||||
int ath_vap_attach(struct ath_softc *sc,
|
int ath_vap_attach(struct ath_softc *sc,
|
||||||
int if_id,
|
int if_id,
|
||||||
struct ieee80211_vif *if_data,
|
struct ieee80211_vif *if_data,
|
||||||
enum hal_opmode opmode)
|
enum ath9k_opmode opmode)
|
||||||
{
|
{
|
||||||
struct ath_vap *avp;
|
struct ath_vap *avp;
|
||||||
|
|
||||||
@ -638,11 +663,11 @@ int ath_vap_attach(struct ath_softc *sc,
|
|||||||
}
|
}
|
||||||
|
|
||||||
switch (opmode) {
|
switch (opmode) {
|
||||||
case HAL_M_STA:
|
case ATH9K_M_STA:
|
||||||
case HAL_M_IBSS:
|
case ATH9K_M_IBSS:
|
||||||
case HAL_M_MONITOR:
|
case ATH9K_M_MONITOR:
|
||||||
break;
|
break;
|
||||||
case HAL_M_HOSTAP:
|
case ATH9K_M_HOSTAP:
|
||||||
/* XXX not right, beacon buffer is allocated on RUN trans */
|
/* XXX not right, beacon buffer is allocated on RUN trans */
|
||||||
if (list_empty(&sc->sc_bbuf))
|
if (list_empty(&sc->sc_bbuf))
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
@ -737,12 +762,12 @@ int ath_vap_config(struct ath_softc *sc,
|
|||||||
/* Core */
|
/* Core */
|
||||||
/********/
|
/********/
|
||||||
|
|
||||||
int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
|
int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
enum hal_status status;
|
int status;
|
||||||
int error = 0;
|
int error = 0;
|
||||||
enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
|
enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
|
||||||
|
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
|
DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
|
||||||
|
|
||||||
@ -801,32 +826,32 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
|
|||||||
goto done;
|
goto done;
|
||||||
}
|
}
|
||||||
/* Setup our intr mask. */
|
/* Setup our intr mask. */
|
||||||
sc->sc_imask = HAL_INT_RX | HAL_INT_TX
|
sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
|
||||||
| HAL_INT_RXEOL | HAL_INT_RXORN
|
| ATH9K_INT_RXEOL | ATH9K_INT_RXORN
|
||||||
| HAL_INT_FATAL | HAL_INT_GLOBAL;
|
| ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
|
||||||
|
|
||||||
if (ah->ah_caps.halGTTSupport)
|
if (ah->ah_caps.halGTTSupport)
|
||||||
sc->sc_imask |= HAL_INT_GTT;
|
sc->sc_imask |= ATH9K_INT_GTT;
|
||||||
|
|
||||||
if (ah->ah_caps.halHTSupport)
|
if (ah->ah_caps.halHTSupport)
|
||||||
sc->sc_imask |= HAL_INT_CST;
|
sc->sc_imask |= ATH9K_INT_CST;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Enable MIB interrupts when there are hardware phy counters.
|
* Enable MIB interrupts when there are hardware phy counters.
|
||||||
* Note we only do this (at the moment) for station mode.
|
* Note we only do this (at the moment) for station mode.
|
||||||
*/
|
*/
|
||||||
if (ath9k_hw_phycounters(ah) &&
|
if (ath9k_hw_phycounters(ah) &&
|
||||||
((sc->sc_opmode == HAL_M_STA) || (sc->sc_opmode == HAL_M_IBSS)))
|
((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS)))
|
||||||
sc->sc_imask |= HAL_INT_MIB;
|
sc->sc_imask |= ATH9K_INT_MIB;
|
||||||
/*
|
/*
|
||||||
* Some hardware processes the TIM IE and fires an
|
* Some hardware processes the TIM IE and fires an
|
||||||
* interrupt when the TIM bit is set. For hardware
|
* interrupt when the TIM bit is set. For hardware
|
||||||
* that does, if not overridden by configuration,
|
* that does, if not overridden by configuration,
|
||||||
* enable the TIM interrupt when operating as station.
|
* enable the TIM interrupt when operating as station.
|
||||||
*/
|
*/
|
||||||
if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == HAL_M_STA &&
|
if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == ATH9K_M_STA &&
|
||||||
!sc->sc_config.swBeaconProcess)
|
!sc->sc_config.swBeaconProcess)
|
||||||
sc->sc_imask |= HAL_INT_TIM;
|
sc->sc_imask |= ATH9K_INT_TIM;
|
||||||
/*
|
/*
|
||||||
* Don't enable interrupts here as we've not yet built our
|
* Don't enable interrupts here as we've not yet built our
|
||||||
* vap and node data structures, which will be needed as soon
|
* vap and node data structures, which will be needed as soon
|
||||||
@ -849,7 +874,7 @@ done:
|
|||||||
* and to reset the hardware when rf gain settings must be reset.
|
* and to reset the hardware when rf gain settings must be reset.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static int ath_reset_start(struct ath_softc *sc, u_int32_t flag)
|
static int ath_reset_start(struct ath_softc *sc, u32 flag)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
|
|
||||||
@ -861,7 +886,7 @@ static int ath_reset_start(struct ath_softc *sc, u_int32_t flag)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
|
static int ath_reset_end(struct ath_softc *sc, u32 flag)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
|
|
||||||
@ -885,7 +910,7 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
|
|||||||
/* Restart the txq */
|
/* Restart the txq */
|
||||||
if (flag & RESET_RETRY_TXQ) {
|
if (flag & RESET_RETRY_TXQ) {
|
||||||
int i;
|
int i;
|
||||||
for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
|
||||||
if (ATH_TXQ_SETUP(sc, i)) {
|
if (ATH_TXQ_SETUP(sc, i)) {
|
||||||
spin_lock_bh(&sc->sc_txq[i].axq_lock);
|
spin_lock_bh(&sc->sc_txq[i].axq_lock);
|
||||||
ath_txq_schedule(sc, &sc->sc_txq[i]);
|
ath_txq_schedule(sc, &sc->sc_txq[i]);
|
||||||
@ -899,9 +924,9 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
|
|||||||
int ath_reset(struct ath_softc *sc)
|
int ath_reset(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
enum hal_status status;
|
int status;
|
||||||
int error = 0;
|
int error = 0;
|
||||||
enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
|
enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
|
||||||
|
|
||||||
/* NB: indicate channel change so we do a full reset */
|
/* NB: indicate channel change so we do a full reset */
|
||||||
spin_lock_bh(&sc->sc_resetlock);
|
spin_lock_bh(&sc->sc_resetlock);
|
||||||
@ -949,7 +974,7 @@ irqreturn_t ath_isr(int irq, void *dev)
|
|||||||
{
|
{
|
||||||
struct ath_softc *sc = dev;
|
struct ath_softc *sc = dev;
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
enum hal_int status;
|
enum ath9k_int status;
|
||||||
bool sched = false;
|
bool sched = false;
|
||||||
|
|
||||||
do {
|
do {
|
||||||
@ -985,18 +1010,18 @@ irqreturn_t ath_isr(int irq, void *dev)
|
|||||||
|
|
||||||
sc->sc_intrstatus = status;
|
sc->sc_intrstatus = status;
|
||||||
|
|
||||||
if (status & HAL_INT_FATAL) {
|
if (status & ATH9K_INT_FATAL) {
|
||||||
/* need a chip reset */
|
/* need a chip reset */
|
||||||
sched = true;
|
sched = true;
|
||||||
} else if (status & HAL_INT_RXORN) {
|
} else if (status & ATH9K_INT_RXORN) {
|
||||||
/* need a chip reset */
|
/* need a chip reset */
|
||||||
sched = true;
|
sched = true;
|
||||||
} else {
|
} else {
|
||||||
if (status & HAL_INT_SWBA) {
|
if (status & ATH9K_INT_SWBA) {
|
||||||
/* schedule a tasklet for beacon handling */
|
/* schedule a tasklet for beacon handling */
|
||||||
tasklet_schedule(&sc->bcon_tasklet);
|
tasklet_schedule(&sc->bcon_tasklet);
|
||||||
}
|
}
|
||||||
if (status & HAL_INT_RXEOL) {
|
if (status & ATH9K_INT_RXEOL) {
|
||||||
/*
|
/*
|
||||||
* NB: the hardware should re-read the link when
|
* NB: the hardware should re-read the link when
|
||||||
* RXE bit is written, but it doesn't work
|
* RXE bit is written, but it doesn't work
|
||||||
@ -1005,20 +1030,20 @@ irqreturn_t ath_isr(int irq, void *dev)
|
|||||||
sched = true;
|
sched = true;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (status & HAL_INT_TXURN)
|
if (status & ATH9K_INT_TXURN)
|
||||||
/* bump tx trigger level */
|
/* bump tx trigger level */
|
||||||
ath9k_hw_updatetxtriglevel(ah, true);
|
ath9k_hw_updatetxtriglevel(ah, true);
|
||||||
/* XXX: optimize this */
|
/* XXX: optimize this */
|
||||||
if (status & HAL_INT_RX)
|
if (status & ATH9K_INT_RX)
|
||||||
sched = true;
|
sched = true;
|
||||||
if (status & HAL_INT_TX)
|
if (status & ATH9K_INT_TX)
|
||||||
sched = true;
|
sched = true;
|
||||||
if (status & HAL_INT_BMISS)
|
if (status & ATH9K_INT_BMISS)
|
||||||
sched = true;
|
sched = true;
|
||||||
/* carrier sense timeout */
|
/* carrier sense timeout */
|
||||||
if (status & HAL_INT_CST)
|
if (status & ATH9K_INT_CST)
|
||||||
sched = true;
|
sched = true;
|
||||||
if (status & HAL_INT_MIB) {
|
if (status & ATH9K_INT_MIB) {
|
||||||
/*
|
/*
|
||||||
* Disable interrupts until we service the MIB
|
* Disable interrupts until we service the MIB
|
||||||
* interrupt; otherwise it will continue to
|
* interrupt; otherwise it will continue to
|
||||||
@ -1033,7 +1058,7 @@ irqreturn_t ath_isr(int irq, void *dev)
|
|||||||
ath9k_hw_procmibevent(ah, &sc->sc_halstats);
|
ath9k_hw_procmibevent(ah, &sc->sc_halstats);
|
||||||
ath9k_hw_set_interrupts(ah, sc->sc_imask);
|
ath9k_hw_set_interrupts(ah, sc->sc_imask);
|
||||||
}
|
}
|
||||||
if (status & HAL_INT_TIM_TIMER) {
|
if (status & ATH9K_INT_TIM_TIMER) {
|
||||||
if (!ah->ah_caps.halAutoSleepSupport) {
|
if (!ah->ah_caps.halAutoSleepSupport) {
|
||||||
/* Clear RxAbort bit so that we can
|
/* Clear RxAbort bit so that we can
|
||||||
* receive frames */
|
* receive frames */
|
||||||
@ -1046,7 +1071,7 @@ irqreturn_t ath_isr(int irq, void *dev)
|
|||||||
|
|
||||||
if (sched) {
|
if (sched) {
|
||||||
/* turn off every interrupt except SWBA */
|
/* turn off every interrupt except SWBA */
|
||||||
ath9k_hw_set_interrupts(ah, (sc->sc_imask & HAL_INT_SWBA));
|
ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
|
||||||
tasklet_schedule(&sc->intr_tq);
|
tasklet_schedule(&sc->intr_tq);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1058,20 +1083,21 @@ irqreturn_t ath_isr(int irq, void *dev)
|
|||||||
static void ath9k_tasklet(unsigned long data)
|
static void ath9k_tasklet(unsigned long data)
|
||||||
{
|
{
|
||||||
struct ath_softc *sc = (struct ath_softc *)data;
|
struct ath_softc *sc = (struct ath_softc *)data;
|
||||||
u_int32_t status = sc->sc_intrstatus;
|
u32 status = sc->sc_intrstatus;
|
||||||
|
|
||||||
if (status & HAL_INT_FATAL) {
|
if (status & ATH9K_INT_FATAL) {
|
||||||
/* need a chip reset */
|
/* need a chip reset */
|
||||||
ath_internal_reset(sc);
|
ath_internal_reset(sc);
|
||||||
return;
|
return;
|
||||||
} else {
|
} else {
|
||||||
|
|
||||||
if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
|
if (status &
|
||||||
|
(ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
|
||||||
/* XXX: fill me in */
|
/* XXX: fill me in */
|
||||||
/*
|
/*
|
||||||
if (status & HAL_INT_RXORN) {
|
if (status & ATH9K_INT_RXORN) {
|
||||||
}
|
}
|
||||||
if (status & HAL_INT_RXEOL) {
|
if (status & ATH9K_INT_RXEOL) {
|
||||||
}
|
}
|
||||||
*/
|
*/
|
||||||
spin_lock_bh(&sc->sc_rxflushlock);
|
spin_lock_bh(&sc->sc_rxflushlock);
|
||||||
@ -1079,16 +1105,16 @@ static void ath9k_tasklet(unsigned long data)
|
|||||||
spin_unlock_bh(&sc->sc_rxflushlock);
|
spin_unlock_bh(&sc->sc_rxflushlock);
|
||||||
}
|
}
|
||||||
/* XXX: optimize this */
|
/* XXX: optimize this */
|
||||||
if (status & HAL_INT_TX)
|
if (status & ATH9K_INT_TX)
|
||||||
ath_tx_tasklet(sc);
|
ath_tx_tasklet(sc);
|
||||||
/* XXX: fill me in */
|
/* XXX: fill me in */
|
||||||
/*
|
/*
|
||||||
if (status & HAL_INT_BMISS) {
|
if (status & ATH9K_INT_BMISS) {
|
||||||
}
|
}
|
||||||
if (status & (HAL_INT_TIM | HAL_INT_DTIMSYNC)) {
|
if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
|
||||||
if (status & HAL_INT_TIM) {
|
if (status & ATH9K_INT_TIM) {
|
||||||
}
|
}
|
||||||
if (status & HAL_INT_DTIMSYNC) {
|
if (status & ATH9K_INT_DTIMSYNC) {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
*/
|
*/
|
||||||
@ -1098,13 +1124,13 @@ static void ath9k_tasklet(unsigned long data)
|
|||||||
ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
|
ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
|
||||||
}
|
}
|
||||||
|
|
||||||
int ath_init(u_int16_t devid, struct ath_softc *sc)
|
int ath_init(u16 devid, struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = NULL;
|
struct ath_hal *ah = NULL;
|
||||||
enum hal_status status;
|
int status;
|
||||||
int error = 0, i;
|
int error = 0, i;
|
||||||
int csz = 0;
|
int csz = 0;
|
||||||
u_int32_t rd;
|
u32 rd;
|
||||||
|
|
||||||
/* XXX: hardware will not be ready until ath_open() being called */
|
/* XXX: hardware will not be ready until ath_open() being called */
|
||||||
sc->sc_invalid = 1;
|
sc->sc_invalid = 1;
|
||||||
@ -1154,7 +1180,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
* reset the contents on initial power up.
|
* reset the contents on initial power up.
|
||||||
*/
|
*/
|
||||||
for (i = 0; i < sc->sc_keymax; i++)
|
for (i = 0; i < sc->sc_keymax; i++)
|
||||||
ath9k_hw_keyreset(ah, (u_int16_t) i);
|
ath9k_hw_keyreset(ah, (u16) i);
|
||||||
/*
|
/*
|
||||||
* Mark key cache slots associated with global keys
|
* Mark key cache slots associated with global keys
|
||||||
* as in use. If we knew TKIP was not to be used we
|
* as in use. If we knew TKIP was not to be used we
|
||||||
@ -1175,15 +1201,12 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
*/
|
*/
|
||||||
rd = ah->ah_currentRD;
|
rd = ah->ah_currentRD;
|
||||||
|
|
||||||
error = ath_getchannels(sc,
|
error = ath_setup_channels(sc);
|
||||||
CTRY_DEFAULT,
|
|
||||||
ath_outdoor,
|
|
||||||
1);
|
|
||||||
if (error)
|
if (error)
|
||||||
goto bad;
|
goto bad;
|
||||||
|
|
||||||
/* default to STA mode */
|
/* default to STA mode */
|
||||||
sc->sc_opmode = HAL_M_MONITOR;
|
sc->sc_opmode = ATH9K_M_MONITOR;
|
||||||
|
|
||||||
/* Setup rate tables for all potential media types. */
|
/* Setup rate tables for all potential media types. */
|
||||||
/* 11g encompasses b,g */
|
/* 11g encompasses b,g */
|
||||||
@ -1207,7 +1230,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
error = -EIO;
|
error = -EIO;
|
||||||
goto bad2;
|
goto bad2;
|
||||||
}
|
}
|
||||||
sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
|
sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
|
||||||
if (sc->sc_cabq == NULL) {
|
if (sc->sc_cabq == NULL) {
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: unable to setup CAB xmit queue\n", __func__);
|
"%s: unable to setup CAB xmit queue\n", __func__);
|
||||||
@ -1223,7 +1246,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
|
|
||||||
/* Setup data queues */
|
/* Setup data queues */
|
||||||
/* NB: ensure BK queue is the lowest priority h/w queue */
|
/* NB: ensure BK queue is the lowest priority h/w queue */
|
||||||
if (!ath_tx_setup(sc, HAL_WME_AC_BK)) {
|
if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: unable to setup xmit queue for BK traffic\n",
|
"%s: unable to setup xmit queue for BK traffic\n",
|
||||||
__func__);
|
__func__);
|
||||||
@ -1231,21 +1254,21 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
goto bad2;
|
goto bad2;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!ath_tx_setup(sc, HAL_WME_AC_BE)) {
|
if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: unable to setup xmit queue for BE traffic\n",
|
"%s: unable to setup xmit queue for BE traffic\n",
|
||||||
__func__);
|
__func__);
|
||||||
error = -EIO;
|
error = -EIO;
|
||||||
goto bad2;
|
goto bad2;
|
||||||
}
|
}
|
||||||
if (!ath_tx_setup(sc, HAL_WME_AC_VI)) {
|
if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: unable to setup xmit queue for VI traffic\n",
|
"%s: unable to setup xmit queue for VI traffic\n",
|
||||||
__func__);
|
__func__);
|
||||||
error = -EIO;
|
error = -EIO;
|
||||||
goto bad2;
|
goto bad2;
|
||||||
}
|
}
|
||||||
if (!ath_tx_setup(sc, HAL_WME_AC_VO)) {
|
if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: unable to setup xmit queue for VO traffic\n",
|
"%s: unable to setup xmit queue for VO traffic\n",
|
||||||
__func__);
|
__func__);
|
||||||
@ -1259,7 +1282,8 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
goto bad2;
|
goto bad2;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_TKIP, NULL)) {
|
if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
|
||||||
|
ATH9K_CIPHER_TKIP, NULL)) {
|
||||||
/*
|
/*
|
||||||
* Whether we should enable h/w TKIP MIC.
|
* Whether we should enable h/w TKIP MIC.
|
||||||
* XXX: if we don't support WME TKIP MIC, then we wouldn't
|
* XXX: if we don't support WME TKIP MIC, then we wouldn't
|
||||||
@ -1275,14 +1299,16 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
* With split mic keys the number of stations is limited
|
* With split mic keys the number of stations is limited
|
||||||
* to 27 otherwise 59.
|
* to 27 otherwise 59.
|
||||||
*/
|
*/
|
||||||
if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_TKIP, NULL)
|
if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
|
||||||
&& ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, HAL_CIPHER_MIC, NULL)
|
ATH9K_CIPHER_TKIP, NULL)
|
||||||
&& ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT, 0, NULL))
|
&& ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
|
||||||
|
ATH9K_CIPHER_MIC, NULL)
|
||||||
|
&& ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT,
|
||||||
|
0, NULL))
|
||||||
sc->sc_splitmic = 1;
|
sc->sc_splitmic = 1;
|
||||||
|
|
||||||
/* turn on mcast key search if possible */
|
/* turn on mcast key search if possible */
|
||||||
if (ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL)
|
if (!ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL))
|
||||||
== HAL_OK)
|
|
||||||
(void)ath9k_hw_setcapability(ah, HAL_CAP_MCAST_KEYSRCH, 1,
|
(void)ath9k_hw_setcapability(ah, HAL_CAP_MCAST_KEYSRCH, 1,
|
||||||
1, NULL);
|
1, NULL);
|
||||||
|
|
||||||
@ -1314,7 +1340,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
|
ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
|
||||||
ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
|
ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
|
||||||
}
|
}
|
||||||
sc->sc_slottime = HAL_SLOT_TIME_9; /* default to short slot time */
|
sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
|
||||||
|
|
||||||
/* initialize beacon slots */
|
/* initialize beacon slots */
|
||||||
for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
|
for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
|
||||||
@ -1331,7 +1357,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
|
|||||||
return 0;
|
return 0;
|
||||||
bad2:
|
bad2:
|
||||||
/* cleanup tx queues */
|
/* cleanup tx queues */
|
||||||
for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
|
||||||
if (ATH_TXQ_SETUP(sc, i))
|
if (ATH_TXQ_SETUP(sc, i))
|
||||||
ath_tx_cleanupq(sc, &sc->sc_txq[i]);
|
ath_tx_cleanupq(sc, &sc->sc_txq[i]);
|
||||||
bad:
|
bad:
|
||||||
@ -1349,10 +1375,10 @@ void ath_deinit(struct ath_softc *sc)
|
|||||||
|
|
||||||
ath_stop(sc);
|
ath_stop(sc);
|
||||||
if (!sc->sc_invalid)
|
if (!sc->sc_invalid)
|
||||||
ath9k_hw_setpower(sc->sc_ah, HAL_PM_AWAKE);
|
ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
|
||||||
ath_rate_detach(sc->sc_rc);
|
ath_rate_detach(sc->sc_rc);
|
||||||
/* cleanup tx queues */
|
/* cleanup tx queues */
|
||||||
for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
|
||||||
if (ATH_TXQ_SETUP(sc, i))
|
if (ATH_TXQ_SETUP(sc, i))
|
||||||
ath_tx_cleanupq(sc, &sc->sc_txq[i]);
|
ath_tx_cleanupq(sc, &sc->sc_txq[i]);
|
||||||
ath9k_hw_detach(ah);
|
ath9k_hw_detach(ah);
|
||||||
@ -1488,7 +1514,7 @@ void ath_newassoc(struct ath_softc *sc,
|
|||||||
/* Encryption */
|
/* Encryption */
|
||||||
/**************/
|
/**************/
|
||||||
|
|
||||||
void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
|
void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
|
||||||
{
|
{
|
||||||
ath9k_hw_keyreset(sc->sc_ah, keyix);
|
ath9k_hw_keyreset(sc->sc_ah, keyix);
|
||||||
if (freeslot)
|
if (freeslot)
|
||||||
@ -1496,9 +1522,9 @@ void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
|
|||||||
}
|
}
|
||||||
|
|
||||||
int ath_keyset(struct ath_softc *sc,
|
int ath_keyset(struct ath_softc *sc,
|
||||||
u_int16_t keyix,
|
u16 keyix,
|
||||||
struct hal_keyval *hk,
|
struct ath9k_keyval *hk,
|
||||||
const u_int8_t mac[ETH_ALEN])
|
const u8 mac[ETH_ALEN])
|
||||||
{
|
{
|
||||||
bool status;
|
bool status;
|
||||||
|
|
||||||
@ -1522,7 +1548,7 @@ int ath_keyset(struct ath_softc *sc,
|
|||||||
void ath_update_txpow(struct ath_softc *sc)
|
void ath_update_txpow(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
u_int32_t txpow;
|
u32 txpow;
|
||||||
|
|
||||||
if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
|
if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
|
||||||
ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
|
ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
|
||||||
@ -1534,7 +1560,7 @@ void ath_update_txpow(struct ath_softc *sc)
|
|||||||
|
|
||||||
/* Return the current country and domain information */
|
/* Return the current country and domain information */
|
||||||
void ath_get_currentCountry(struct ath_softc *sc,
|
void ath_get_currentCountry(struct ath_softc *sc,
|
||||||
struct hal_country_entry *ctry)
|
struct ath9k_country_entry *ctry)
|
||||||
{
|
{
|
||||||
ath9k_regd_get_current_country(sc->sc_ah, ctry);
|
ath9k_regd_get_current_country(sc->sc_ah, ctry);
|
||||||
|
|
||||||
@ -1572,8 +1598,8 @@ void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
|
|||||||
}
|
}
|
||||||
|
|
||||||
void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
|
void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
|
||||||
u_int8_t num_antcfg,
|
u8 num_antcfg,
|
||||||
const u_int8_t *bssid)
|
const u8 *bssid)
|
||||||
{
|
{
|
||||||
antdiv->antdiv_num_antcfg =
|
antdiv->antdiv_num_antcfg =
|
||||||
num_antcfg < ATH_ANT_DIV_MAX_CFG ?
|
num_antcfg < ATH_ANT_DIV_MAX_CFG ?
|
||||||
@ -1594,10 +1620,10 @@ void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static int32_t ath_find_max_val(int32_t *val,
|
static int32_t ath_find_max_val(int32_t *val,
|
||||||
u_int8_t num_val, u_int8_t *max_index)
|
u8 num_val, u8 *max_index)
|
||||||
{
|
{
|
||||||
u_int32_t MaxVal = *val++;
|
u32 MaxVal = *val++;
|
||||||
u_int32_t cur_index = 0;
|
u32 cur_index = 0;
|
||||||
|
|
||||||
*max_index = 0;
|
*max_index = 0;
|
||||||
while (++cur_index < num_val) {
|
while (++cur_index < num_val) {
|
||||||
@ -1618,8 +1644,8 @@ void ath_slow_ant_div(struct ath_antdiv *antdiv,
|
|||||||
{
|
{
|
||||||
struct ath_softc *sc = antdiv->antdiv_sc;
|
struct ath_softc *sc = antdiv->antdiv_sc;
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
u_int64_t curtsf = 0;
|
u64 curtsf = 0;
|
||||||
u_int8_t bestcfg, curcfg = antdiv->antdiv_curcfg;
|
u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
|
||||||
__le16 fc = hdr->frame_control;
|
__le16 fc = hdr->frame_control;
|
||||||
|
|
||||||
if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
|
if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
|
||||||
@ -1642,7 +1668,7 @@ void ath_slow_ant_div(struct ath_antdiv *antdiv,
|
|||||||
if (curcfg == antdiv->antdiv_num_antcfg)
|
if (curcfg == antdiv->antdiv_num_antcfg)
|
||||||
curcfg = 0;
|
curcfg = 0;
|
||||||
|
|
||||||
if (HAL_OK == ath9k_hw_select_antconfig(ah, curcfg)) {
|
if (!ath9k_hw_select_antconfig(ah, curcfg)) {
|
||||||
antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
|
antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
|
||||||
antdiv->antdiv_curcfg = curcfg;
|
antdiv->antdiv_curcfg = curcfg;
|
||||||
antdiv->antdiv_laststatetsf = curtsf;
|
antdiv->antdiv_laststatetsf = curtsf;
|
||||||
@ -1663,14 +1689,14 @@ void ath_slow_ant_div(struct ath_antdiv *antdiv,
|
|||||||
if (curcfg == antdiv->antdiv_bestcfg) {
|
if (curcfg == antdiv->antdiv_bestcfg) {
|
||||||
ath_find_max_val(antdiv->antdiv_lastbrssi,
|
ath_find_max_val(antdiv->antdiv_lastbrssi,
|
||||||
antdiv->antdiv_num_antcfg, &bestcfg);
|
antdiv->antdiv_num_antcfg, &bestcfg);
|
||||||
if (HAL_OK == ath9k_hw_select_antconfig(ah, bestcfg)) {
|
if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
|
||||||
antdiv->antdiv_bestcfg = bestcfg;
|
antdiv->antdiv_bestcfg = bestcfg;
|
||||||
antdiv->antdiv_curcfg = bestcfg;
|
antdiv->antdiv_curcfg = bestcfg;
|
||||||
antdiv->antdiv_laststatetsf = curtsf;
|
antdiv->antdiv_laststatetsf = curtsf;
|
||||||
antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
|
antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
if (HAL_OK == ath9k_hw_select_antconfig(ah, curcfg)) {
|
if (!ath9k_hw_select_antconfig(ah, curcfg)) {
|
||||||
antdiv->antdiv_curcfg = curcfg;
|
antdiv->antdiv_curcfg = curcfg;
|
||||||
antdiv->antdiv_laststatetsf = curtsf;
|
antdiv->antdiv_laststatetsf = curtsf;
|
||||||
antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
|
antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
|
||||||
@ -1730,9 +1756,9 @@ int ath_descdma_setup(struct ath_softc *sc,
|
|||||||
* one skipped descriptor per 4K page.
|
* one skipped descriptor per 4K page.
|
||||||
*/
|
*/
|
||||||
if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
|
if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) {
|
||||||
u_int32_t ndesc_skipped =
|
u32 ndesc_skipped =
|
||||||
ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
|
ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
|
||||||
u_int32_t dma_len;
|
u32 dma_len;
|
||||||
|
|
||||||
while (ndesc_skipped) {
|
while (ndesc_skipped) {
|
||||||
dma_len = ndesc_skipped * sizeof(struct ath_desc);
|
dma_len = ndesc_skipped * sizeof(struct ath_desc);
|
||||||
@ -1752,8 +1778,8 @@ int ath_descdma_setup(struct ath_softc *sc,
|
|||||||
}
|
}
|
||||||
ds = dd->dd_desc;
|
ds = dd->dd_desc;
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
|
DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
|
||||||
__func__, dd->dd_name, ds, (u_int32_t) dd->dd_desc_len,
|
__func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
|
||||||
ito64(dd->dd_desc_paddr), /*XXX*/(u_int32_t) dd->dd_desc_len);
|
ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
|
||||||
|
|
||||||
/* allocate buffers */
|
/* allocate buffers */
|
||||||
bsize = sizeof(struct ath_buf) * nbuf;
|
bsize = sizeof(struct ath_buf) * nbuf;
|
||||||
@ -1838,40 +1864,40 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
|
|||||||
|
|
||||||
switch (queue) {
|
switch (queue) {
|
||||||
case 0:
|
case 0:
|
||||||
qnum = sc->sc_haltype2q[HAL_WME_AC_VO];
|
qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
qnum = sc->sc_haltype2q[HAL_WME_AC_VI];
|
qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
qnum = sc->sc_haltype2q[HAL_WME_AC_BE];
|
qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
qnum = sc->sc_haltype2q[HAL_WME_AC_BK];
|
qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
qnum = sc->sc_haltype2q[HAL_WME_AC_BE];
|
qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
return qnum;
|
return qnum;
|
||||||
}
|
}
|
||||||
|
|
||||||
int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc)
|
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
int qnum;
|
int qnum;
|
||||||
|
|
||||||
switch (queue) {
|
switch (queue) {
|
||||||
case HAL_WME_AC_VO:
|
case ATH9K_WME_AC_VO:
|
||||||
qnum = 0;
|
qnum = 0;
|
||||||
break;
|
break;
|
||||||
case HAL_WME_AC_VI:
|
case ATH9K_WME_AC_VI:
|
||||||
qnum = 1;
|
qnum = 1;
|
||||||
break;
|
break;
|
||||||
case HAL_WME_AC_BE:
|
case ATH9K_WME_AC_BE:
|
||||||
qnum = 2;
|
qnum = 2;
|
||||||
break;
|
break;
|
||||||
case HAL_WME_AC_BK:
|
case ATH9K_WME_AC_BK:
|
||||||
qnum = 3;
|
qnum = 3;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
@ -1890,9 +1916,9 @@ int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc)
|
|||||||
* a full 64-bit TSF using the current h/w TSF.
|
* a full 64-bit TSF using the current h/w TSF.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp)
|
u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
|
||||||
{
|
{
|
||||||
u_int64_t tsf;
|
u64 tsf;
|
||||||
|
|
||||||
tsf = ath9k_hw_gettsf64(sc->sc_ah);
|
tsf = ath9k_hw_gettsf64(sc->sc_ah);
|
||||||
if ((tsf & 0x7fff) < rstamp)
|
if ((tsf & 0x7fff) < rstamp)
|
||||||
@ -1907,7 +1933,7 @@ u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp)
|
|||||||
* MIMO technology.
|
* MIMO technology.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
void ath_setdefantenna(void *context, u_int antenna)
|
void ath_setdefantenna(void *context, u32 antenna)
|
||||||
{
|
{
|
||||||
struct ath_softc *sc = (struct ath_softc *)context;
|
struct ath_softc *sc = (struct ath_softc *)context;
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
|
@ -213,11 +213,11 @@ enum ATH_DEBUG {
|
|||||||
/* Per-instance load-time (note: NOT run-time) configurations
|
/* Per-instance load-time (note: NOT run-time) configurations
|
||||||
* for Atheros Device */
|
* for Atheros Device */
|
||||||
struct ath_config {
|
struct ath_config {
|
||||||
u_int32_t ath_aggr_prot;
|
u32 ath_aggr_prot;
|
||||||
u_int16_t txpowlimit;
|
u16 txpowlimit;
|
||||||
u_int16_t txpowlimit_override;
|
u16 txpowlimit_override;
|
||||||
u_int8_t cabqReadytime; /* Cabq Readytime % */
|
u8 cabqReadytime; /* Cabq Readytime % */
|
||||||
u_int8_t swBeaconProcess; /* Process received beacons
|
u8 swBeaconProcess; /* Process received beacons
|
||||||
in SW (vs HW) */
|
in SW (vs HW) */
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -269,8 +269,8 @@ chains is due to FF aggregation in the driver. */
|
|||||||
|
|
||||||
struct ath_buf_state {
|
struct ath_buf_state {
|
||||||
int bfs_nframes; /* # frames in aggregate */
|
int bfs_nframes; /* # frames in aggregate */
|
||||||
u_int16_t bfs_al; /* length of aggregate */
|
u16 bfs_al; /* length of aggregate */
|
||||||
u_int16_t bfs_frmlen; /* length of frame */
|
u16 bfs_frmlen; /* length of frame */
|
||||||
int bfs_seqno; /* sequence number */
|
int bfs_seqno; /* sequence number */
|
||||||
int bfs_tidno; /* tid of this frame */
|
int bfs_tidno; /* tid of this frame */
|
||||||
int bfs_retries; /* current retries */
|
int bfs_retries; /* current retries */
|
||||||
@ -289,7 +289,8 @@ struct ath_buf_state {
|
|||||||
when set for tx frame */
|
when set for tx frame */
|
||||||
int bfs_rifsburst_elem; /* RIFS burst/bar */
|
int bfs_rifsburst_elem; /* RIFS burst/bar */
|
||||||
int bfs_nrifsubframes; /* # of elements in burst */
|
int bfs_nrifsubframes; /* # of elements in burst */
|
||||||
enum hal_key_type bfs_keytype; /* key type use to encrypt this frame */
|
/* key type use to encrypt this frame */
|
||||||
|
enum ath9k_key_type bfs_keytype;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define bf_nframes bf_state.bfs_nframes
|
#define bf_nframes bf_state.bfs_nframes
|
||||||
@ -332,8 +333,8 @@ struct ath_buf {
|
|||||||
struct ath_desc *bf_desc; /* virtual addr of desc */
|
struct ath_desc *bf_desc; /* virtual addr of desc */
|
||||||
dma_addr_t bf_daddr; /* physical addr of desc */
|
dma_addr_t bf_daddr; /* physical addr of desc */
|
||||||
dma_addr_t bf_buf_addr; /* physical addr of data buffer */
|
dma_addr_t bf_buf_addr; /* physical addr of data buffer */
|
||||||
u_int32_t bf_status;
|
u32 bf_status;
|
||||||
u_int16_t bf_flags; /* tx descriptor flags */
|
u16 bf_flags; /* tx descriptor flags */
|
||||||
struct ath_buf_state bf_state; /* buffer state */
|
struct ath_buf_state bf_state; /* buffer state */
|
||||||
dma_addr_t bf_dmacontext;
|
dma_addr_t bf_dmacontext;
|
||||||
};
|
};
|
||||||
@ -360,7 +361,7 @@ struct ath_descdma {
|
|||||||
const char *dd_name;
|
const char *dd_name;
|
||||||
struct ath_desc *dd_desc; /* descriptors */
|
struct ath_desc *dd_desc; /* descriptors */
|
||||||
dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
|
dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
|
||||||
u_int32_t dd_desc_len; /* size of dd_desc */
|
u32 dd_desc_len; /* size of dd_desc */
|
||||||
struct ath_buf *dd_bufptr; /* associated buffers */
|
struct ath_buf *dd_bufptr; /* associated buffers */
|
||||||
dma_addr_t dd_dmacontext;
|
dma_addr_t dd_dmacontext;
|
||||||
};
|
};
|
||||||
@ -402,13 +403,13 @@ enum ATH_RX_TYPE {
|
|||||||
|
|
||||||
/* per frame rx status block */
|
/* per frame rx status block */
|
||||||
struct ath_recv_status {
|
struct ath_recv_status {
|
||||||
u_int64_t tsf; /* mac tsf */
|
u64 tsf; /* mac tsf */
|
||||||
int8_t rssi; /* RSSI (noise floor ajusted) */
|
int8_t rssi; /* RSSI (noise floor ajusted) */
|
||||||
int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
|
int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
|
||||||
int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
|
int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
|
||||||
int8_t abs_rssi; /* absolute RSSI */
|
int8_t abs_rssi; /* absolute RSSI */
|
||||||
u_int8_t rateieee; /* data rate received (IEEE rate code) */
|
u8 rateieee; /* data rate received (IEEE rate code) */
|
||||||
u_int8_t ratecode; /* phy rate code */
|
u8 ratecode; /* phy rate code */
|
||||||
int rateKbps; /* data rate received (Kbps) */
|
int rateKbps; /* data rate received (Kbps) */
|
||||||
int antenna; /* rx antenna */
|
int antenna; /* rx antenna */
|
||||||
int flags; /* status of associated skb */
|
int flags; /* status of associated skb */
|
||||||
@ -442,8 +443,8 @@ struct ath_arx_tid {
|
|||||||
int baw_tail; /* tail of block-ack window */
|
int baw_tail; /* tail of block-ack window */
|
||||||
int seq_reset; /* need to reset start sequence */
|
int seq_reset; /* need to reset start sequence */
|
||||||
int addba_exchangecomplete;
|
int addba_exchangecomplete;
|
||||||
u_int16_t seq_next; /* next expected sequence */
|
u16 seq_next; /* next expected sequence */
|
||||||
u_int16_t baw_size; /* block-ack window size */
|
u16 baw_size; /* block-ack window size */
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Per-node receiver aggregate state */
|
/* Per-node receiver aggregate state */
|
||||||
@ -454,7 +455,7 @@ struct ath_arx {
|
|||||||
int ath_startrecv(struct ath_softc *sc);
|
int ath_startrecv(struct ath_softc *sc);
|
||||||
bool ath_stoprecv(struct ath_softc *sc);
|
bool ath_stoprecv(struct ath_softc *sc);
|
||||||
void ath_flushrecv(struct ath_softc *sc);
|
void ath_flushrecv(struct ath_softc *sc);
|
||||||
u_int32_t ath_calcrxfilter(struct ath_softc *sc);
|
u32 ath_calcrxfilter(struct ath_softc *sc);
|
||||||
void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
|
void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
|
||||||
void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
|
void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
|
||||||
void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
|
void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
|
||||||
@ -471,7 +472,7 @@ int ath_rx_input(struct ath_softc *sc,
|
|||||||
int ath__rx_indicate(struct ath_softc *sc,
|
int ath__rx_indicate(struct ath_softc *sc,
|
||||||
struct sk_buff *skb,
|
struct sk_buff *skb,
|
||||||
struct ath_recv_status *status,
|
struct ath_recv_status *status,
|
||||||
u_int16_t keyix);
|
u16 keyix);
|
||||||
int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
|
int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
|
||||||
struct ath_recv_status *status);
|
struct ath_recv_status *status);
|
||||||
|
|
||||||
@ -520,15 +521,15 @@ enum ATH_SM_PWRSAV{
|
|||||||
* hardware queue).
|
* hardware queue).
|
||||||
*/
|
*/
|
||||||
struct ath_txq {
|
struct ath_txq {
|
||||||
u_int axq_qnum; /* hardware q number */
|
u32 axq_qnum; /* hardware q number */
|
||||||
u_int32_t *axq_link; /* link ptr in last TX desc */
|
u32 *axq_link; /* link ptr in last TX desc */
|
||||||
struct list_head axq_q; /* transmit queue */
|
struct list_head axq_q; /* transmit queue */
|
||||||
spinlock_t axq_lock; /* lock on q and link */
|
spinlock_t axq_lock; /* lock on q and link */
|
||||||
unsigned long axq_lockflags; /* intr state when must cli */
|
unsigned long axq_lockflags; /* intr state when must cli */
|
||||||
u_int axq_depth; /* queue depth */
|
u32 axq_depth; /* queue depth */
|
||||||
u_int8_t axq_aggr_depth; /* aggregates queued */
|
u8 axq_aggr_depth; /* aggregates queued */
|
||||||
u_int32_t axq_totalqueued;/* total ever queued */
|
u32 axq_totalqueued;/* total ever queued */
|
||||||
u_int axq_intrcnt; /* count to determine
|
u32 axq_intrcnt; /* count to determine
|
||||||
if descriptor should generate
|
if descriptor should generate
|
||||||
int on this txq. */
|
int on this txq. */
|
||||||
bool stopped; /* Is mac80211 queue
|
bool stopped; /* Is mac80211 queue
|
||||||
@ -550,9 +551,9 @@ struct ath_atx_tid {
|
|||||||
struct ath_node *an; /* parent node structure */
|
struct ath_node *an; /* parent node structure */
|
||||||
struct ath_atx_ac *ac; /* parent access category */
|
struct ath_atx_ac *ac; /* parent access category */
|
||||||
struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */
|
struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */
|
||||||
u_int16_t seq_start; /* starting seq of BA window */
|
u16 seq_start; /* starting seq of BA window */
|
||||||
u_int16_t seq_next; /* next seq to be used */
|
u16 seq_next; /* next seq to be used */
|
||||||
u_int16_t baw_size; /* BA window size */
|
u16 baw_size; /* BA window size */
|
||||||
int tidno; /* TID number */
|
int tidno; /* TID number */
|
||||||
int baw_head; /* first un-acked tx buffer */
|
int baw_head; /* first un-acked tx buffer */
|
||||||
int baw_tail; /* next unused tx buffer slot */
|
int baw_tail; /* next unused tx buffer slot */
|
||||||
@ -560,7 +561,7 @@ struct ath_atx_tid {
|
|||||||
int paused; /* TID is paused */
|
int paused; /* TID is paused */
|
||||||
int cleanup_inprogress; /* aggr of this TID is
|
int cleanup_inprogress; /* aggr of this TID is
|
||||||
being teared down */
|
being teared down */
|
||||||
u_int32_t addba_exchangecomplete:1; /* ADDBA state */
|
u32 addba_exchangecomplete:1; /* ADDBA state */
|
||||||
int32_t addba_exchangeinprogress;
|
int32_t addba_exchangeinprogress;
|
||||||
int addba_exchangeattempts;
|
int addba_exchangeattempts;
|
||||||
};
|
};
|
||||||
@ -585,21 +586,21 @@ struct ath_tx_control {
|
|||||||
struct ath_node *an; /* destination to sent to */
|
struct ath_node *an; /* destination to sent to */
|
||||||
int if_id; /* only valid for cab traffic */
|
int if_id; /* only valid for cab traffic */
|
||||||
int qnum; /* h/w queue number */
|
int qnum; /* h/w queue number */
|
||||||
u_int ht:1; /* if it can be transmitted using HT */
|
u32 ht:1; /* if it can be transmitted using HT */
|
||||||
u_int ps:1; /* if one or more stations are in PS mode */
|
u32 ps:1; /* if one or more stations are in PS mode */
|
||||||
u_int use_minrate:1; /* if this frame should transmitted using
|
u32 use_minrate:1; /* if this frame should transmitted using
|
||||||
minimum rate */
|
minimum rate */
|
||||||
enum hal_pkt_type atype; /* Atheros packet type */
|
enum ath9k_pkt_type atype; /* Atheros packet type */
|
||||||
enum hal_key_type keytype; /* key type */
|
enum ath9k_key_type keytype; /* key type */
|
||||||
u_int flags; /* HAL flags */
|
u32 flags; /* HAL flags */
|
||||||
u_int16_t seqno; /* sequence number */
|
u16 seqno; /* sequence number */
|
||||||
u_int16_t tidno; /* tid number */
|
u16 tidno; /* tid number */
|
||||||
u_int16_t txpower; /* transmit power */
|
u16 txpower; /* transmit power */
|
||||||
u_int16_t frmlen; /* frame length */
|
u16 frmlen; /* frame length */
|
||||||
u_int32_t keyix; /* key index */
|
u32 keyix; /* key index */
|
||||||
int min_rate; /* minimum rate */
|
int min_rate; /* minimum rate */
|
||||||
int mcast_rate; /* multicast rate */
|
int mcast_rate; /* multicast rate */
|
||||||
u_int16_t nextfraglen; /* next fragment length */
|
u16 nextfraglen; /* next fragment length */
|
||||||
/* below is set only by ath_dev */
|
/* below is set only by ath_dev */
|
||||||
struct ath_softc *dev; /* device handle */
|
struct ath_softc *dev; /* device handle */
|
||||||
dma_addr_t dmacontext;
|
dma_addr_t dmacontext;
|
||||||
@ -627,7 +628,7 @@ struct ath_tx_stat {
|
|||||||
#define ATH_TX_CHAIN_RSSI_VALID 0x01
|
#define ATH_TX_CHAIN_RSSI_VALID 0x01
|
||||||
/* if extn chain rssis are valid */
|
/* if extn chain rssis are valid */
|
||||||
#define ATH_TX_RSSI_EXTN_VALID 0x02
|
#define ATH_TX_RSSI_EXTN_VALID 0x02
|
||||||
u_int32_t airtime; /* time on air per final tx rate */
|
u32 airtime; /* time on air per final tx rate */
|
||||||
};
|
};
|
||||||
|
|
||||||
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
|
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
|
||||||
@ -644,12 +645,12 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
|
|||||||
int ath_tx_init(struct ath_softc *sc, int nbufs);
|
int ath_tx_init(struct ath_softc *sc, int nbufs);
|
||||||
int ath_tx_cleanup(struct ath_softc *sc);
|
int ath_tx_cleanup(struct ath_softc *sc);
|
||||||
int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
|
int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
|
||||||
int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *q);
|
int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_txq_info *q);
|
||||||
int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
|
int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
|
||||||
void ath_tx_tasklet(struct ath_softc *sc);
|
void ath_tx_tasklet(struct ath_softc *sc);
|
||||||
u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum);
|
u32 ath_txq_depth(struct ath_softc *sc, int qnum);
|
||||||
u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
|
u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
|
||||||
void ath_notify_txq_status(struct ath_softc *sc, u_int16_t queue_depth);
|
void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
|
||||||
void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
|
void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
|
||||||
struct ath_xmit_status *tx_status, struct ath_node *an);
|
struct ath_xmit_status *tx_status, struct ath_node *an);
|
||||||
|
|
||||||
@ -733,8 +734,8 @@ struct ath_node {
|
|||||||
atomic_t an_refcnt;
|
atomic_t an_refcnt;
|
||||||
struct ath_chainmask_sel an_chainmask_sel;
|
struct ath_chainmask_sel an_chainmask_sel;
|
||||||
struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */
|
struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */
|
||||||
u_int8_t an_smmode; /* SM Power save mode */
|
u8 an_smmode; /* SM Power save mode */
|
||||||
u_int8_t an_flags;
|
u8 an_flags;
|
||||||
u8 an_addr[ETH_ALEN];
|
u8 an_addr[ETH_ALEN];
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -743,9 +744,9 @@ void ath_tx_resume_tid(struct ath_softc *sc,
|
|||||||
enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
|
enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
|
||||||
struct ath_node *an, u8 tidno);
|
struct ath_node *an, u8 tidno);
|
||||||
void ath_tx_aggr_teardown(struct ath_softc *sc,
|
void ath_tx_aggr_teardown(struct ath_softc *sc,
|
||||||
struct ath_node *an, u_int8_t tidno);
|
struct ath_node *an, u8 tidno);
|
||||||
void ath_rx_aggr_teardown(struct ath_softc *sc,
|
void ath_rx_aggr_teardown(struct ath_softc *sc,
|
||||||
struct ath_node *an, u_int8_t tidno);
|
struct ath_node *an, u8 tidno);
|
||||||
int ath_rx_aggr_start(struct ath_softc *sc,
|
int ath_rx_aggr_start(struct ath_softc *sc,
|
||||||
const u8 *addr,
|
const u8 *addr,
|
||||||
u16 tid,
|
u16 tid,
|
||||||
@ -763,11 +764,11 @@ int ath_tx_aggr_stop(struct ath_softc *sc,
|
|||||||
void ath_newassoc(struct ath_softc *sc,
|
void ath_newassoc(struct ath_softc *sc,
|
||||||
struct ath_node *node, int isnew, int isuapsd);
|
struct ath_node *node, int isnew, int isuapsd);
|
||||||
struct ath_node *ath_node_attach(struct ath_softc *sc,
|
struct ath_node *ath_node_attach(struct ath_softc *sc,
|
||||||
u_int8_t addr[ETH_ALEN], int if_id);
|
u8 addr[ETH_ALEN], int if_id);
|
||||||
void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
|
void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
|
||||||
struct ath_node *ath_node_get(struct ath_softc *sc, u_int8_t addr[ETH_ALEN]);
|
struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
|
||||||
void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
|
void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
|
||||||
struct ath_node *ath_node_find(struct ath_softc *sc, u_int8_t *addr);
|
struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
|
||||||
|
|
||||||
/*******************/
|
/*******************/
|
||||||
/* Beacon Handling */
|
/* Beacon Handling */
|
||||||
@ -789,22 +790,22 @@ struct ath_node *ath_node_find(struct ath_softc *sc, u_int8_t *addr);
|
|||||||
|
|
||||||
/* beacon configuration */
|
/* beacon configuration */
|
||||||
struct ath_beacon_config {
|
struct ath_beacon_config {
|
||||||
u_int16_t beacon_interval;
|
u16 beacon_interval;
|
||||||
u_int16_t listen_interval;
|
u16 listen_interval;
|
||||||
u_int16_t dtim_period;
|
u16 dtim_period;
|
||||||
u_int16_t bmiss_timeout;
|
u16 bmiss_timeout;
|
||||||
u_int8_t dtim_count;
|
u8 dtim_count;
|
||||||
u_int8_t tim_offset;
|
u8 tim_offset;
|
||||||
union {
|
union {
|
||||||
u_int64_t last_tsf;
|
u64 last_tsf;
|
||||||
u_int8_t last_tstamp[8];
|
u8 last_tstamp[8];
|
||||||
} u; /* last received beacon/probe response timestamp of this BSS. */
|
} u; /* last received beacon/probe response timestamp of this BSS. */
|
||||||
};
|
};
|
||||||
|
|
||||||
/* offsets in a beacon frame for
|
/* offsets in a beacon frame for
|
||||||
* quick acess of beacon content by low-level driver */
|
* quick acess of beacon content by low-level driver */
|
||||||
struct ath_beacon_offset {
|
struct ath_beacon_offset {
|
||||||
u_int8_t *bo_tim; /* start of atim/dtim */
|
u8 *bo_tim; /* start of atim/dtim */
|
||||||
};
|
};
|
||||||
|
|
||||||
void ath9k_beacon_tasklet(unsigned long data);
|
void ath9k_beacon_tasklet(unsigned long data);
|
||||||
@ -851,15 +852,15 @@ int ath_update_beacon(struct ath_softc *sc,
|
|||||||
|
|
||||||
/* VAP configuration (from protocol layer) */
|
/* VAP configuration (from protocol layer) */
|
||||||
struct ath_vap_config {
|
struct ath_vap_config {
|
||||||
u_int32_t av_fixed_rateset;
|
u32 av_fixed_rateset;
|
||||||
u_int32_t av_fixed_retryset;
|
u32 av_fixed_retryset;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* driver-specific vap state */
|
/* driver-specific vap state */
|
||||||
struct ath_vap {
|
struct ath_vap {
|
||||||
struct ieee80211_vif *av_if_data; /* interface(vap)
|
struct ieee80211_vif *av_if_data; /* interface(vap)
|
||||||
instance from 802.11 protocal layer */
|
instance from 802.11 protocal layer */
|
||||||
enum hal_opmode av_opmode; /* VAP operational mode */
|
enum ath9k_opmode av_opmode; /* VAP operational mode */
|
||||||
struct ath_buf *av_bcbuf; /* beacon buffer */
|
struct ath_buf *av_bcbuf; /* beacon buffer */
|
||||||
struct ath_beacon_offset av_boff; /* dynamic update state */
|
struct ath_beacon_offset av_boff; /* dynamic update state */
|
||||||
struct ath_tx_control av_btxctl; /* tx control information
|
struct ath_tx_control av_btxctl; /* tx control information
|
||||||
@ -869,12 +870,13 @@ struct ath_vap {
|
|||||||
transmit queue */
|
transmit queue */
|
||||||
struct ath_vap_config av_config; /* vap configuration
|
struct ath_vap_config av_config; /* vap configuration
|
||||||
parameters from 802.11 protocol layer*/
|
parameters from 802.11 protocol layer*/
|
||||||
|
struct ath_rate_node *rc_node;
|
||||||
};
|
};
|
||||||
|
|
||||||
int ath_vap_attach(struct ath_softc *sc,
|
int ath_vap_attach(struct ath_softc *sc,
|
||||||
int if_id,
|
int if_id,
|
||||||
struct ieee80211_vif *if_data,
|
struct ieee80211_vif *if_data,
|
||||||
enum hal_opmode opmode);
|
enum ath9k_opmode opmode);
|
||||||
int ath_vap_detach(struct ath_softc *sc, int if_id);
|
int ath_vap_detach(struct ath_softc *sc, int if_id);
|
||||||
int ath_vap_config(struct ath_softc *sc,
|
int ath_vap_config(struct ath_softc *sc,
|
||||||
int if_id, struct ath_vap_config *if_config);
|
int if_id, struct ath_vap_config *if_config);
|
||||||
@ -895,28 +897,28 @@ enum ATH_ANT_DIV_STATE{
|
|||||||
|
|
||||||
struct ath_antdiv {
|
struct ath_antdiv {
|
||||||
struct ath_softc *antdiv_sc;
|
struct ath_softc *antdiv_sc;
|
||||||
u_int8_t antdiv_start;
|
u8 antdiv_start;
|
||||||
enum ATH_ANT_DIV_STATE antdiv_state;
|
enum ATH_ANT_DIV_STATE antdiv_state;
|
||||||
u_int8_t antdiv_num_antcfg;
|
u8 antdiv_num_antcfg;
|
||||||
u_int8_t antdiv_curcfg;
|
u8 antdiv_curcfg;
|
||||||
u_int8_t antdiv_bestcfg;
|
u8 antdiv_bestcfg;
|
||||||
int32_t antdivf_rssitrig;
|
int32_t antdivf_rssitrig;
|
||||||
int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
|
int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
|
||||||
u_int64_t antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
|
u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
|
||||||
u_int64_t antdiv_laststatetsf;
|
u64 antdiv_laststatetsf;
|
||||||
u_int8_t antdiv_bssid[ETH_ALEN];
|
u8 antdiv_bssid[ETH_ALEN];
|
||||||
};
|
};
|
||||||
|
|
||||||
void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
|
void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
|
||||||
struct ath_softc *sc, int32_t rssitrig);
|
struct ath_softc *sc, int32_t rssitrig);
|
||||||
void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
|
void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
|
||||||
u_int8_t num_antcfg,
|
u8 num_antcfg,
|
||||||
const u_int8_t *bssid);
|
const u8 *bssid);
|
||||||
void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
|
void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
|
||||||
void ath_slow_ant_div(struct ath_antdiv *antdiv,
|
void ath_slow_ant_div(struct ath_antdiv *antdiv,
|
||||||
struct ieee80211_hdr *wh,
|
struct ieee80211_hdr *wh,
|
||||||
struct ath_rx_status *rx_stats);
|
struct ath_rx_status *rx_stats);
|
||||||
void ath_setdefantenna(void *sc, u_int antenna);
|
void ath_setdefantenna(void *sc, u32 antenna);
|
||||||
|
|
||||||
/********************/
|
/********************/
|
||||||
/* Main driver core */
|
/* Main driver core */
|
||||||
@ -947,7 +949,6 @@ void ath_setdefantenna(void *sc, u_int antenna);
|
|||||||
* up to ATH_KEYMAX entries (could dynamically allocate state).
|
* up to ATH_KEYMAX entries (could dynamically allocate state).
|
||||||
*/
|
*/
|
||||||
#define ATH_KEYMAX 128 /* max key cache size we handle */
|
#define ATH_KEYMAX 128 /* max key cache size we handle */
|
||||||
#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
|
|
||||||
|
|
||||||
#define RESET_RETRY_TXQ 0x00000001
|
#define RESET_RETRY_TXQ 0x00000001
|
||||||
#define ATH_IF_ID_ANY 0xff
|
#define ATH_IF_ID_ANY 0xff
|
||||||
@ -984,12 +985,6 @@ enum PROT_MODE {
|
|||||||
PROT_M_CTSONLY
|
PROT_M_CTSONLY
|
||||||
};
|
};
|
||||||
|
|
||||||
enum ieee80211_clist_cmd {
|
|
||||||
CLIST_UPDATE,
|
|
||||||
CLIST_DFS_UPDATE,
|
|
||||||
CLIST_NEW_COUNTRY
|
|
||||||
};
|
|
||||||
|
|
||||||
enum RATE_TYPE {
|
enum RATE_TYPE {
|
||||||
NORMAL_RATE = 0,
|
NORMAL_RATE = 0,
|
||||||
HALF_RATE,
|
HALF_RATE,
|
||||||
@ -997,10 +992,10 @@ enum RATE_TYPE {
|
|||||||
};
|
};
|
||||||
|
|
||||||
struct ath_ht_info {
|
struct ath_ht_info {
|
||||||
enum hal_ht_macmode tx_chan_width;
|
enum ath9k_ht_macmode tx_chan_width;
|
||||||
u_int16_t maxampdu;
|
u16 maxampdu;
|
||||||
u_int8_t mpdudensity;
|
u8 mpdudensity;
|
||||||
u_int8_t ext_chan_offset;
|
u8 ext_chan_offset;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct ath_softc {
|
struct ath_softc {
|
||||||
@ -1014,52 +1009,52 @@ struct ath_softc {
|
|||||||
int sc_debug; /* Debug masks */
|
int sc_debug; /* Debug masks */
|
||||||
struct ath_hal *sc_ah; /* HAL Instance */
|
struct ath_hal *sc_ah; /* HAL Instance */
|
||||||
struct ath_rate_softc *sc_rc; /* tx rate control support */
|
struct ath_rate_softc *sc_rc; /* tx rate control support */
|
||||||
u_int32_t sc_intrstatus; /* HAL_STATUS */
|
u32 sc_intrstatus; /* HAL_STATUS */
|
||||||
enum hal_opmode sc_opmode; /* current operating mode */
|
enum ath9k_opmode sc_opmode; /* current operating mode */
|
||||||
|
|
||||||
/* Properties, Config */
|
/* Properties, Config */
|
||||||
u_int8_t sc_invalid; /* being detached */
|
u8 sc_invalid; /* being detached */
|
||||||
u_int8_t sc_beacons; /* beacons running */
|
u8 sc_beacons; /* beacons running */
|
||||||
u_int8_t sc_scanning; /* scanning active */
|
u8 sc_scanning; /* scanning active */
|
||||||
u_int8_t sc_txaggr; /* enable 11n tx aggregation */
|
u8 sc_txaggr; /* enable 11n tx aggregation */
|
||||||
u_int8_t sc_rxaggr; /* enable 11n rx aggregation */
|
u8 sc_rxaggr; /* enable 11n rx aggregation */
|
||||||
u_int8_t sc_update_chainmask; /* change chain mask */
|
u8 sc_update_chainmask; /* change chain mask */
|
||||||
u_int8_t sc_full_reset; /* force full reset */
|
u8 sc_full_reset; /* force full reset */
|
||||||
enum wireless_mode sc_curmode; /* current phy mode */
|
enum wireless_mode sc_curmode; /* current phy mode */
|
||||||
u_int16_t sc_curtxpow; /* current tx power limit */
|
u16 sc_curtxpow; /* current tx power limit */
|
||||||
u_int16_t sc_curaid; /* current association id */
|
u16 sc_curaid; /* current association id */
|
||||||
u_int8_t sc_curbssid[ETH_ALEN];
|
u8 sc_curbssid[ETH_ALEN];
|
||||||
u_int8_t sc_myaddr[ETH_ALEN];
|
u8 sc_myaddr[ETH_ALEN];
|
||||||
enum PROT_MODE sc_protmode; /* protection mode */
|
enum PROT_MODE sc_protmode; /* protection mode */
|
||||||
u_int8_t sc_mcastantenna;/* Multicast antenna number */
|
u8 sc_mcastantenna;/* Multicast antenna number */
|
||||||
u_int8_t sc_txantenna; /* data tx antenna
|
u8 sc_txantenna; /* data tx antenna
|
||||||
(fixed or auto) */
|
(fixed or auto) */
|
||||||
u_int8_t sc_nbcnvaps; /* # of vaps sending beacons */
|
u8 sc_nbcnvaps; /* # of vaps sending beacons */
|
||||||
u_int16_t sc_nvaps; /* # of active virtual ap's */
|
u16 sc_nvaps; /* # of active virtual ap's */
|
||||||
struct ath_vap *sc_vaps[ATH_BCBUF]; /* interface id
|
struct ath_vap *sc_vaps[ATH_BCBUF]; /* interface id
|
||||||
to avp map */
|
to avp map */
|
||||||
enum hal_int sc_imask; /* interrupt mask copy */
|
enum ath9k_int sc_imask; /* interrupt mask copy */
|
||||||
u_int8_t sc_bssidmask[ETH_ALEN];
|
u8 sc_bssidmask[ETH_ALEN];
|
||||||
u_int8_t sc_defant; /* current default antenna */
|
u8 sc_defant; /* current default antenna */
|
||||||
u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
|
u8 sc_rxotherant; /* rx's on non-default antenna*/
|
||||||
u_int16_t sc_cachelsz; /* cache line size */
|
u16 sc_cachelsz; /* cache line size */
|
||||||
int sc_slotupdate; /* slot to next advance fsm */
|
int sc_slotupdate; /* slot to next advance fsm */
|
||||||
int sc_slottime; /* slot time */
|
int sc_slottime; /* slot time */
|
||||||
u_int8_t sc_noreset;
|
u8 sc_noreset;
|
||||||
int sc_bslot[ATH_BCBUF];/* beacon xmit slots */
|
int sc_bslot[ATH_BCBUF];/* beacon xmit slots */
|
||||||
struct hal_node_stats sc_halstats; /* station-mode rssi stats */
|
struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
|
||||||
struct list_head node_list;
|
struct list_head node_list;
|
||||||
struct ath_ht_info sc_ht_info;
|
struct ath_ht_info sc_ht_info;
|
||||||
int16_t sc_noise_floor; /* signal noise floor in dBm */
|
int16_t sc_noise_floor; /* signal noise floor in dBm */
|
||||||
enum hal_ht_extprotspacing sc_ht_extprotspacing;
|
enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
|
||||||
u_int8_t sc_tx_chainmask;
|
u8 sc_tx_chainmask;
|
||||||
u_int8_t sc_rx_chainmask;
|
u8 sc_rx_chainmask;
|
||||||
u_int8_t sc_rxchaindetect_ref;
|
u8 sc_rxchaindetect_ref;
|
||||||
u_int8_t sc_rxchaindetect_thresh5GHz;
|
u8 sc_rxchaindetect_thresh5GHz;
|
||||||
u_int8_t sc_rxchaindetect_thresh2GHz;
|
u8 sc_rxchaindetect_thresh2GHz;
|
||||||
u_int8_t sc_rxchaindetect_delta5GHz;
|
u8 sc_rxchaindetect_delta5GHz;
|
||||||
u_int8_t sc_rxchaindetect_delta2GHz;
|
u8 sc_rxchaindetect_delta2GHz;
|
||||||
u_int32_t sc_rtsaggrlimit; /* Chipset specific
|
u32 sc_rtsaggrlimit; /* Chipset specific
|
||||||
aggr limit */
|
aggr limit */
|
||||||
u32 sc_flags;
|
u32 sc_flags;
|
||||||
#ifdef CONFIG_SLOW_ANT_DIV
|
#ifdef CONFIG_SLOW_ANT_DIV
|
||||||
@ -1073,56 +1068,56 @@ struct ath_softc {
|
|||||||
} sc_updateslot; /* slot time update fsm */
|
} sc_updateslot; /* slot time update fsm */
|
||||||
|
|
||||||
/* Crypto */
|
/* Crypto */
|
||||||
u_int sc_keymax; /* size of key cache */
|
u32 sc_keymax; /* size of key cache */
|
||||||
DECLARE_BITMAP (sc_keymap, ATH_KEYBYTES);/* key use bit map */
|
DECLARE_BITMAP (sc_keymap, ATH_KEYMAX);/* key use bit map */
|
||||||
u_int8_t sc_splitmic; /* split TKIP MIC keys */
|
u8 sc_splitmic; /* split TKIP MIC keys */
|
||||||
int sc_keytype; /* type of the key being used */
|
int sc_keytype; /* type of the key being used */
|
||||||
|
|
||||||
/* RX */
|
/* RX */
|
||||||
struct list_head sc_rxbuf; /* receive buffer */
|
struct list_head sc_rxbuf; /* receive buffer */
|
||||||
struct ath_descdma sc_rxdma; /* RX descriptors */
|
struct ath_descdma sc_rxdma; /* RX descriptors */
|
||||||
int sc_rxbufsize; /* rx size based on mtu */
|
int sc_rxbufsize; /* rx size based on mtu */
|
||||||
u_int32_t *sc_rxlink; /* link ptr in last RX desc */
|
u32 *sc_rxlink; /* link ptr in last RX desc */
|
||||||
u_int32_t sc_rxflush; /* rx flush in progress */
|
u32 sc_rxflush; /* rx flush in progress */
|
||||||
u_int64_t sc_lastrx; /* tsf of last rx'd frame */
|
u64 sc_lastrx; /* tsf of last rx'd frame */
|
||||||
|
|
||||||
/* TX */
|
/* TX */
|
||||||
struct list_head sc_txbuf; /* transmit buffer */
|
struct list_head sc_txbuf; /* transmit buffer */
|
||||||
struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
|
struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
|
||||||
struct ath_descdma sc_txdma; /* TX descriptors */
|
struct ath_descdma sc_txdma; /* TX descriptors */
|
||||||
u_int sc_txqsetup; /* h/w queues setup */
|
u32 sc_txqsetup; /* h/w queues setup */
|
||||||
u_int sc_txintrperiod;/* tx interrupt batching */
|
u32 sc_txintrperiod;/* tx interrupt batching */
|
||||||
int sc_haltype2q[HAL_WME_AC_VO+1]; /* HAL WME
|
int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME
|
||||||
AC -> h/w qnum */
|
AC -> h/w qnum */
|
||||||
u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
|
u32 sc_ant_tx[8]; /* recent tx frames/antenna */
|
||||||
|
|
||||||
/* Beacon */
|
/* Beacon */
|
||||||
struct hal_txq_info sc_beacon_qi; /* adhoc only: beacon
|
struct ath9k_txq_info sc_beacon_qi; /* adhoc only: beacon
|
||||||
queue parameters */
|
queue parameters */
|
||||||
struct ath_descdma sc_bdma; /* beacon descriptors */
|
struct ath_descdma sc_bdma; /* beacon descriptors */
|
||||||
struct ath_txq *sc_cabq; /* tx q for cab frames */
|
struct ath_txq *sc_cabq; /* tx q for cab frames */
|
||||||
struct list_head sc_bbuf; /* beacon buffers */
|
struct list_head sc_bbuf; /* beacon buffers */
|
||||||
u_int sc_bhalq; /* HAL q for outgoing beacons */
|
u32 sc_bhalq; /* HAL q for outgoing beacons */
|
||||||
u_int sc_bmisscount; /* missed beacon transmits */
|
u32 sc_bmisscount; /* missed beacon transmits */
|
||||||
u_int32_t ast_be_xmit; /* beacons transmitted */
|
u32 ast_be_xmit; /* beacons transmitted */
|
||||||
|
|
||||||
/* Rate */
|
/* Rate */
|
||||||
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
|
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
|
||||||
const struct hal_rate_table *sc_rates[WIRELESS_MODE_MAX];
|
const struct ath9k_rate_table *sc_rates[WIRELESS_MODE_MAX];
|
||||||
const struct hal_rate_table *sc_currates; /* current rate table */
|
const struct ath9k_rate_table *sc_currates; /* current rate table */
|
||||||
u_int8_t sc_rixmap[256]; /* IEEE to h/w
|
u8 sc_rixmap[256]; /* IEEE to h/w
|
||||||
rate table ix */
|
rate table ix */
|
||||||
u_int8_t sc_minrateix; /* min h/w rate index */
|
u8 sc_minrateix; /* min h/w rate index */
|
||||||
u_int8_t sc_protrix; /* protection rate index */
|
u8 sc_protrix; /* protection rate index */
|
||||||
struct {
|
struct {
|
||||||
u_int32_t rateKbps; /* transfer rate in kbs */
|
u32 rateKbps; /* transfer rate in kbs */
|
||||||
u_int8_t ieeerate; /* IEEE rate */
|
u8 ieeerate; /* IEEE rate */
|
||||||
} sc_hwmap[256]; /* h/w rate ix mappings */
|
} sc_hwmap[256]; /* h/w rate ix mappings */
|
||||||
|
|
||||||
/* Channel, Band */
|
/* Channel, Band */
|
||||||
struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
|
struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
|
||||||
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
||||||
struct hal_channel sc_curchan; /* current h/w channel */
|
struct ath9k_channel sc_curchan; /* current h/w channel */
|
||||||
|
|
||||||
/* Locks */
|
/* Locks */
|
||||||
spinlock_t sc_rxflushlock; /* lock of RX flush */
|
spinlock_t sc_rxflushlock; /* lock of RX flush */
|
||||||
@ -1132,46 +1127,39 @@ struct ath_softc {
|
|||||||
spinlock_t node_lock;
|
spinlock_t node_lock;
|
||||||
};
|
};
|
||||||
|
|
||||||
int ath_init(u_int16_t devid, struct ath_softc *sc);
|
int ath_init(u16 devid, struct ath_softc *sc);
|
||||||
void ath_deinit(struct ath_softc *sc);
|
void ath_deinit(struct ath_softc *sc);
|
||||||
int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
|
int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
|
||||||
int ath_suspend(struct ath_softc *sc);
|
int ath_suspend(struct ath_softc *sc);
|
||||||
irqreturn_t ath_isr(int irq, void *dev);
|
irqreturn_t ath_isr(int irq, void *dev);
|
||||||
int ath_reset(struct ath_softc *sc);
|
int ath_reset(struct ath_softc *sc);
|
||||||
void ath_scan_start(struct ath_softc *sc);
|
void ath_scan_start(struct ath_softc *sc);
|
||||||
void ath_scan_end(struct ath_softc *sc);
|
void ath_scan_end(struct ath_softc *sc);
|
||||||
int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan);
|
int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
|
||||||
void ath_setup_channel_list(struct ath_softc *sc,
|
|
||||||
enum ieee80211_clist_cmd cmd,
|
|
||||||
const struct hal_channel *chans,
|
|
||||||
int nchan,
|
|
||||||
const u_int8_t *regclassids,
|
|
||||||
u_int nregclass,
|
|
||||||
int countrycode);
|
|
||||||
void ath_setup_rate(struct ath_softc *sc,
|
void ath_setup_rate(struct ath_softc *sc,
|
||||||
enum wireless_mode wMode,
|
enum wireless_mode wMode,
|
||||||
enum RATE_TYPE type,
|
enum RATE_TYPE type,
|
||||||
const struct hal_rate_table *rt);
|
const struct ath9k_rate_table *rt);
|
||||||
|
|
||||||
/*********************/
|
/*********************/
|
||||||
/* Utility Functions */
|
/* Utility Functions */
|
||||||
/*********************/
|
/*********************/
|
||||||
|
|
||||||
void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
|
void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
|
||||||
int ath_keyset(struct ath_softc *sc,
|
int ath_keyset(struct ath_softc *sc,
|
||||||
u_int16_t keyix,
|
u16 keyix,
|
||||||
struct hal_keyval *hk,
|
struct ath9k_keyval *hk,
|
||||||
const u_int8_t mac[ETH_ALEN]);
|
const u8 mac[ETH_ALEN]);
|
||||||
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
|
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
|
||||||
int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc);
|
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
|
||||||
void ath_setslottime(struct ath_softc *sc);
|
void ath_setslottime(struct ath_softc *sc);
|
||||||
void ath_update_txpow(struct ath_softc *sc);
|
void ath_update_txpow(struct ath_softc *sc);
|
||||||
int ath_cabq_update(struct ath_softc *);
|
int ath_cabq_update(struct ath_softc *);
|
||||||
void ath_get_currentCountry(struct ath_softc *sc,
|
void ath_get_currentCountry(struct ath_softc *sc,
|
||||||
struct hal_country_entry *ctry);
|
struct ath9k_country_entry *ctry);
|
||||||
u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp);
|
u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
|
||||||
void ath_internal_reset(struct ath_softc *sc);
|
void ath_internal_reset(struct ath_softc *sc);
|
||||||
u_int32_t ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
|
u32 ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
|
||||||
dma_addr_t ath_skb_map_single(struct ath_softc *sc,
|
dma_addr_t ath_skb_map_single(struct ath_softc *sc,
|
||||||
struct sk_buff *skb,
|
struct sk_buff *skb,
|
||||||
int direction,
|
int direction,
|
||||||
@ -1180,7 +1168,7 @@ void ath_skb_unmap_single(struct ath_softc *sc,
|
|||||||
struct sk_buff *skb,
|
struct sk_buff *skb,
|
||||||
int direction,
|
int direction,
|
||||||
dma_addr_t *pa);
|
dma_addr_t *pa);
|
||||||
void ath_mcast_merge(struct ath_softc *sc, u_int32_t mfilt[2]);
|
void ath_mcast_merge(struct ath_softc *sc, u32 mfilt[2]);
|
||||||
enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
|
enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
|
||||||
|
|
||||||
#endif /* CORE_H */
|
#endif /* CORE_H */
|
||||||
|
File diff suppressed because it is too large
Load Diff
@ -21,43 +21,43 @@
|
|||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
|
|
||||||
struct ar5416_desc {
|
struct ar5416_desc {
|
||||||
u_int32_t ds_link;
|
u32 ds_link;
|
||||||
u_int32_t ds_data;
|
u32 ds_data;
|
||||||
u_int32_t ds_ctl0;
|
u32 ds_ctl0;
|
||||||
u_int32_t ds_ctl1;
|
u32 ds_ctl1;
|
||||||
union {
|
union {
|
||||||
struct {
|
struct {
|
||||||
u_int32_t ctl2;
|
u32 ctl2;
|
||||||
u_int32_t ctl3;
|
u32 ctl3;
|
||||||
u_int32_t ctl4;
|
u32 ctl4;
|
||||||
u_int32_t ctl5;
|
u32 ctl5;
|
||||||
u_int32_t ctl6;
|
u32 ctl6;
|
||||||
u_int32_t ctl7;
|
u32 ctl7;
|
||||||
u_int32_t ctl8;
|
u32 ctl8;
|
||||||
u_int32_t ctl9;
|
u32 ctl9;
|
||||||
u_int32_t ctl10;
|
u32 ctl10;
|
||||||
u_int32_t ctl11;
|
u32 ctl11;
|
||||||
u_int32_t status0;
|
u32 status0;
|
||||||
u_int32_t status1;
|
u32 status1;
|
||||||
u_int32_t status2;
|
u32 status2;
|
||||||
u_int32_t status3;
|
u32 status3;
|
||||||
u_int32_t status4;
|
u32 status4;
|
||||||
u_int32_t status5;
|
u32 status5;
|
||||||
u_int32_t status6;
|
u32 status6;
|
||||||
u_int32_t status7;
|
u32 status7;
|
||||||
u_int32_t status8;
|
u32 status8;
|
||||||
u_int32_t status9;
|
u32 status9;
|
||||||
} tx;
|
} tx;
|
||||||
struct {
|
struct {
|
||||||
u_int32_t status0;
|
u32 status0;
|
||||||
u_int32_t status1;
|
u32 status1;
|
||||||
u_int32_t status2;
|
u32 status2;
|
||||||
u_int32_t status3;
|
u32 status3;
|
||||||
u_int32_t status4;
|
u32 status4;
|
||||||
u_int32_t status5;
|
u32 status5;
|
||||||
u_int32_t status6;
|
u32 status6;
|
||||||
u_int32_t status7;
|
u32 status7;
|
||||||
u_int32_t status8;
|
u32 status8;
|
||||||
} rx;
|
} rx;
|
||||||
} u;
|
} u;
|
||||||
} __packed;
|
} __packed;
|
||||||
@ -326,13 +326,13 @@ struct ar5416_desc {
|
|||||||
|
|
||||||
#define set11nPktDurRTSCTS(_series, _index) \
|
#define set11nPktDurRTSCTS(_series, _index) \
|
||||||
(SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
|
(SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
|
||||||
((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ? \
|
((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
|
||||||
AR_RTSCTSQual##_index : 0))
|
AR_RTSCTSQual##_index : 0))
|
||||||
|
|
||||||
#define set11nRateFlags(_series, _index) \
|
#define set11nRateFlags(_series, _index) \
|
||||||
(((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? \
|
(((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
|
||||||
AR_2040_##_index : 0) \
|
AR_2040_##_index : 0) \
|
||||||
|((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? \
|
|((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
|
||||||
AR_GI##_index : 0) \
|
AR_GI##_index : 0) \
|
||||||
|SM((_series)[_index].ChSel, AR_ChainSel##_index))
|
|SM((_series)[_index].ChSel, AR_ChainSel##_index))
|
||||||
|
|
||||||
@ -350,27 +350,27 @@ struct ar5416_desc {
|
|||||||
#define CCK_OFDM_GAIN_DELTA 15
|
#define CCK_OFDM_GAIN_DELTA 15
|
||||||
|
|
||||||
struct ar5416AniState {
|
struct ar5416AniState {
|
||||||
struct hal_channel c;
|
struct ath9k_channel c;
|
||||||
u_int8_t noiseImmunityLevel;
|
u8 noiseImmunityLevel;
|
||||||
u_int8_t spurImmunityLevel;
|
u8 spurImmunityLevel;
|
||||||
u_int8_t firstepLevel;
|
u8 firstepLevel;
|
||||||
u_int8_t ofdmWeakSigDetectOff;
|
u8 ofdmWeakSigDetectOff;
|
||||||
u_int8_t cckWeakSigThreshold;
|
u8 cckWeakSigThreshold;
|
||||||
u_int32_t listenTime;
|
u32 listenTime;
|
||||||
u_int32_t ofdmTrigHigh;
|
u32 ofdmTrigHigh;
|
||||||
u_int32_t ofdmTrigLow;
|
u32 ofdmTrigLow;
|
||||||
int32_t cckTrigHigh;
|
int32_t cckTrigHigh;
|
||||||
int32_t cckTrigLow;
|
int32_t cckTrigLow;
|
||||||
int32_t rssiThrLow;
|
int32_t rssiThrLow;
|
||||||
int32_t rssiThrHigh;
|
int32_t rssiThrHigh;
|
||||||
u_int32_t noiseFloor;
|
u32 noiseFloor;
|
||||||
u_int32_t txFrameCount;
|
u32 txFrameCount;
|
||||||
u_int32_t rxFrameCount;
|
u32 rxFrameCount;
|
||||||
u_int32_t cycleCount;
|
u32 cycleCount;
|
||||||
u_int32_t ofdmPhyErrCount;
|
u32 ofdmPhyErrCount;
|
||||||
u_int32_t cckPhyErrCount;
|
u32 cckPhyErrCount;
|
||||||
u_int32_t ofdmPhyErrBase;
|
u32 ofdmPhyErrBase;
|
||||||
u_int32_t cckPhyErrBase;
|
u32 cckPhyErrBase;
|
||||||
int16_t pktRssi[2];
|
int16_t pktRssi[2];
|
||||||
int16_t ofdmErrRssi[2];
|
int16_t ofdmErrRssi[2];
|
||||||
int16_t cckErrRssi[2];
|
int16_t cckErrRssi[2];
|
||||||
@ -384,23 +384,23 @@ struct ar5416AniState {
|
|||||||
((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
|
((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
|
||||||
|
|
||||||
struct ar5416Stats {
|
struct ar5416Stats {
|
||||||
u_int32_t ast_ani_niup;
|
u32 ast_ani_niup;
|
||||||
u_int32_t ast_ani_nidown;
|
u32 ast_ani_nidown;
|
||||||
u_int32_t ast_ani_spurup;
|
u32 ast_ani_spurup;
|
||||||
u_int32_t ast_ani_spurdown;
|
u32 ast_ani_spurdown;
|
||||||
u_int32_t ast_ani_ofdmon;
|
u32 ast_ani_ofdmon;
|
||||||
u_int32_t ast_ani_ofdmoff;
|
u32 ast_ani_ofdmoff;
|
||||||
u_int32_t ast_ani_cckhigh;
|
u32 ast_ani_cckhigh;
|
||||||
u_int32_t ast_ani_ccklow;
|
u32 ast_ani_ccklow;
|
||||||
u_int32_t ast_ani_stepup;
|
u32 ast_ani_stepup;
|
||||||
u_int32_t ast_ani_stepdown;
|
u32 ast_ani_stepdown;
|
||||||
u_int32_t ast_ani_ofdmerrs;
|
u32 ast_ani_ofdmerrs;
|
||||||
u_int32_t ast_ani_cckerrs;
|
u32 ast_ani_cckerrs;
|
||||||
u_int32_t ast_ani_reset;
|
u32 ast_ani_reset;
|
||||||
u_int32_t ast_ani_lzero;
|
u32 ast_ani_lzero;
|
||||||
u_int32_t ast_ani_lneg;
|
u32 ast_ani_lneg;
|
||||||
struct hal_mib_stats ast_mibstats;
|
struct ath9k_mib_stats ast_mibstats;
|
||||||
struct hal_node_stats ast_nodestats;
|
struct ath9k_node_stats ast_nodestats;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define AR5416_OPFLAGS_11A 0x01
|
#define AR5416_OPFLAGS_11A 0x01
|
||||||
@ -495,100 +495,100 @@ enum ar5416_rates {
|
|||||||
};
|
};
|
||||||
|
|
||||||
struct base_eep_header {
|
struct base_eep_header {
|
||||||
u_int16_t length;
|
u16 length;
|
||||||
u_int16_t checksum;
|
u16 checksum;
|
||||||
u_int16_t version;
|
u16 version;
|
||||||
u_int8_t opCapFlags;
|
u8 opCapFlags;
|
||||||
u_int8_t eepMisc;
|
u8 eepMisc;
|
||||||
u_int16_t regDmn[2];
|
u16 regDmn[2];
|
||||||
u_int8_t macAddr[6];
|
u8 macAddr[6];
|
||||||
u_int8_t rxMask;
|
u8 rxMask;
|
||||||
u_int8_t txMask;
|
u8 txMask;
|
||||||
u_int16_t rfSilent;
|
u16 rfSilent;
|
||||||
u_int16_t blueToothOptions;
|
u16 blueToothOptions;
|
||||||
u_int16_t deviceCap;
|
u16 deviceCap;
|
||||||
u_int32_t binBuildNumber;
|
u32 binBuildNumber;
|
||||||
u_int8_t deviceType;
|
u8 deviceType;
|
||||||
u_int8_t pwdclkind;
|
u8 pwdclkind;
|
||||||
u_int8_t futureBase[32];
|
u8 futureBase[32];
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
struct spur_chan {
|
struct spur_chan {
|
||||||
u_int16_t spurChan;
|
u16 spurChan;
|
||||||
u_int8_t spurRangeLow;
|
u8 spurRangeLow;
|
||||||
u_int8_t spurRangeHigh;
|
u8 spurRangeHigh;
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
struct modal_eep_header {
|
struct modal_eep_header {
|
||||||
u_int32_t antCtrlChain[AR5416_MAX_CHAINS];
|
u32 antCtrlChain[AR5416_MAX_CHAINS];
|
||||||
u_int32_t antCtrlCommon;
|
u32 antCtrlCommon;
|
||||||
u_int8_t antennaGainCh[AR5416_MAX_CHAINS];
|
u8 antennaGainCh[AR5416_MAX_CHAINS];
|
||||||
u_int8_t switchSettling;
|
u8 switchSettling;
|
||||||
u_int8_t txRxAttenCh[AR5416_MAX_CHAINS];
|
u8 txRxAttenCh[AR5416_MAX_CHAINS];
|
||||||
u_int8_t rxTxMarginCh[AR5416_MAX_CHAINS];
|
u8 rxTxMarginCh[AR5416_MAX_CHAINS];
|
||||||
u_int8_t adcDesiredSize;
|
u8 adcDesiredSize;
|
||||||
u_int8_t pgaDesiredSize;
|
u8 pgaDesiredSize;
|
||||||
u_int8_t xlnaGainCh[AR5416_MAX_CHAINS];
|
u8 xlnaGainCh[AR5416_MAX_CHAINS];
|
||||||
u_int8_t txEndToXpaOff;
|
u8 txEndToXpaOff;
|
||||||
u_int8_t txEndToRxOn;
|
u8 txEndToRxOn;
|
||||||
u_int8_t txFrameToXpaOn;
|
u8 txFrameToXpaOn;
|
||||||
u_int8_t thresh62;
|
u8 thresh62;
|
||||||
u_int8_t noiseFloorThreshCh[AR5416_MAX_CHAINS];
|
u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
|
||||||
u_int8_t xpdGain;
|
u8 xpdGain;
|
||||||
u_int8_t xpd;
|
u8 xpd;
|
||||||
u_int8_t iqCalICh[AR5416_MAX_CHAINS];
|
u8 iqCalICh[AR5416_MAX_CHAINS];
|
||||||
u_int8_t iqCalQCh[AR5416_MAX_CHAINS];
|
u8 iqCalQCh[AR5416_MAX_CHAINS];
|
||||||
u_int8_t pdGainOverlap;
|
u8 pdGainOverlap;
|
||||||
u_int8_t ob;
|
u8 ob;
|
||||||
u_int8_t db;
|
u8 db;
|
||||||
u_int8_t xpaBiasLvl;
|
u8 xpaBiasLvl;
|
||||||
u_int8_t pwrDecreaseFor2Chain;
|
u8 pwrDecreaseFor2Chain;
|
||||||
u_int8_t pwrDecreaseFor3Chain;
|
u8 pwrDecreaseFor3Chain;
|
||||||
u_int8_t txFrameToDataStart;
|
u8 txFrameToDataStart;
|
||||||
u_int8_t txFrameToPaOn;
|
u8 txFrameToPaOn;
|
||||||
u_int8_t ht40PowerIncForPdadc;
|
u8 ht40PowerIncForPdadc;
|
||||||
u_int8_t bswAtten[AR5416_MAX_CHAINS];
|
u8 bswAtten[AR5416_MAX_CHAINS];
|
||||||
u_int8_t bswMargin[AR5416_MAX_CHAINS];
|
u8 bswMargin[AR5416_MAX_CHAINS];
|
||||||
u_int8_t swSettleHt40;
|
u8 swSettleHt40;
|
||||||
u_int8_t xatten2Db[AR5416_MAX_CHAINS];
|
u8 xatten2Db[AR5416_MAX_CHAINS];
|
||||||
u_int8_t xatten2Margin[AR5416_MAX_CHAINS];
|
u8 xatten2Margin[AR5416_MAX_CHAINS];
|
||||||
u_int8_t ob_ch1;
|
u8 ob_ch1;
|
||||||
u_int8_t db_ch1;
|
u8 db_ch1;
|
||||||
u_int8_t useAnt1:1,
|
u8 useAnt1:1,
|
||||||
force_xpaon:1,
|
force_xpaon:1,
|
||||||
local_bias:1,
|
local_bias:1,
|
||||||
femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
|
femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
|
||||||
u_int8_t futureModalar9280;
|
u8 futureModalar9280;
|
||||||
u_int16_t xpaBiasLvlFreq[3];
|
u16 xpaBiasLvlFreq[3];
|
||||||
u_int8_t futureModal[6];
|
u8 futureModal[6];
|
||||||
|
|
||||||
struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
|
struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
struct cal_data_per_freq {
|
struct cal_data_per_freq {
|
||||||
u_int8_t pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||||
u_int8_t vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
struct cal_target_power_leg {
|
struct cal_target_power_leg {
|
||||||
u_int8_t bChannel;
|
u8 bChannel;
|
||||||
u_int8_t tPow2x[4];
|
u8 tPow2x[4];
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
struct cal_target_power_ht {
|
struct cal_target_power_ht {
|
||||||
u_int8_t bChannel;
|
u8 bChannel;
|
||||||
u_int8_t tPow2x[8];
|
u8 tPow2x[8];
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
#ifdef __BIG_ENDIAN_BITFIELD
|
#ifdef __BIG_ENDIAN_BITFIELD
|
||||||
struct cal_ctl_edges {
|
struct cal_ctl_edges {
|
||||||
u_int8_t bChannel;
|
u8 bChannel;
|
||||||
u_int8_t flag:2, tPower:6;
|
u8 flag:2, tPower:6;
|
||||||
} __packed;
|
} __packed;
|
||||||
#else
|
#else
|
||||||
struct cal_ctl_edges {
|
struct cal_ctl_edges {
|
||||||
u_int8_t bChannel;
|
u8 bChannel;
|
||||||
u_int8_t tPower:6, flag:2;
|
u8 tPower:6, flag:2;
|
||||||
} __packed;
|
} __packed;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -599,10 +599,10 @@ struct cal_ctl_data {
|
|||||||
|
|
||||||
struct ar5416_eeprom {
|
struct ar5416_eeprom {
|
||||||
struct base_eep_header baseEepHeader;
|
struct base_eep_header baseEepHeader;
|
||||||
u_int8_t custData[64];
|
u8 custData[64];
|
||||||
struct modal_eep_header modalHeader[2];
|
struct modal_eep_header modalHeader[2];
|
||||||
u_int8_t calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
|
u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
|
||||||
u_int8_t calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
|
u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
|
||||||
struct cal_data_per_freq
|
struct cal_data_per_freq
|
||||||
calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
|
calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
|
||||||
struct cal_data_per_freq
|
struct cal_data_per_freq
|
||||||
@ -621,19 +621,19 @@ struct ar5416_eeprom {
|
|||||||
calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
|
calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
|
||||||
struct cal_target_power_ht
|
struct cal_target_power_ht
|
||||||
calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
|
calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
|
||||||
u_int8_t ctlIndex[AR5416_NUM_CTLS];
|
u8 ctlIndex[AR5416_NUM_CTLS];
|
||||||
struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
|
struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
|
||||||
u_int8_t padding;
|
u8 padding;
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
struct ar5416IniArray {
|
struct ar5416IniArray {
|
||||||
u_int32_t *ia_array;
|
u32 *ia_array;
|
||||||
u_int32_t ia_rows;
|
u32 ia_rows;
|
||||||
u_int32_t ia_columns;
|
u32 ia_columns;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
|
#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
|
||||||
(iniarray)->ia_array = (u_int32_t *)(array); \
|
(iniarray)->ia_array = (u32 *)(array); \
|
||||||
(iniarray)->ia_rows = (rows); \
|
(iniarray)->ia_rows = (rows); \
|
||||||
(iniarray)->ia_columns = (columns); \
|
(iniarray)->ia_columns = (columns); \
|
||||||
} while (0)
|
} while (0)
|
||||||
@ -681,10 +681,10 @@ enum hal_cal_state {
|
|||||||
|
|
||||||
struct hal_percal_data {
|
struct hal_percal_data {
|
||||||
enum hal_cal_types calType;
|
enum hal_cal_types calType;
|
||||||
u_int32_t calNumSamples;
|
u32 calNumSamples;
|
||||||
u_int32_t calCountMax;
|
u32 calCountMax;
|
||||||
void (*calCollect) (struct ath_hal *);
|
void (*calCollect) (struct ath_hal *);
|
||||||
void (*calPostProc) (struct ath_hal *, u_int8_t);
|
void (*calPostProc) (struct ath_hal *, u8);
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_cal_list {
|
struct hal_cal_list {
|
||||||
@ -696,25 +696,25 @@ struct hal_cal_list {
|
|||||||
struct ath_hal_5416 {
|
struct ath_hal_5416 {
|
||||||
struct ath_hal ah;
|
struct ath_hal ah;
|
||||||
struct ar5416_eeprom ah_eeprom;
|
struct ar5416_eeprom ah_eeprom;
|
||||||
u_int8_t ah_macaddr[ETH_ALEN];
|
u8 ah_macaddr[ETH_ALEN];
|
||||||
u_int8_t ah_bssid[ETH_ALEN];
|
u8 ah_bssid[ETH_ALEN];
|
||||||
u_int8_t ah_bssidmask[ETH_ALEN];
|
u8 ah_bssidmask[ETH_ALEN];
|
||||||
u_int16_t ah_assocId;
|
u16 ah_assocId;
|
||||||
int16_t ah_curchanRadIndex;
|
int16_t ah_curchanRadIndex;
|
||||||
u_int32_t ah_maskReg;
|
u32 ah_maskReg;
|
||||||
struct ar5416Stats ah_stats;
|
struct ar5416Stats ah_stats;
|
||||||
u_int32_t ah_txDescMask;
|
u32 ah_txDescMask;
|
||||||
u_int32_t ah_txOkInterruptMask;
|
u32 ah_txOkInterruptMask;
|
||||||
u_int32_t ah_txErrInterruptMask;
|
u32 ah_txErrInterruptMask;
|
||||||
u_int32_t ah_txDescInterruptMask;
|
u32 ah_txDescInterruptMask;
|
||||||
u_int32_t ah_txEolInterruptMask;
|
u32 ah_txEolInterruptMask;
|
||||||
u_int32_t ah_txUrnInterruptMask;
|
u32 ah_txUrnInterruptMask;
|
||||||
struct hal_tx_queue_info ah_txq[HAL_NUM_TX_QUEUES];
|
struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
|
||||||
enum hal_power_mode ah_powerMode;
|
enum ath9k_power_mode ah_powerMode;
|
||||||
bool ah_chipFullSleep;
|
bool ah_chipFullSleep;
|
||||||
u_int32_t ah_atimWindow;
|
u32 ah_atimWindow;
|
||||||
enum hal_ant_setting ah_diversityControl;
|
enum ath9k_ant_setting ah_diversityControl;
|
||||||
u_int16_t ah_antennaSwitchSwap;
|
u16 ah_antennaSwitchSwap;
|
||||||
enum hal_cal_types ah_suppCals;
|
enum hal_cal_types ah_suppCals;
|
||||||
struct hal_cal_list ah_iqCalData;
|
struct hal_cal_list ah_iqCalData;
|
||||||
struct hal_cal_list ah_adcGainCalData;
|
struct hal_cal_list ah_adcGainCalData;
|
||||||
@ -735,73 +735,73 @@ struct ath_hal_5416 {
|
|||||||
#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign
|
#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign
|
||||||
#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
|
#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign
|
||||||
union {
|
union {
|
||||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
u32 unsign[AR5416_MAX_CHAINS];
|
||||||
int32_t sign[AR5416_MAX_CHAINS];
|
int32_t sign[AR5416_MAX_CHAINS];
|
||||||
} ah_Meas0;
|
} ah_Meas0;
|
||||||
union {
|
union {
|
||||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
u32 unsign[AR5416_MAX_CHAINS];
|
||||||
int32_t sign[AR5416_MAX_CHAINS];
|
int32_t sign[AR5416_MAX_CHAINS];
|
||||||
} ah_Meas1;
|
} ah_Meas1;
|
||||||
union {
|
union {
|
||||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
u32 unsign[AR5416_MAX_CHAINS];
|
||||||
int32_t sign[AR5416_MAX_CHAINS];
|
int32_t sign[AR5416_MAX_CHAINS];
|
||||||
} ah_Meas2;
|
} ah_Meas2;
|
||||||
union {
|
union {
|
||||||
u_int32_t unsign[AR5416_MAX_CHAINS];
|
u32 unsign[AR5416_MAX_CHAINS];
|
||||||
int32_t sign[AR5416_MAX_CHAINS];
|
int32_t sign[AR5416_MAX_CHAINS];
|
||||||
} ah_Meas3;
|
} ah_Meas3;
|
||||||
u_int16_t ah_CalSamples;
|
u16 ah_CalSamples;
|
||||||
u_int32_t ah_tx6PowerInHalfDbm;
|
u32 ah_tx6PowerInHalfDbm;
|
||||||
u_int32_t ah_staId1Defaults;
|
u32 ah_staId1Defaults;
|
||||||
u_int32_t ah_miscMode;
|
u32 ah_miscMode;
|
||||||
bool ah_tpcEnabled;
|
bool ah_tpcEnabled;
|
||||||
u_int32_t ah_beaconInterval;
|
u32 ah_beaconInterval;
|
||||||
enum {
|
enum {
|
||||||
AUTO_32KHZ,
|
AUTO_32KHZ,
|
||||||
USE_32KHZ,
|
USE_32KHZ,
|
||||||
DONT_USE_32KHZ,
|
DONT_USE_32KHZ,
|
||||||
} ah_enable32kHzClock;
|
} ah_enable32kHzClock;
|
||||||
u_int32_t *ah_analogBank0Data;
|
u32 *ah_analogBank0Data;
|
||||||
u_int32_t *ah_analogBank1Data;
|
u32 *ah_analogBank1Data;
|
||||||
u_int32_t *ah_analogBank2Data;
|
u32 *ah_analogBank2Data;
|
||||||
u_int32_t *ah_analogBank3Data;
|
u32 *ah_analogBank3Data;
|
||||||
u_int32_t *ah_analogBank6Data;
|
u32 *ah_analogBank6Data;
|
||||||
u_int32_t *ah_analogBank6TPCData;
|
u32 *ah_analogBank6TPCData;
|
||||||
u_int32_t *ah_analogBank7Data;
|
u32 *ah_analogBank7Data;
|
||||||
u_int32_t *ah_addac5416_21;
|
u32 *ah_addac5416_21;
|
||||||
u_int32_t *ah_bank6Temp;
|
u32 *ah_bank6Temp;
|
||||||
u_int32_t ah_ofdmTxPower;
|
u32 ah_ofdmTxPower;
|
||||||
int16_t ah_txPowerIndexOffset;
|
int16_t ah_txPowerIndexOffset;
|
||||||
u_int ah_slottime;
|
u32 ah_slottime;
|
||||||
u_int ah_acktimeout;
|
u32 ah_acktimeout;
|
||||||
u_int ah_ctstimeout;
|
u32 ah_ctstimeout;
|
||||||
u_int ah_globaltxtimeout;
|
u32 ah_globaltxtimeout;
|
||||||
u_int8_t ah_gBeaconRate;
|
u8 ah_gBeaconRate;
|
||||||
u_int32_t ah_gpioSelect;
|
u32 ah_gpioSelect;
|
||||||
u_int32_t ah_polarity;
|
u32 ah_polarity;
|
||||||
u_int32_t ah_gpioBit;
|
u32 ah_gpioBit;
|
||||||
bool ah_eepEnabled;
|
bool ah_eepEnabled;
|
||||||
u_int32_t ah_procPhyErr;
|
u32 ah_procPhyErr;
|
||||||
bool ah_hasHwPhyCounters;
|
bool ah_hasHwPhyCounters;
|
||||||
u_int32_t ah_aniPeriod;
|
u32 ah_aniPeriod;
|
||||||
struct ar5416AniState *ah_curani;
|
struct ar5416AniState *ah_curani;
|
||||||
struct ar5416AniState ah_ani[255];
|
struct ar5416AniState ah_ani[255];
|
||||||
int ah_totalSizeDesired[5];
|
int ah_totalSizeDesired[5];
|
||||||
int ah_coarseHigh[5];
|
int ah_coarseHigh[5];
|
||||||
int ah_coarseLow[5];
|
int ah_coarseLow[5];
|
||||||
int ah_firpwr[5];
|
int ah_firpwr[5];
|
||||||
u_int16_t ah_ratesArray[16];
|
u16 ah_ratesArray[16];
|
||||||
u_int32_t ah_intrTxqs;
|
u32 ah_intrTxqs;
|
||||||
bool ah_intrMitigation;
|
bool ah_intrMitigation;
|
||||||
u_int32_t ah_cycleCount;
|
u32 ah_cycleCount;
|
||||||
u_int32_t ah_ctlBusy;
|
u32 ah_ctlBusy;
|
||||||
u_int32_t ah_extBusy;
|
u32 ah_extBusy;
|
||||||
enum hal_ht_extprotspacing ah_extprotspacing;
|
enum ath9k_ht_extprotspacing ah_extprotspacing;
|
||||||
u_int8_t ah_txchainmask;
|
u8 ah_txchainmask;
|
||||||
u_int8_t ah_rxchainmask;
|
u8 ah_rxchainmask;
|
||||||
int ah_hwp;
|
int ah_hwp;
|
||||||
void __iomem *ah_cal_mem;
|
void __iomem *ah_cal_mem;
|
||||||
enum hal_ani_cmd ah_ani_function;
|
enum ath9k_ani_cmd ah_ani_function;
|
||||||
struct ar5416IniArray ah_iniModes;
|
struct ar5416IniArray ah_iniModes;
|
||||||
struct ar5416IniArray ah_iniCommon;
|
struct ar5416IniArray ah_iniCommon;
|
||||||
struct ar5416IniArray ah_iniBank0;
|
struct ar5416IniArray ah_iniBank0;
|
||||||
@ -853,8 +853,8 @@ struct ath_hal_5416 {
|
|||||||
#define HT40_CHANNEL_CENTER_SHIFT 10
|
#define HT40_CHANNEL_CENTER_SHIFT 10
|
||||||
|
|
||||||
#define ar5416CheckOpMode(_opmode) \
|
#define ar5416CheckOpMode(_opmode) \
|
||||||
((_opmode == HAL_M_STA) || (_opmode == HAL_M_IBSS) || \
|
((_opmode == ATH9K_M_STA) || (_opmode == ATH9K_M_IBSS) || \
|
||||||
(_opmode == HAL_M_HOSTAP) || (_opmode == HAL_M_MONITOR))
|
(_opmode == ATH9K_M_HOSTAP) || (_opmode == ATH9K_M_MONITOR))
|
||||||
|
|
||||||
#define AR5416_EEPROM_MAGIC_OFFSET 0x0
|
#define AR5416_EEPROM_MAGIC_OFFSET 0x0
|
||||||
|
|
||||||
@ -894,18 +894,18 @@ struct ath_hal_5416 {
|
|||||||
#define HAL_SPUR_IMMUNE_MAX 7
|
#define HAL_SPUR_IMMUNE_MAX 7
|
||||||
#define HAL_FIRST_STEP_MAX 2
|
#define HAL_FIRST_STEP_MAX 2
|
||||||
|
|
||||||
#define HAL_ANI_OFDM_TRIG_HIGH 500
|
#define ATH9K_ANI_OFDM_TRIG_HIGH 500
|
||||||
#define HAL_ANI_OFDM_TRIG_LOW 200
|
#define ATH9K_ANI_OFDM_TRIG_LOW 200
|
||||||
#define HAL_ANI_CCK_TRIG_HIGH 200
|
#define ATH9K_ANI_CCK_TRIG_HIGH 200
|
||||||
#define HAL_ANI_CCK_TRIG_LOW 100
|
#define ATH9K_ANI_CCK_TRIG_LOW 100
|
||||||
#define HAL_ANI_NOISE_IMMUNE_LVL 4
|
#define ATH9K_ANI_NOISE_IMMUNE_LVL 4
|
||||||
#define HAL_ANI_USE_OFDM_WEAK_SIG true
|
#define ATH9K_ANI_USE_OFDM_WEAK_SIG true
|
||||||
#define HAL_ANI_CCK_WEAK_SIG_THR false
|
#define ATH9K_ANI_CCK_WEAK_SIG_THR false
|
||||||
#define HAL_ANI_SPUR_IMMUNE_LVL 7
|
#define ATH9K_ANI_SPUR_IMMUNE_LVL 7
|
||||||
#define HAL_ANI_FIRSTEP_LVL 0
|
#define ATH9K_ANI_FIRSTEP_LVL 0
|
||||||
#define HAL_ANI_RSSI_THR_HIGH 40
|
#define ATH9K_ANI_RSSI_THR_HIGH 40
|
||||||
#define HAL_ANI_RSSI_THR_LOW 7
|
#define ATH9K_ANI_RSSI_THR_LOW 7
|
||||||
#define HAL_ANI_PERIOD 100
|
#define ATH9K_ANI_PERIOD 100
|
||||||
|
|
||||||
#define AR_GPIOD_MASK 0x00001FFF
|
#define AR_GPIOD_MASK 0x00001FFF
|
||||||
#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
|
#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
|
||||||
@ -916,7 +916,7 @@ struct ath_hal_5416 {
|
|||||||
((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
|
((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
|
||||||
#define BEACON_RSSI(ahp) \
|
#define BEACON_RSSI(ahp) \
|
||||||
HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
|
HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
|
||||||
HAL_RSSI_EP_MULTIPLIER)
|
ATH9K_RSSI_EP_MULTIPLIER)
|
||||||
|
|
||||||
#define ah_mibStats ah_stats.ast_mibstats
|
#define ah_mibStats ah_stats.ast_mibstats
|
||||||
|
|
||||||
@ -963,7 +963,7 @@ struct ath_hal_5416 {
|
|||||||
#define OFDM_PLCP_BITS_QUARTER 22
|
#define OFDM_PLCP_BITS_QUARTER 22
|
||||||
#define OFDM_SYMBOL_TIME_QUARTER 16
|
#define OFDM_SYMBOL_TIME_QUARTER 16
|
||||||
|
|
||||||
u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
|
u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
|
||||||
enum eeprom_param param);
|
enum eeprom_param param);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -14,7 +14,7 @@
|
|||||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static const u_int32_t ar5416Modes_9100[][6] = {
|
static const u32 ar5416Modes_9100[][6] = {
|
||||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||||
@ -78,7 +78,7 @@ static const u_int32_t ar5416Modes_9100[][6] = {
|
|||||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
{ 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Common_9100[][2] = {
|
static const u32 ar5416Common_9100[][2] = {
|
||||||
{ 0x0000000c, 0x00000000 },
|
{ 0x0000000c, 0x00000000 },
|
||||||
{ 0x00000030, 0x00020015 },
|
{ 0x00000030, 0x00020015 },
|
||||||
{ 0x00000034, 0x00000005 },
|
{ 0x00000034, 0x00000005 },
|
||||||
@ -456,12 +456,12 @@ static const u_int32_t ar5416Common_9100[][2] = {
|
|||||||
{ 0x0000a3e0, 0x000001ce },
|
{ 0x0000a3e0, 0x000001ce },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank0_9100[][2] = {
|
static const u32 ar5416Bank0_9100[][2] = {
|
||||||
{ 0x000098b0, 0x1e5795e5 },
|
{ 0x000098b0, 0x1e5795e5 },
|
||||||
{ 0x000098e0, 0x02008020 },
|
{ 0x000098e0, 0x02008020 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416BB_RfGain_9100[][3] = {
|
static const u32 ar5416BB_RfGain_9100[][3] = {
|
||||||
{ 0x00009a00, 0x00000000, 0x00000000 },
|
{ 0x00009a00, 0x00000000, 0x00000000 },
|
||||||
{ 0x00009a04, 0x00000040, 0x00000040 },
|
{ 0x00009a04, 0x00000040, 0x00000040 },
|
||||||
{ 0x00009a08, 0x00000080, 0x00000080 },
|
{ 0x00009a08, 0x00000080, 0x00000080 },
|
||||||
@ -528,21 +528,21 @@ static const u_int32_t ar5416BB_RfGain_9100[][3] = {
|
|||||||
{ 0x00009afc, 0x000000f9, 0x000000f9 },
|
{ 0x00009afc, 0x000000f9, 0x000000f9 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank1_9100[][2] = {
|
static const u32 ar5416Bank1_9100[][2] = {
|
||||||
{ 0x000098b0, 0x02108421 },
|
{ 0x000098b0, 0x02108421 },
|
||||||
{ 0x000098ec, 0x00000008 },
|
{ 0x000098ec, 0x00000008 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank2_9100[][2] = {
|
static const u32 ar5416Bank2_9100[][2] = {
|
||||||
{ 0x000098b0, 0x0e73ff17 },
|
{ 0x000098b0, 0x0e73ff17 },
|
||||||
{ 0x000098e0, 0x00000420 },
|
{ 0x000098e0, 0x00000420 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank3_9100[][3] = {
|
static const u32 ar5416Bank3_9100[][3] = {
|
||||||
{ 0x000098f0, 0x01400018, 0x01c00018 },
|
{ 0x000098f0, 0x01400018, 0x01c00018 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank6_9100[][3] = {
|
static const u32 ar5416Bank6_9100[][3] = {
|
||||||
|
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
@ -579,7 +579,7 @@ static const u_int32_t ar5416Bank6_9100[][3] = {
|
|||||||
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank6TPC_9100[][3] = {
|
static const u32 ar5416Bank6TPC_9100[][3] = {
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
@ -615,13 +615,13 @@ static const u_int32_t ar5416Bank6TPC_9100[][3] = {
|
|||||||
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank7_9100[][2] = {
|
static const u32 ar5416Bank7_9100[][2] = {
|
||||||
{ 0x0000989c, 0x00000500 },
|
{ 0x0000989c, 0x00000500 },
|
||||||
{ 0x0000989c, 0x00000800 },
|
{ 0x0000989c, 0x00000800 },
|
||||||
{ 0x000098cc, 0x0000000e },
|
{ 0x000098cc, 0x0000000e },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Addac_9100[][2] = {
|
static const u32 ar5416Addac_9100[][2] = {
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
{0x0000989c, 0x00000003 },
|
{0x0000989c, 0x00000003 },
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
@ -661,7 +661,7 @@ static const u_int32_t ar5416Addac_9100[][2] = {
|
|||||||
{0x000098c4, 0x00000000 },
|
{0x000098c4, 0x00000000 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Modes[][6] = {
|
static const u32 ar5416Modes[][6] = {
|
||||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||||
@ -735,7 +735,7 @@ static const u_int32_t ar5416Modes[][6] = {
|
|||||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
{ 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Common[][2] = {
|
static const u32 ar5416Common[][2] = {
|
||||||
{ 0x0000000c, 0x00000000 },
|
{ 0x0000000c, 0x00000000 },
|
||||||
{ 0x00000030, 0x00020015 },
|
{ 0x00000030, 0x00020015 },
|
||||||
{ 0x00000034, 0x00000005 },
|
{ 0x00000034, 0x00000005 },
|
||||||
@ -1109,12 +1109,12 @@ static const u_int32_t ar5416Common[][2] = {
|
|||||||
{ 0x0000a3e0, 0x000001ce },
|
{ 0x0000a3e0, 0x000001ce },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank0[][2] = {
|
static const u32 ar5416Bank0[][2] = {
|
||||||
{ 0x000098b0, 0x1e5795e5 },
|
{ 0x000098b0, 0x1e5795e5 },
|
||||||
{ 0x000098e0, 0x02008020 },
|
{ 0x000098e0, 0x02008020 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416BB_RfGain[][3] = {
|
static const u32 ar5416BB_RfGain[][3] = {
|
||||||
{ 0x00009a00, 0x00000000, 0x00000000 },
|
{ 0x00009a00, 0x00000000, 0x00000000 },
|
||||||
{ 0x00009a04, 0x00000040, 0x00000040 },
|
{ 0x00009a04, 0x00000040, 0x00000040 },
|
||||||
{ 0x00009a08, 0x00000080, 0x00000080 },
|
{ 0x00009a08, 0x00000080, 0x00000080 },
|
||||||
@ -1181,21 +1181,21 @@ static const u_int32_t ar5416BB_RfGain[][3] = {
|
|||||||
{ 0x00009afc, 0x000000f9, 0x000000f9 },
|
{ 0x00009afc, 0x000000f9, 0x000000f9 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank1[][2] = {
|
static const u32 ar5416Bank1[][2] = {
|
||||||
{ 0x000098b0, 0x02108421},
|
{ 0x000098b0, 0x02108421},
|
||||||
{ 0x000098ec, 0x00000008},
|
{ 0x000098ec, 0x00000008},
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank2[][2] = {
|
static const u32 ar5416Bank2[][2] = {
|
||||||
{ 0x000098b0, 0x0e73ff17},
|
{ 0x000098b0, 0x0e73ff17},
|
||||||
{ 0x000098e0, 0x00000420},
|
{ 0x000098e0, 0x00000420},
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank3[][3] = {
|
static const u32 ar5416Bank3[][3] = {
|
||||||
{ 0x000098f0, 0x01400018, 0x01c00018 },
|
{ 0x000098f0, 0x01400018, 0x01c00018 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank6[][3] = {
|
static const u32 ar5416Bank6[][3] = {
|
||||||
|
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
@ -1233,7 +1233,7 @@ static const u_int32_t ar5416Bank6[][3] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank6TPC[][3] = {
|
static const u32 ar5416Bank6TPC[][3] = {
|
||||||
|
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
@ -1270,13 +1270,13 @@ static const u_int32_t ar5416Bank6TPC[][3] = {
|
|||||||
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank7[][2] = {
|
static const u32 ar5416Bank7[][2] = {
|
||||||
{ 0x0000989c, 0x00000500 },
|
{ 0x0000989c, 0x00000500 },
|
||||||
{ 0x0000989c, 0x00000800 },
|
{ 0x0000989c, 0x00000800 },
|
||||||
{ 0x000098cc, 0x0000000e },
|
{ 0x000098cc, 0x0000000e },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Addac[][2] = {
|
static const u32 ar5416Addac[][2] = {
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
@ -1312,7 +1312,7 @@ static const u_int32_t ar5416Addac[][2] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static const u_int32_t ar5416Modes_9160[][6] = {
|
static const u32 ar5416Modes_9160[][6] = {
|
||||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||||
@ -1376,7 +1376,7 @@ static const u_int32_t ar5416Modes_9160[][6] = {
|
|||||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
{ 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Common_9160[][2] = {
|
static const u32 ar5416Common_9160[][2] = {
|
||||||
{ 0x0000000c, 0x00000000 },
|
{ 0x0000000c, 0x00000000 },
|
||||||
{ 0x00000030, 0x00020015 },
|
{ 0x00000030, 0x00020015 },
|
||||||
{ 0x00000034, 0x00000005 },
|
{ 0x00000034, 0x00000005 },
|
||||||
@ -1755,12 +1755,12 @@ static const u_int32_t ar5416Common_9160[][2] = {
|
|||||||
{ 0x0000a3e0, 0x000001ce },
|
{ 0x0000a3e0, 0x000001ce },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank0_9160[][2] = {
|
static const u32 ar5416Bank0_9160[][2] = {
|
||||||
{ 0x000098b0, 0x1e5795e5 },
|
{ 0x000098b0, 0x1e5795e5 },
|
||||||
{ 0x000098e0, 0x02008020 },
|
{ 0x000098e0, 0x02008020 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416BB_RfGain_9160[][3] = {
|
static const u32 ar5416BB_RfGain_9160[][3] = {
|
||||||
{ 0x00009a00, 0x00000000, 0x00000000 },
|
{ 0x00009a00, 0x00000000, 0x00000000 },
|
||||||
{ 0x00009a04, 0x00000040, 0x00000040 },
|
{ 0x00009a04, 0x00000040, 0x00000040 },
|
||||||
{ 0x00009a08, 0x00000080, 0x00000080 },
|
{ 0x00009a08, 0x00000080, 0x00000080 },
|
||||||
@ -1827,21 +1827,21 @@ static const u_int32_t ar5416BB_RfGain_9160[][3] = {
|
|||||||
{ 0x00009afc, 0x000000f9, 0x000000f9 },
|
{ 0x00009afc, 0x000000f9, 0x000000f9 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank1_9160[][2] = {
|
static const u32 ar5416Bank1_9160[][2] = {
|
||||||
{ 0x000098b0, 0x02108421 },
|
{ 0x000098b0, 0x02108421 },
|
||||||
{ 0x000098ec, 0x00000008 },
|
{ 0x000098ec, 0x00000008 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank2_9160[][2] = {
|
static const u32 ar5416Bank2_9160[][2] = {
|
||||||
{ 0x000098b0, 0x0e73ff17 },
|
{ 0x000098b0, 0x0e73ff17 },
|
||||||
{ 0x000098e0, 0x00000420 },
|
{ 0x000098e0, 0x00000420 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank3_9160[][3] = {
|
static const u32 ar5416Bank3_9160[][3] = {
|
||||||
{ 0x000098f0, 0x01400018, 0x01c00018 },
|
{ 0x000098f0, 0x01400018, 0x01c00018 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank6_9160[][3] = {
|
static const u32 ar5416Bank6_9160[][3] = {
|
||||||
|
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
@ -1878,7 +1878,7 @@ static const u_int32_t ar5416Bank6_9160[][3] = {
|
|||||||
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank6TPC_9160[][3] = {
|
static const u32 ar5416Bank6TPC_9160[][3] = {
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
{ 0x0000989c, 0x00000000, 0x00000000 },
|
{ 0x0000989c, 0x00000000, 0x00000000 },
|
||||||
@ -1914,14 +1914,14 @@ static const u_int32_t ar5416Bank6TPC_9160[][3] = {
|
|||||||
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
{ 0x000098d0, 0x0000000f, 0x0010000f },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar5416Bank7_9160[][2] = {
|
static const u32 ar5416Bank7_9160[][2] = {
|
||||||
{ 0x0000989c, 0x00000500 },
|
{ 0x0000989c, 0x00000500 },
|
||||||
{ 0x0000989c, 0x00000800 },
|
{ 0x0000989c, 0x00000800 },
|
||||||
{ 0x000098cc, 0x0000000e },
|
{ 0x000098cc, 0x0000000e },
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static u_int32_t ar5416Addac_9160[][2] = {
|
static u32 ar5416Addac_9160[][2] = {
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
@ -1957,7 +1957,7 @@ static u_int32_t ar5416Addac_9160[][2] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
static u_int32_t ar5416Addac_91601_1[][2] = {
|
static u32 ar5416Addac_91601_1[][2] = {
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
{0x0000989c, 0x00000000 },
|
{0x0000989c, 0x00000000 },
|
||||||
@ -1994,7 +1994,7 @@ static u_int32_t ar5416Addac_91601_1[][2] = {
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
static const u_int32_t ar9280Modes_9280[][6] = {
|
static const u32 ar9280Modes_9280[][6] = {
|
||||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||||
@ -2196,7 +2196,7 @@ static const u_int32_t ar9280Modes_9280[][6] = {
|
|||||||
{ 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
|
{ 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar9280Common_9280[][2] = {
|
static const u32 ar9280Common_9280[][2] = {
|
||||||
{ 0x0000000c, 0x00000000 },
|
{ 0x0000000c, 0x00000000 },
|
||||||
{ 0x00000030, 0x00020015 },
|
{ 0x00000030, 0x00020015 },
|
||||||
{ 0x00000034, 0x00000005 },
|
{ 0x00000034, 0x00000005 },
|
||||||
@ -2546,7 +2546,7 @@ static const u_int32_t ar9280Common_9280[][2] = {
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
static const u_int32_t ar9280Modes_9280_2[][6] = {
|
static const u32 ar9280Modes_9280_2[][6] = {
|
||||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||||
@ -2750,7 +2750,7 @@ static const u_int32_t ar9280Modes_9280_2[][6] = {
|
|||||||
{ 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
|
{ 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar9280Common_9280_2[][2] = {
|
static const u32 ar9280Common_9280_2[][2] = {
|
||||||
{ 0x0000000c, 0x00000000 },
|
{ 0x0000000c, 0x00000000 },
|
||||||
{ 0x00000030, 0x00020015 },
|
{ 0x00000030, 0x00020015 },
|
||||||
{ 0x00000034, 0x00000005 },
|
{ 0x00000034, 0x00000005 },
|
||||||
@ -3098,7 +3098,7 @@ static const u_int32_t ar9280Common_9280_2[][2] = {
|
|||||||
{ 0x00007898, 0x2a850160 },
|
{ 0x00007898, 0x2a850160 },
|
||||||
};
|
};
|
||||||
|
|
||||||
static const u_int32_t ar9280Modes_fast_clock_9280_2[][3] = {
|
static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
|
||||||
{ 0x00001030, 0x00000268, 0x000004d0 },
|
{ 0x00001030, 0x00000268, 0x000004d0 },
|
||||||
{ 0x00001070, 0x0000018c, 0x00000318 },
|
{ 0x00001070, 0x0000018c, 0x00000318 },
|
||||||
{ 0x000010b0, 0x00000fd0, 0x00001fa0 },
|
{ 0x000010b0, 0x00000fd0, 0x00001fa0 },
|
||||||
@ -3117,7 +3117,7 @@ static const u_int32_t ar9280Modes_fast_clock_9280_2[][3] = {
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
static const u_int32_t ar9280PciePhy_clkreq_off_L1_9280[][2] = {
|
static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
|
||||||
{0x00004040, 0x9248fd00 },
|
{0x00004040, 0x9248fd00 },
|
||||||
{0x00004040, 0x24924924 },
|
{0x00004040, 0x24924924 },
|
||||||
{0x00004040, 0xa8000019 },
|
{0x00004040, 0xa8000019 },
|
||||||
@ -3132,7 +3132,7 @@ static const u_int32_t ar9280PciePhy_clkreq_off_L1_9280[][2] = {
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
static const u_int32_t ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
|
static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
|
||||||
{0x00004040, 0x9248fd00 },
|
{0x00004040, 0x9248fd00 },
|
||||||
{0x00004040, 0x24924924 },
|
{0x00004040, 0x24924924 },
|
||||||
{0x00004040, 0xa8000019 },
|
{0x00004040, 0xa8000019 },
|
||||||
|
@ -41,44 +41,60 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = {
|
|||||||
{ 0 }
|
{ 0 }
|
||||||
};
|
};
|
||||||
|
|
||||||
static int test_update_chan(enum ieee80211_band band,
|
static int ath_get_channel(struct ath_softc *sc,
|
||||||
const struct hal_channel *chan,
|
struct ieee80211_channel *chan)
|
||||||
struct ath_softc *sc)
|
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < sc->sbands[band].n_channels; i++) {
|
for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
|
||||||
if (sc->channels[band][i].center_freq == chan->channel)
|
if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
|
||||||
return 1;
|
return i;
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ath_check_chanflags(struct ieee80211_channel *chan,
|
static u32 ath_get_extchanmode(struct ath_softc *sc,
|
||||||
u_int32_t mode,
|
struct ieee80211_channel *chan)
|
||||||
struct ath_softc *sc)
|
|
||||||
{
|
{
|
||||||
struct ieee80211_hw *hw = sc->hw;
|
u32 chanmode = 0;
|
||||||
struct ieee80211_supported_band *band;
|
u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
|
||||||
struct ieee80211_channel *band_channel;
|
enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
|
||||||
int i;
|
|
||||||
|
|
||||||
band = hw->wiphy->bands[chan->band];
|
switch (chan->band) {
|
||||||
|
case IEEE80211_BAND_2GHZ:
|
||||||
for (i = 0; i < band->n_channels; i++) {
|
if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
|
||||||
band_channel = &band->channels[i];
|
(tx_chan_width == ATH9K_HT_MACMODE_20))
|
||||||
|
chanmode = CHANNEL_G_HT20;
|
||||||
if ((band_channel->center_freq == chan->center_freq) &&
|
if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
|
||||||
((band_channel->hw_value & mode) == mode))
|
(tx_chan_width == ATH9K_HT_MACMODE_2040))
|
||||||
return 1;
|
chanmode = CHANNEL_G_HT40PLUS;
|
||||||
|
if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
|
||||||
|
(tx_chan_width == ATH9K_HT_MACMODE_2040))
|
||||||
|
chanmode = CHANNEL_G_HT40MINUS;
|
||||||
|
break;
|
||||||
|
case IEEE80211_BAND_5GHZ:
|
||||||
|
if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
|
||||||
|
(tx_chan_width == ATH9K_HT_MACMODE_20))
|
||||||
|
chanmode = CHANNEL_A_HT20;
|
||||||
|
if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
|
||||||
|
(tx_chan_width == ATH9K_HT_MACMODE_2040))
|
||||||
|
chanmode = CHANNEL_A_HT40PLUS;
|
||||||
|
if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
|
||||||
|
(tx_chan_width == ATH9K_HT_MACMODE_2040))
|
||||||
|
chanmode = CHANNEL_A_HT40MINUS;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
return 0;
|
|
||||||
|
return chanmode;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static int ath_setkey_tkip(struct ath_softc *sc,
|
static int ath_setkey_tkip(struct ath_softc *sc,
|
||||||
struct ieee80211_key_conf *key,
|
struct ieee80211_key_conf *key,
|
||||||
struct hal_keyval *hk,
|
struct ath9k_keyval *hk,
|
||||||
const u8 *addr)
|
const u8 *addr)
|
||||||
{
|
{
|
||||||
u8 *key_rxmic = NULL;
|
u8 *key_rxmic = NULL;
|
||||||
@ -123,7 +139,7 @@ static int ath_key_config(struct ath_softc *sc,
|
|||||||
struct ieee80211_key_conf *key)
|
struct ieee80211_key_conf *key)
|
||||||
{
|
{
|
||||||
struct ieee80211_vif *vif;
|
struct ieee80211_vif *vif;
|
||||||
struct hal_keyval hk;
|
struct ath9k_keyval hk;
|
||||||
const u8 *mac = NULL;
|
const u8 *mac = NULL;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
enum ieee80211_if_types opmode;
|
enum ieee80211_if_types opmode;
|
||||||
@ -132,13 +148,13 @@ static int ath_key_config(struct ath_softc *sc,
|
|||||||
|
|
||||||
switch (key->alg) {
|
switch (key->alg) {
|
||||||
case ALG_WEP:
|
case ALG_WEP:
|
||||||
hk.kv_type = HAL_CIPHER_WEP;
|
hk.kv_type = ATH9K_CIPHER_WEP;
|
||||||
break;
|
break;
|
||||||
case ALG_TKIP:
|
case ALG_TKIP:
|
||||||
hk.kv_type = HAL_CIPHER_TKIP;
|
hk.kv_type = ATH9K_CIPHER_TKIP;
|
||||||
break;
|
break;
|
||||||
case ALG_CCMP:
|
case ALG_CCMP:
|
||||||
hk.kv_type = HAL_CIPHER_AES_CCM;
|
hk.kv_type = ATH9K_CIPHER_AES_CCM;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
@ -266,10 +282,11 @@ static void ath9k_rx_prepare(struct ath_softc *sc,
|
|||||||
rx_status->mactime = status->tsf;
|
rx_status->mactime = status->tsf;
|
||||||
rx_status->band = curchan->band;
|
rx_status->band = curchan->band;
|
||||||
rx_status->freq = curchan->center_freq;
|
rx_status->freq = curchan->center_freq;
|
||||||
rx_status->signal = (status->rssi * 64) / 100;
|
|
||||||
rx_status->noise = ATH_DEFAULT_NOISE_FLOOR;
|
rx_status->noise = ATH_DEFAULT_NOISE_FLOOR;
|
||||||
|
rx_status->signal = rx_status->noise + status->rssi;
|
||||||
rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
|
rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
|
||||||
rx_status->antenna = status->antenna;
|
rx_status->antenna = status->antenna;
|
||||||
|
rx_status->qual = status->rssi * 100 / 64;
|
||||||
|
|
||||||
if (status->flags & ATH_RX_MIC_ERROR)
|
if (status->flags & ATH_RX_MIC_ERROR)
|
||||||
rx_status->flag |= RX_FLAG_MMIC_ERROR;
|
rx_status->flag |= RX_FLAG_MMIC_ERROR;
|
||||||
@ -279,7 +296,7 @@ static void ath9k_rx_prepare(struct ath_softc *sc,
|
|||||||
rx_status->flag |= RX_FLAG_TSFT;
|
rx_status->flag |= RX_FLAG_TSFT;
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int8_t parse_mpdudensity(u_int8_t mpdudensity)
|
static u8 parse_mpdudensity(u8 mpdudensity)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
* 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
|
* 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
|
||||||
@ -318,19 +335,24 @@ static int ath9k_start(struct ieee80211_hw *hw)
|
|||||||
{
|
{
|
||||||
struct ath_softc *sc = hw->priv;
|
struct ath_softc *sc = hw->priv;
|
||||||
struct ieee80211_channel *curchan = hw->conf.channel;
|
struct ieee80211_channel *curchan = hw->conf.channel;
|
||||||
struct hal_channel hchan;
|
int error = 0, pos;
|
||||||
int error = 0;
|
|
||||||
|
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
|
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
|
||||||
"initial channel: %d MHz\n", __func__, curchan->center_freq);
|
"initial channel: %d MHz\n", __func__, curchan->center_freq);
|
||||||
|
|
||||||
/* setup initial channel */
|
/* setup initial channel */
|
||||||
|
|
||||||
hchan.channel = curchan->center_freq;
|
pos = ath_get_channel(sc, curchan);
|
||||||
hchan.channelFlags = ath_chan2flags(curchan, sc);
|
if (pos == -1) {
|
||||||
|
DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
sc->sc_ah->ah_channels[pos].chanmode =
|
||||||
|
(curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
|
||||||
|
|
||||||
/* open ath_dev */
|
/* open ath_dev */
|
||||||
error = ath_open(sc, &hchan);
|
error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
|
||||||
if (error) {
|
if (error) {
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: Unable to complete ath_open\n", __func__);
|
"%s: Unable to complete ath_open\n", __func__);
|
||||||
@ -399,10 +421,10 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
|
|||||||
|
|
||||||
switch (conf->type) {
|
switch (conf->type) {
|
||||||
case IEEE80211_IF_TYPE_STA:
|
case IEEE80211_IF_TYPE_STA:
|
||||||
ic_opmode = HAL_M_STA;
|
ic_opmode = ATH9K_M_STA;
|
||||||
break;
|
break;
|
||||||
case IEEE80211_IF_TYPE_IBSS:
|
case IEEE80211_IF_TYPE_IBSS:
|
||||||
ic_opmode = HAL_M_IBSS;
|
ic_opmode = ATH9K_M_IBSS;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
@ -447,17 +469,17 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Update ratectrl */
|
/* Update ratectrl */
|
||||||
ath_rate_newstate(sc, avp, 0);
|
ath_rate_newstate(sc, avp);
|
||||||
|
|
||||||
/* Reclaim beacon resources */
|
/* Reclaim beacon resources */
|
||||||
if (sc->sc_opmode == HAL_M_HOSTAP || sc->sc_opmode == HAL_M_IBSS) {
|
if (sc->sc_opmode == ATH9K_M_HOSTAP || sc->sc_opmode == ATH9K_M_IBSS) {
|
||||||
ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
|
ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
|
||||||
ath_beacon_return(sc, avp);
|
ath_beacon_return(sc, avp);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Set interrupt mask */
|
/* Set interrupt mask */
|
||||||
sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
|
sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
|
||||||
ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~HAL_INT_GLOBAL);
|
ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
|
||||||
sc->sc_beacons = 0;
|
sc->sc_beacons = 0;
|
||||||
|
|
||||||
error = ath_vap_detach(sc, 0);
|
error = ath_vap_detach(sc, 0);
|
||||||
@ -472,18 +494,24 @@ static int ath9k_config(struct ieee80211_hw *hw,
|
|||||||
{
|
{
|
||||||
struct ath_softc *sc = hw->priv;
|
struct ath_softc *sc = hw->priv;
|
||||||
struct ieee80211_channel *curchan = hw->conf.channel;
|
struct ieee80211_channel *curchan = hw->conf.channel;
|
||||||
struct hal_channel hchan;
|
int pos;
|
||||||
|
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
|
DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
|
||||||
__func__,
|
__func__,
|
||||||
curchan->center_freq);
|
curchan->center_freq);
|
||||||
|
|
||||||
hchan.channel = curchan->center_freq;
|
pos = ath_get_channel(sc, curchan);
|
||||||
hchan.channelFlags = ath_chan2flags(curchan, sc);
|
if (pos == -1) {
|
||||||
|
DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
sc->sc_ah->ah_channels[pos].chanmode =
|
||||||
|
(curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
|
||||||
sc->sc_config.txpowlimit = 2 * conf->power_level;
|
sc->sc_config.txpowlimit = 2 * conf->power_level;
|
||||||
|
|
||||||
/* set h/w channel */
|
/* set h/w channel */
|
||||||
if (ath_set_channel(sc, &hchan) < 0)
|
if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
|
||||||
DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
|
DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
|
||||||
__func__);
|
__func__);
|
||||||
|
|
||||||
@ -496,7 +524,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
|
|||||||
{
|
{
|
||||||
struct ath_softc *sc = hw->priv;
|
struct ath_softc *sc = hw->priv;
|
||||||
struct ath_vap *avp;
|
struct ath_vap *avp;
|
||||||
u_int32_t rfilt = 0;
|
u32 rfilt = 0;
|
||||||
int error, i;
|
int error, i;
|
||||||
DECLARE_MAC_BUF(mac);
|
DECLARE_MAC_BUF(mac);
|
||||||
|
|
||||||
@ -513,7 +541,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
|
|||||||
case IEEE80211_IF_TYPE_STA:
|
case IEEE80211_IF_TYPE_STA:
|
||||||
case IEEE80211_IF_TYPE_IBSS:
|
case IEEE80211_IF_TYPE_IBSS:
|
||||||
/* Update ratectrl about the new state */
|
/* Update ratectrl about the new state */
|
||||||
ath_rate_newstate(sc, avp, 0);
|
ath_rate_newstate(sc, avp);
|
||||||
|
|
||||||
/* Set rx filter */
|
/* Set rx filter */
|
||||||
rfilt = ath_calcrxfilter(sc);
|
rfilt = ath_calcrxfilter(sc);
|
||||||
@ -542,8 +570,8 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
|
|||||||
/* Disable BMISS interrupt when we're not associated */
|
/* Disable BMISS interrupt when we're not associated */
|
||||||
ath9k_hw_set_interrupts(sc->sc_ah,
|
ath9k_hw_set_interrupts(sc->sc_ah,
|
||||||
sc->sc_imask &
|
sc->sc_imask &
|
||||||
~(HAL_INT_SWBA | HAL_INT_BMISS));
|
~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
|
||||||
sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
|
sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
|
||||||
|
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG,
|
DPRINTF(sc, ATH_DBG_CONFIG,
|
||||||
"%s: RX filter 0x%x bssid %s aid 0x%x\n",
|
"%s: RX filter 0x%x bssid %s aid 0x%x\n",
|
||||||
@ -581,9 +609,9 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
|
|||||||
/* Check for WLAN_CAPABILITY_PRIVACY ? */
|
/* Check for WLAN_CAPABILITY_PRIVACY ? */
|
||||||
if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
|
if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
|
||||||
for (i = 0; i < IEEE80211_WEP_NKID; i++)
|
for (i = 0; i < IEEE80211_WEP_NKID; i++)
|
||||||
if (ath9k_hw_keyisvalid(sc->sc_ah, (u_int16_t)i))
|
if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
|
||||||
ath9k_hw_keysetmac(sc->sc_ah,
|
ath9k_hw_keysetmac(sc->sc_ah,
|
||||||
(u_int16_t)i,
|
(u16)i,
|
||||||
sc->sc_curbssid);
|
sc->sc_curbssid);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -672,7 +700,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
|
|||||||
const struct ieee80211_tx_queue_params *params)
|
const struct ieee80211_tx_queue_params *params)
|
||||||
{
|
{
|
||||||
struct ath_softc *sc = hw->priv;
|
struct ath_softc *sc = hw->priv;
|
||||||
struct hal_txq_info qi;
|
struct ath9k_txq_info qi;
|
||||||
int ret = 0, qnum;
|
int ret = 0, qnum;
|
||||||
|
|
||||||
if (queue >= WME_NUM_AC)
|
if (queue >= WME_NUM_AC)
|
||||||
@ -728,7 +756,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
|
|||||||
case DISABLE_KEY:
|
case DISABLE_KEY:
|
||||||
ath_key_delete(sc, key);
|
ath_key_delete(sc, key);
|
||||||
clear_bit(key->keyidx, sc->sc_keymap);
|
clear_bit(key->keyidx, sc->sc_keymap);
|
||||||
sc->sc_keytype = HAL_CIPHER_CLR;
|
sc->sc_keytype = ATH9K_CIPHER_CLR;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
ret = -EINVAL;
|
ret = -EINVAL;
|
||||||
@ -752,9 +780,9 @@ static void ath9k_ht_conf(struct ath_softc *sc,
|
|||||||
IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
|
IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
|
||||||
(bss_conf->ht_bss_conf->bss_cap &
|
(bss_conf->ht_bss_conf->bss_cap &
|
||||||
IEEE80211_HT_IE_CHA_WIDTH))
|
IEEE80211_HT_IE_CHA_WIDTH))
|
||||||
ht_info->tx_chan_width = HAL_HT_MACMODE_2040;
|
ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
|
||||||
else
|
else
|
||||||
ht_info->tx_chan_width = HAL_HT_MACMODE_20;
|
ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
|
||||||
|
|
||||||
ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
|
ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
|
||||||
ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
|
ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
|
||||||
@ -772,8 +800,8 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
|
|||||||
{
|
{
|
||||||
struct ieee80211_hw *hw = sc->hw;
|
struct ieee80211_hw *hw = sc->hw;
|
||||||
struct ieee80211_channel *curchan = hw->conf.channel;
|
struct ieee80211_channel *curchan = hw->conf.channel;
|
||||||
struct hal_channel hchan;
|
|
||||||
struct ath_vap *avp;
|
struct ath_vap *avp;
|
||||||
|
int pos;
|
||||||
DECLARE_MAC_BUF(mac);
|
DECLARE_MAC_BUF(mac);
|
||||||
|
|
||||||
if (bss_conf->assoc) {
|
if (bss_conf->assoc) {
|
||||||
@ -788,11 +816,8 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Update ratectrl about the new state */
|
|
||||||
ath_rate_newstate(sc, avp, 1);
|
|
||||||
|
|
||||||
/* New association, store aid */
|
/* New association, store aid */
|
||||||
if (avp->av_opmode == HAL_M_STA) {
|
if (avp->av_opmode == ATH9K_M_STA) {
|
||||||
sc->sc_curaid = bss_conf->aid;
|
sc->sc_curaid = bss_conf->aid;
|
||||||
ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
|
ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
|
||||||
sc->sc_curaid);
|
sc->sc_curaid);
|
||||||
@ -820,14 +845,30 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
|
|||||||
__func__,
|
__func__,
|
||||||
curchan->center_freq);
|
curchan->center_freq);
|
||||||
|
|
||||||
hchan.channel = curchan->center_freq;
|
pos = ath_get_channel(sc, curchan);
|
||||||
hchan.channelFlags = ath_chan2flags(curchan, sc);
|
if (pos == -1) {
|
||||||
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
|
"%s: Invalid channel\n", __func__);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (hw->conf.ht_conf.ht_supported)
|
||||||
|
sc->sc_ah->ah_channels[pos].chanmode =
|
||||||
|
ath_get_extchanmode(sc, curchan);
|
||||||
|
else
|
||||||
|
sc->sc_ah->ah_channels[pos].chanmode =
|
||||||
|
(curchan->band == IEEE80211_BAND_2GHZ) ?
|
||||||
|
CHANNEL_G : CHANNEL_A;
|
||||||
|
|
||||||
/* set h/w channel */
|
/* set h/w channel */
|
||||||
if (ath_set_channel(sc, &hchan) < 0)
|
if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: Unable to set channel\n",
|
"%s: Unable to set channel\n",
|
||||||
__func__);
|
__func__);
|
||||||
|
|
||||||
|
ath_rate_newstate(sc, avp);
|
||||||
|
/* Update ratectrl about the new state */
|
||||||
|
ath_rc_node_update(hw, avp->rc_node);
|
||||||
} else {
|
} else {
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG,
|
DPRINTF(sc, ATH_DBG_CONFIG,
|
||||||
"%s: Bss Info DISSOC\n", __func__);
|
"%s: Bss Info DISSOC\n", __func__);
|
||||||
@ -880,7 +921,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
|
|||||||
|
|
||||||
static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
|
static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
|
||||||
{
|
{
|
||||||
u_int64_t tsf;
|
u64 tsf;
|
||||||
struct ath_softc *sc = hw->priv;
|
struct ath_softc *sc = hw->priv;
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
|
|
||||||
@ -974,143 +1015,6 @@ static struct ieee80211_ops ath9k_ops = {
|
|||||||
.ampdu_action = ath9k_ampdu_action
|
.ampdu_action = ath9k_ampdu_action
|
||||||
};
|
};
|
||||||
|
|
||||||
u_int32_t ath_chan2flags(struct ieee80211_channel *chan,
|
|
||||||
struct ath_softc *sc)
|
|
||||||
{
|
|
||||||
struct ieee80211_hw *hw = sc->hw;
|
|
||||||
struct ath_ht_info *ht_info = &sc->sc_ht_info;
|
|
||||||
|
|
||||||
if (sc->sc_scanning) {
|
|
||||||
if (chan->band == IEEE80211_BAND_5GHZ) {
|
|
||||||
if (ath_check_chanflags(chan, CHANNEL_A_HT20, sc))
|
|
||||||
return CHANNEL_A_HT20;
|
|
||||||
else
|
|
||||||
return CHANNEL_A;
|
|
||||||
} else {
|
|
||||||
if (ath_check_chanflags(chan, CHANNEL_G_HT20, sc))
|
|
||||||
return CHANNEL_G_HT20;
|
|
||||||
else if (ath_check_chanflags(chan, CHANNEL_G, sc))
|
|
||||||
return CHANNEL_G;
|
|
||||||
else
|
|
||||||
return CHANNEL_B;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
if (chan->band == IEEE80211_BAND_2GHZ) {
|
|
||||||
if (!hw->conf.ht_conf.ht_supported) {
|
|
||||||
if (ath_check_chanflags(chan, CHANNEL_G, sc))
|
|
||||||
return CHANNEL_G;
|
|
||||||
else
|
|
||||||
return CHANNEL_B;
|
|
||||||
}
|
|
||||||
if ((ht_info->ext_chan_offset ==
|
|
||||||
IEEE80211_HT_IE_CHA_SEC_NONE) &&
|
|
||||||
(ht_info->tx_chan_width == HAL_HT_MACMODE_20))
|
|
||||||
return CHANNEL_G_HT20;
|
|
||||||
if ((ht_info->ext_chan_offset ==
|
|
||||||
IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
|
|
||||||
(ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
|
|
||||||
return CHANNEL_G_HT40PLUS;
|
|
||||||
if ((ht_info->ext_chan_offset ==
|
|
||||||
IEEE80211_HT_IE_CHA_SEC_BELOW) &&
|
|
||||||
(ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
|
|
||||||
return CHANNEL_G_HT40MINUS;
|
|
||||||
return CHANNEL_B;
|
|
||||||
} else {
|
|
||||||
if (!hw->conf.ht_conf.ht_supported)
|
|
||||||
return CHANNEL_A;
|
|
||||||
if ((ht_info->ext_chan_offset ==
|
|
||||||
IEEE80211_HT_IE_CHA_SEC_NONE) &&
|
|
||||||
(ht_info->tx_chan_width == HAL_HT_MACMODE_20))
|
|
||||||
return CHANNEL_A_HT20;
|
|
||||||
if ((ht_info->ext_chan_offset ==
|
|
||||||
IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
|
|
||||||
(ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
|
|
||||||
return CHANNEL_A_HT40PLUS;
|
|
||||||
if ((ht_info->ext_chan_offset ==
|
|
||||||
IEEE80211_HT_IE_CHA_SEC_BELOW) &&
|
|
||||||
(ht_info->tx_chan_width == HAL_HT_MACMODE_2040))
|
|
||||||
return CHANNEL_A_HT40MINUS;
|
|
||||||
return CHANNEL_A;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void ath_setup_channel_list(struct ath_softc *sc,
|
|
||||||
enum ieee80211_clist_cmd cmd,
|
|
||||||
const struct hal_channel *chans,
|
|
||||||
int nchan,
|
|
||||||
const u_int8_t *regclassids,
|
|
||||||
u_int nregclass,
|
|
||||||
int countrycode)
|
|
||||||
{
|
|
||||||
const struct hal_channel *c;
|
|
||||||
int i, a = 0, b = 0, flags;
|
|
||||||
|
|
||||||
if (countrycode == CTRY_DEFAULT) {
|
|
||||||
for (i = 0; i < nchan; i++) {
|
|
||||||
c = &chans[i];
|
|
||||||
flags = 0;
|
|
||||||
/* XXX: Ah! make more readable, and
|
|
||||||
* idententation friendly */
|
|
||||||
if (IS_CHAN_2GHZ(c) &&
|
|
||||||
!test_update_chan(IEEE80211_BAND_2GHZ, c, sc)) {
|
|
||||||
sc->channels[IEEE80211_BAND_2GHZ][a].band =
|
|
||||||
IEEE80211_BAND_2GHZ;
|
|
||||||
sc->channels[IEEE80211_BAND_2GHZ][a].
|
|
||||||
center_freq =
|
|
||||||
c->channel;
|
|
||||||
sc->channels[IEEE80211_BAND_2GHZ][a].max_power =
|
|
||||||
c->maxTxPower;
|
|
||||||
sc->channels[IEEE80211_BAND_2GHZ][a].hw_value =
|
|
||||||
c->channelFlags;
|
|
||||||
|
|
||||||
if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
|
|
||||||
flags |= IEEE80211_CHAN_NO_IBSS;
|
|
||||||
if (IS_CHAN_PASSIVE(c))
|
|
||||||
flags |= IEEE80211_CHAN_PASSIVE_SCAN;
|
|
||||||
|
|
||||||
sc->channels[IEEE80211_BAND_2GHZ][a].flags =
|
|
||||||
flags;
|
|
||||||
sc->sbands[IEEE80211_BAND_2GHZ].n_channels++;
|
|
||||||
a++;
|
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG,
|
|
||||||
"%s: 2MHz channel: %d, "
|
|
||||||
"channelFlags: 0x%x\n",
|
|
||||||
__func__,
|
|
||||||
c->channel,
|
|
||||||
c->channelFlags);
|
|
||||||
} else if (IS_CHAN_5GHZ(c) &&
|
|
||||||
!test_update_chan(IEEE80211_BAND_5GHZ, c, sc)) {
|
|
||||||
sc->channels[IEEE80211_BAND_5GHZ][b].band =
|
|
||||||
IEEE80211_BAND_5GHZ;
|
|
||||||
sc->channels[IEEE80211_BAND_5GHZ][b].
|
|
||||||
center_freq =
|
|
||||||
c->channel;
|
|
||||||
sc->channels[IEEE80211_BAND_5GHZ][b].max_power =
|
|
||||||
c->maxTxPower;
|
|
||||||
sc->channels[IEEE80211_BAND_5GHZ][b].hw_value =
|
|
||||||
c->channelFlags;
|
|
||||||
|
|
||||||
if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
|
|
||||||
flags |= IEEE80211_CHAN_NO_IBSS;
|
|
||||||
if (IS_CHAN_PASSIVE(c))
|
|
||||||
flags |= IEEE80211_CHAN_PASSIVE_SCAN;
|
|
||||||
|
|
||||||
sc->channels[IEEE80211_BAND_5GHZ][b].
|
|
||||||
flags = flags;
|
|
||||||
sc->sbands[IEEE80211_BAND_5GHZ].n_channels++;
|
|
||||||
b++;
|
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG,
|
|
||||||
"%s: 5MHz channel: %d, "
|
|
||||||
"channelFlags: 0x%x\n",
|
|
||||||
__func__,
|
|
||||||
c->channel,
|
|
||||||
c->channelFlags);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void ath_get_beaconconfig(struct ath_softc *sc,
|
void ath_get_beaconconfig(struct ath_softc *sc,
|
||||||
int if_id,
|
int if_id,
|
||||||
struct ath_beacon_config *conf)
|
struct ath_beacon_config *conf)
|
||||||
@ -1168,7 +1072,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
|
|||||||
int ath__rx_indicate(struct ath_softc *sc,
|
int ath__rx_indicate(struct ath_softc *sc,
|
||||||
struct sk_buff *skb,
|
struct sk_buff *skb,
|
||||||
struct ath_recv_status *status,
|
struct ath_recv_status *status,
|
||||||
u_int16_t keyix)
|
u16 keyix)
|
||||||
{
|
{
|
||||||
struct ieee80211_hw *hw = sc->hw;
|
struct ieee80211_hw *hw = sc->hw;
|
||||||
struct ath_node *an = NULL;
|
struct ath_node *an = NULL;
|
||||||
@ -1191,7 +1095,7 @@ int ath__rx_indicate(struct ath_softc *sc,
|
|||||||
/* Prepare rx status */
|
/* Prepare rx status */
|
||||||
ath9k_rx_prepare(sc, skb, status, &rx_status);
|
ath9k_rx_prepare(sc, skb, status, &rx_status);
|
||||||
|
|
||||||
if (!(keyix == HAL_RXKEYIX_INVALID) &&
|
if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
|
||||||
!(status->flags & ATH_RX_DECRYPT_ERROR)) {
|
!(status->flags & ATH_RX_DECRYPT_ERROR)) {
|
||||||
rx_status.flag |= RX_FLAG_DECRYPTED;
|
rx_status.flag |= RX_FLAG_DECRYPTED;
|
||||||
} else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
|
} else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
|
||||||
@ -1236,7 +1140,7 @@ int ath_rx_subframe(struct ath_node *an,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
|
enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
return sc->sc_ht_info.tx_chan_width;
|
return sc->sc_ht_info.tx_chan_width;
|
||||||
}
|
}
|
||||||
@ -1244,7 +1148,7 @@ enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
|
|||||||
void ath_setup_rate(struct ath_softc *sc,
|
void ath_setup_rate(struct ath_softc *sc,
|
||||||
enum wireless_mode wMode,
|
enum wireless_mode wMode,
|
||||||
enum RATE_TYPE type,
|
enum RATE_TYPE type,
|
||||||
const struct hal_rate_table *rt)
|
const struct ath9k_rate_table *rt)
|
||||||
{
|
{
|
||||||
int i, maxrates, a = 0, b = 0;
|
int i, maxrates, a = 0, b = 0;
|
||||||
struct ieee80211_supported_band *band_2ghz;
|
struct ieee80211_supported_band *band_2ghz;
|
||||||
@ -1335,7 +1239,7 @@ static int ath_detach(struct ath_softc *sc)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ath_attach(u_int16_t devid,
|
static int ath_attach(u16 devid,
|
||||||
struct ath_softc *sc)
|
struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ieee80211_hw *hw = sc->hw;
|
struct ieee80211_hw *hw = sc->hw;
|
||||||
@ -1432,7 +1336,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||||||
struct ath_softc *sc;
|
struct ath_softc *sc;
|
||||||
struct ieee80211_hw *hw;
|
struct ieee80211_hw *hw;
|
||||||
const char *athname;
|
const char *athname;
|
||||||
u_int8_t csz;
|
u8 csz;
|
||||||
u32 val;
|
u32 val;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
@ -1459,7 +1363,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||||||
* DMA to work so force a reasonable value here if it
|
* DMA to work so force a reasonable value here if it
|
||||||
* comes up zero.
|
* comes up zero.
|
||||||
*/
|
*/
|
||||||
csz = L1_CACHE_BYTES / sizeof(u_int32_t);
|
csz = L1_CACHE_BYTES / sizeof(u32);
|
||||||
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
|
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
@ -1499,6 +1403,9 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||||||
goto bad2;
|
goto bad2;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
hw->flags = IEEE80211_HW_SIGNAL_DBM |
|
||||||
|
IEEE80211_HW_NOISE_DBM;
|
||||||
|
|
||||||
SET_IEEE80211_DEV(hw, &pdev->dev);
|
SET_IEEE80211_DEV(hw, &pdev->dev);
|
||||||
pci_set_drvdata(pdev, hw);
|
pci_set_drvdata(pdev, hw);
|
||||||
|
|
||||||
|
@ -20,7 +20,7 @@
|
|||||||
#include "phy.h"
|
#include "phy.h"
|
||||||
|
|
||||||
void
|
void
|
||||||
ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
|
ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex,
|
||||||
int regWrites)
|
int regWrites)
|
||||||
{
|
{
|
||||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||||
@ -29,20 +29,20 @@ ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
|
|||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
|
ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
u_int32_t channelSel = 0;
|
u32 channelSel = 0;
|
||||||
u_int32_t bModeSynth = 0;
|
u32 bModeSynth = 0;
|
||||||
u_int32_t aModeRefSel = 0;
|
u32 aModeRefSel = 0;
|
||||||
u_int32_t reg32 = 0;
|
u32 reg32 = 0;
|
||||||
u_int16_t freq;
|
u16 freq;
|
||||||
struct chan_centers centers;
|
struct chan_centers centers;
|
||||||
|
|
||||||
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
|
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
|
||||||
freq = centers.synth_center;
|
freq = centers.synth_center;
|
||||||
|
|
||||||
if (freq < 4800) {
|
if (freq < 4800) {
|
||||||
u_int32_t txctl;
|
u32 txctl;
|
||||||
|
|
||||||
if (((freq - 2192) % 5) == 0) {
|
if (((freq - 2192) % 5) == 0) {
|
||||||
channelSel = ((freq - 672) * 2 - 3040) / 10;
|
channelSel = ((freq - 672) * 2 - 3040) / 10;
|
||||||
@ -105,12 +105,12 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
|
|||||||
|
|
||||||
bool
|
bool
|
||||||
ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
||||||
struct hal_channel_internal *chan)
|
struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
u_int16_t bMode, fracMode, aModeRefSel = 0;
|
u16 bMode, fracMode, aModeRefSel = 0;
|
||||||
u_int32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
|
u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
|
||||||
struct chan_centers centers;
|
struct chan_centers centers;
|
||||||
u_int32_t refDivA = 24;
|
u32 refDivA = 24;
|
||||||
|
|
||||||
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
|
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
|
||||||
freq = centers.synth_center;
|
freq = centers.synth_center;
|
||||||
@ -119,7 +119,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
|||||||
reg32 &= 0xc0000000;
|
reg32 &= 0xc0000000;
|
||||||
|
|
||||||
if (freq < 4800) {
|
if (freq < 4800) {
|
||||||
u_int32_t txctl;
|
u32 txctl;
|
||||||
|
|
||||||
bMode = 1;
|
bMode = 1;
|
||||||
fracMode = 1;
|
fracMode = 1;
|
||||||
@ -175,11 +175,11 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
|||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
|
ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
|
||||||
u_int32_t numBits, u_int32_t firstBit,
|
u32 numBits, u32 firstBit,
|
||||||
u_int32_t column)
|
u32 column)
|
||||||
{
|
{
|
||||||
u_int32_t tmp32, mask, arrayEntry, lastBit;
|
u32 tmp32, mask, arrayEntry, lastBit;
|
||||||
int32_t bitPosition, bitsLeft;
|
int32_t bitPosition, bitsLeft;
|
||||||
|
|
||||||
tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
|
tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
|
||||||
@ -202,14 +202,14 @@ ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
|
|||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
|
ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
|
||||||
u_int16_t modesIndex)
|
u16 modesIndex)
|
||||||
{
|
{
|
||||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||||
|
|
||||||
u_int32_t eepMinorRev;
|
u32 eepMinorRev;
|
||||||
u_int32_t ob5GHz = 0, db5GHz = 0;
|
u32 ob5GHz = 0, db5GHz = 0;
|
||||||
u_int32_t ob2GHz = 0, db2GHz = 0;
|
u32 ob2GHz = 0, db2GHz = 0;
|
||||||
int regWrites = 0;
|
int regWrites = 0;
|
||||||
|
|
||||||
if (AR_SREV_9280_10_OR_LATER(ah))
|
if (AR_SREV_9280_10_OR_LATER(ah))
|
||||||
@ -312,47 +312,32 @@ ath9k_hw_rfdetach(struct ath_hal *ah)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
|
||||||
ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
|
|
||||||
struct hal_channel *chans, u_int32_t nchans)
|
|
||||||
{
|
|
||||||
bool retVal = true;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < nchans; i++) {
|
|
||||||
chans[i].maxTxPower = AR5416_MAX_RATE_POWER;
|
|
||||||
chans[i].minTxPower = AR5416_MAX_RATE_POWER;
|
|
||||||
}
|
|
||||||
return retVal;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
|
|
||||||
{
|
{
|
||||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||||
|
|
||||||
if (!AR_SREV_9280_10_OR_LATER(ah)) {
|
if (!AR_SREV_9280_10_OR_LATER(ah)) {
|
||||||
|
|
||||||
ahp->ah_analogBank0Data =
|
ahp->ah_analogBank0Data =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank0.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank0.ia_rows), GFP_KERNEL);
|
||||||
ahp->ah_analogBank1Data =
|
ahp->ah_analogBank1Data =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank1.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank1.ia_rows), GFP_KERNEL);
|
||||||
ahp->ah_analogBank2Data =
|
ahp->ah_analogBank2Data =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank2.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank2.ia_rows), GFP_KERNEL);
|
||||||
ahp->ah_analogBank3Data =
|
ahp->ah_analogBank3Data =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank3.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank3.ia_rows), GFP_KERNEL);
|
||||||
ahp->ah_analogBank6Data =
|
ahp->ah_analogBank6Data =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
|
||||||
ahp->ah_analogBank6TPCData =
|
ahp->ah_analogBank6TPCData =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
|
||||||
ahp->ah_analogBank7Data =
|
ahp->ah_analogBank7Data =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank7.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank7.ia_rows), GFP_KERNEL);
|
||||||
|
|
||||||
if (ahp->ah_analogBank0Data == NULL
|
if (ahp->ah_analogBank0Data == NULL
|
||||||
@ -365,30 +350,30 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
|
|||||||
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
||||||
"%s: cannot allocate RF banks\n",
|
"%s: cannot allocate RF banks\n",
|
||||||
__func__);
|
__func__);
|
||||||
*status = HAL_ENOMEM;
|
*status = -ENOMEM;
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
ahp->ah_addac5416_21 =
|
ahp->ah_addac5416_21 =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniAddac.ia_rows *
|
ahp->ah_iniAddac.ia_rows *
|
||||||
ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
|
ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
|
||||||
if (ahp->ah_addac5416_21 == NULL) {
|
if (ahp->ah_addac5416_21 == NULL) {
|
||||||
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
||||||
"%s: cannot allocate ah_addac5416_21\n",
|
"%s: cannot allocate ah_addac5416_21\n",
|
||||||
__func__);
|
__func__);
|
||||||
*status = HAL_ENOMEM;
|
*status = -ENOMEM;
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
ahp->ah_bank6Temp =
|
ahp->ah_bank6Temp =
|
||||||
kzalloc((sizeof(u_int32_t) *
|
kzalloc((sizeof(u32) *
|
||||||
ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
|
ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
|
||||||
if (ahp->ah_bank6Temp == NULL) {
|
if (ahp->ah_bank6Temp == NULL) {
|
||||||
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
||||||
"%s: cannot allocate ah_bank6Temp\n",
|
"%s: cannot allocate ah_bank6Temp\n",
|
||||||
__func__);
|
__func__);
|
||||||
*status = HAL_ENOMEM;
|
*status = -ENOMEM;
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -397,27 +382,27 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
|
|||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct hal_channel *chan)
|
ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
int i, regWrites = 0;
|
int i, regWrites = 0;
|
||||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||||
u_int32_t bank6SelMask;
|
u32 bank6SelMask;
|
||||||
u_int32_t *bank6Temp = ahp->ah_bank6Temp;
|
u32 *bank6Temp = ahp->ah_bank6Temp;
|
||||||
|
|
||||||
switch (ahp->ah_diversityControl) {
|
switch (ahp->ah_diversityControl) {
|
||||||
case HAL_ANT_FIXED_A:
|
case ATH9K_ANT_FIXED_A:
|
||||||
bank6SelMask =
|
bank6SelMask =
|
||||||
(ahp->
|
(ahp->
|
||||||
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
|
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
|
||||||
REDUCE_CHAIN_1;
|
REDUCE_CHAIN_1;
|
||||||
break;
|
break;
|
||||||
case HAL_ANT_FIXED_B:
|
case ATH9K_ANT_FIXED_B:
|
||||||
bank6SelMask =
|
bank6SelMask =
|
||||||
(ahp->
|
(ahp->
|
||||||
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
|
ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
|
||||||
REDUCE_CHAIN_0;
|
REDUCE_CHAIN_0;
|
||||||
break;
|
break;
|
||||||
case HAL_ANT_VARIABLE:
|
case ATH9K_ANT_VARIABLE:
|
||||||
return;
|
return;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
@ -18,19 +18,19 @@
|
|||||||
#define PHY_H
|
#define PHY_H
|
||||||
|
|
||||||
bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
|
||||||
struct hal_channel_internal
|
struct ath9k_channel
|
||||||
*chan);
|
*chan);
|
||||||
bool ath9k_hw_set_channel(struct ath_hal *ah,
|
bool ath9k_hw_set_channel(struct ath_hal *ah,
|
||||||
struct hal_channel_internal *chan);
|
struct ath9k_channel *chan);
|
||||||
void ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex,
|
void ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex,
|
||||||
u_int freqIndex, int regWrites);
|
u32 freqIndex, int regWrites);
|
||||||
bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
|
bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
|
||||||
struct hal_channel_internal *chan,
|
struct ath9k_channel *chan,
|
||||||
u_int16_t modesIndex);
|
u16 modesIndex);
|
||||||
void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
|
void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
|
||||||
struct hal_channel *chan);
|
struct ath9k_channel *chan);
|
||||||
bool ath9k_hw_init_rf(struct ath_hal *ah,
|
bool ath9k_hw_init_rf(struct ath_hal *ah,
|
||||||
enum hal_status *status);
|
int *status);
|
||||||
|
|
||||||
#define AR_PHY_BASE 0x9800
|
#define AR_PHY_BASE 0x9800
|
||||||
#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
|
#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
|
||||||
|
@ -22,7 +22,7 @@
|
|||||||
#include "core.h"
|
#include "core.h"
|
||||||
#include "../net/mac80211/rate.h"
|
#include "../net/mac80211/rate.h"
|
||||||
|
|
||||||
static u_int32_t tx_triglevel_max;
|
static u32 tx_triglevel_max;
|
||||||
|
|
||||||
static struct ath_rate_table ar5416_11na_ratetable = {
|
static struct ath_rate_table ar5416_11na_ratetable = {
|
||||||
42,
|
42,
|
||||||
@ -159,12 +159,12 @@ static struct ath_rate_table ar5416_11na_ratetable = {
|
|||||||
WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
|
WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TRUE_ALL - valid for 20/40/Legacy,
|
/* TRUE_ALL - valid for 20/40/Legacy,
|
||||||
* TRUE - Legacy only,
|
* TRUE - Legacy only,
|
||||||
* TRUE_20 - HT 20 only,
|
* TRUE_20 - HT 20 only,
|
||||||
* TRUE_40 - HT 40 only */
|
* TRUE_40 - HT 40 only */
|
||||||
|
|
||||||
/* 4ms frame limit not used for NG mode. The values filled
|
/* 4ms frame limit not used for NG mode. The values filled
|
||||||
* for HT are the 64K max aggregate limit */
|
* for HT are the 64K max aggregate limit */
|
||||||
|
|
||||||
static struct ath_rate_table ar5416_11ng_ratetable = {
|
static struct ath_rate_table ar5416_11ng_ratetable = {
|
||||||
@ -543,17 +543,15 @@ static inline int8_t median(int8_t a, int8_t b, int8_t c)
|
|||||||
static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
|
static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
|
||||||
struct ath_tx_ratectrl *rate_ctrl)
|
struct ath_tx_ratectrl *rate_ctrl)
|
||||||
{
|
{
|
||||||
u_int8_t i, j, idx, idx_next;
|
u8 i, j, idx, idx_next;
|
||||||
|
|
||||||
for (i = rate_ctrl->max_valid_rate - 1; i > 0; i--) {
|
for (i = rate_ctrl->max_valid_rate - 1; i > 0; i--) {
|
||||||
for (j = 0; j <= i-1; j++) {
|
for (j = 0; j <= i-1; j++) {
|
||||||
|
|
||||||
idx = rate_ctrl->valid_rate_index[j];
|
idx = rate_ctrl->valid_rate_index[j];
|
||||||
idx_next = rate_ctrl->valid_rate_index[j+1];
|
idx_next = rate_ctrl->valid_rate_index[j+1];
|
||||||
|
|
||||||
if (rate_table->info[idx].ratekbps >
|
if (rate_table->info[idx].ratekbps >
|
||||||
rate_table->info[idx_next].ratekbps) {
|
rate_table->info[idx_next].ratekbps) {
|
||||||
|
|
||||||
rate_ctrl->valid_rate_index[j] = idx_next;
|
rate_ctrl->valid_rate_index[j] = idx_next;
|
||||||
rate_ctrl->valid_rate_index[j+1] = idx;
|
rate_ctrl->valid_rate_index[j+1] = idx;
|
||||||
}
|
}
|
||||||
@ -565,34 +563,34 @@ static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
|
|||||||
|
|
||||||
static void ath_rc_init_valid_txmask(struct ath_tx_ratectrl *rate_ctrl)
|
static void ath_rc_init_valid_txmask(struct ath_tx_ratectrl *rate_ctrl)
|
||||||
{
|
{
|
||||||
u_int8_t i;
|
u8 i;
|
||||||
|
|
||||||
for (i = 0; i < rate_ctrl->rate_table_size; i++)
|
for (i = 0; i < rate_ctrl->rate_table_size; i++)
|
||||||
rate_ctrl->valid_rate_index[i] = FALSE;
|
rate_ctrl->valid_rate_index[i] = FALSE;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ath_rc_set_valid_txmask(struct ath_tx_ratectrl *rate_ctrl,
|
static inline void ath_rc_set_valid_txmask(struct ath_tx_ratectrl *rate_ctrl,
|
||||||
u_int8_t index, int valid_tx_rate)
|
u8 index, int valid_tx_rate)
|
||||||
{
|
{
|
||||||
ASSERT(index <= rate_ctrl->rate_table_size);
|
ASSERT(index <= rate_ctrl->rate_table_size);
|
||||||
rate_ctrl->valid_rate_index[index] = valid_tx_rate ? TRUE : FALSE;
|
rate_ctrl->valid_rate_index[index] = valid_tx_rate ? TRUE : FALSE;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline int ath_rc_isvalid_txmask(struct ath_tx_ratectrl *rate_ctrl,
|
static inline int ath_rc_isvalid_txmask(struct ath_tx_ratectrl *rate_ctrl,
|
||||||
u_int8_t index)
|
u8 index)
|
||||||
{
|
{
|
||||||
ASSERT(index <= rate_ctrl->rate_table_size);
|
ASSERT(index <= rate_ctrl->rate_table_size);
|
||||||
return rate_ctrl->valid_rate_index[index];
|
return rate_ctrl->valid_rate_index[index];
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Iterators for valid_txrate_mask */
|
/* Iterators for valid_txrate_mask */
|
||||||
static inline int ath_rc_get_nextvalid_txrate(
|
static inline int
|
||||||
const struct ath_rate_table *rate_table,
|
ath_rc_get_nextvalid_txrate(const struct ath_rate_table *rate_table,
|
||||||
struct ath_tx_ratectrl *rate_ctrl,
|
struct ath_tx_ratectrl *rate_ctrl,
|
||||||
u_int8_t cur_valid_txrate,
|
u8 cur_valid_txrate,
|
||||||
u_int8_t *next_idx)
|
u8 *next_idx)
|
||||||
{
|
{
|
||||||
u_int8_t i;
|
u8 i;
|
||||||
|
|
||||||
for (i = 0; i < rate_ctrl->max_valid_rate - 1; i++) {
|
for (i = 0; i < rate_ctrl->max_valid_rate - 1; i++) {
|
||||||
if (rate_ctrl->valid_rate_index[i] == cur_valid_txrate) {
|
if (rate_ctrl->valid_rate_index[i] == cur_valid_txrate) {
|
||||||
@ -608,7 +606,7 @@ static inline int ath_rc_get_nextvalid_txrate(
|
|||||||
|
|
||||||
/* Return true only for single stream */
|
/* Return true only for single stream */
|
||||||
|
|
||||||
static int ath_rc_valid_phyrate(u_int32_t phy, u_int32_t capflag, int ignore_cw)
|
static int ath_rc_valid_phyrate(u32 phy, u32 capflag, int ignore_cw)
|
||||||
{
|
{
|
||||||
if (WLAN_RC_PHY_HT(phy) & !(capflag & WLAN_RC_HT_FLAG))
|
if (WLAN_RC_PHY_HT(phy) & !(capflag & WLAN_RC_HT_FLAG))
|
||||||
return FALSE;
|
return FALSE;
|
||||||
@ -624,10 +622,10 @@ static int ath_rc_valid_phyrate(u_int32_t phy, u_int32_t capflag, int ignore_cw)
|
|||||||
return TRUE;
|
return TRUE;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline int ath_rc_get_nextlowervalid_txrate(
|
static inline int
|
||||||
const struct ath_rate_table *rate_table,
|
ath_rc_get_nextlowervalid_txrate(const struct ath_rate_table *rate_table,
|
||||||
struct ath_tx_ratectrl *rate_ctrl,
|
struct ath_tx_ratectrl *rate_ctrl,
|
||||||
u_int8_t cur_valid_txrate, u_int8_t *next_idx)
|
u8 cur_valid_txrate, u8 *next_idx)
|
||||||
{
|
{
|
||||||
int8_t i;
|
int8_t i;
|
||||||
|
|
||||||
@ -643,13 +641,14 @@ static inline int ath_rc_get_nextlowervalid_txrate(
|
|||||||
/*
|
/*
|
||||||
* Initialize the Valid Rate Index from valid entries in Rate Table
|
* Initialize the Valid Rate Index from valid entries in Rate Table
|
||||||
*/
|
*/
|
||||||
static u_int8_t ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
|
static u8
|
||||||
|
ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
|
||||||
const struct ath_rate_table *rate_table,
|
const struct ath_rate_table *rate_table,
|
||||||
u_int32_t capflag)
|
u32 capflag)
|
||||||
{
|
{
|
||||||
struct ath_tx_ratectrl *rate_ctrl;
|
struct ath_tx_ratectrl *rate_ctrl;
|
||||||
u_int8_t i, hi = 0;
|
u8 i, hi = 0;
|
||||||
u_int32_t valid;
|
u32 valid;
|
||||||
|
|
||||||
rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv);
|
rate_ctrl = (struct ath_tx_ratectrl *)(ath_rc_priv);
|
||||||
for (i = 0; i < rate_table->rate_cnt; i++) {
|
for (i = 0; i < rate_table->rate_cnt; i++) {
|
||||||
@ -657,8 +656,8 @@ static u_int8_t ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
|
|||||||
rate_table->info[i].valid_single_stream :
|
rate_table->info[i].valid_single_stream :
|
||||||
rate_table->info[i].valid);
|
rate_table->info[i].valid);
|
||||||
if (valid == TRUE) {
|
if (valid == TRUE) {
|
||||||
u_int32_t phy = rate_table->info[i].phy;
|
u32 phy = rate_table->info[i].phy;
|
||||||
u_int8_t valid_rate_count = 0;
|
u8 valid_rate_count = 0;
|
||||||
|
|
||||||
if (!ath_rc_valid_phyrate(phy, capflag, FALSE))
|
if (!ath_rc_valid_phyrate(phy, capflag, FALSE))
|
||||||
continue;
|
continue;
|
||||||
@ -677,21 +676,22 @@ static u_int8_t ath_rc_sib_init_validrates(struct ath_rate_node *ath_rc_priv,
|
|||||||
/*
|
/*
|
||||||
* Initialize the Valid Rate Index from Rate Set
|
* Initialize the Valid Rate Index from Rate Set
|
||||||
*/
|
*/
|
||||||
static u_int8_t ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
|
static u8
|
||||||
|
ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
|
||||||
const struct ath_rate_table *rate_table,
|
const struct ath_rate_table *rate_table,
|
||||||
struct ath_rateset *rateset,
|
struct ath_rateset *rateset,
|
||||||
u_int32_t capflag)
|
u32 capflag)
|
||||||
{
|
{
|
||||||
/* XXX: Clean me up and make identation friendly */
|
/* XXX: Clean me up and make identation friendly */
|
||||||
u_int8_t i, j, hi = 0;
|
u8 i, j, hi = 0;
|
||||||
struct ath_tx_ratectrl *rate_ctrl =
|
struct ath_tx_ratectrl *rate_ctrl =
|
||||||
(struct ath_tx_ratectrl *)(ath_rc_priv);
|
(struct ath_tx_ratectrl *)(ath_rc_priv);
|
||||||
|
|
||||||
/* Use intersection of working rates and valid rates */
|
/* Use intersection of working rates and valid rates */
|
||||||
for (i = 0; i < rateset->rs_nrates; i++) {
|
for (i = 0; i < rateset->rs_nrates; i++) {
|
||||||
for (j = 0; j < rate_table->rate_cnt; j++) {
|
for (j = 0; j < rate_table->rate_cnt; j++) {
|
||||||
u_int32_t phy = rate_table->info[j].phy;
|
u32 phy = rate_table->info[j].phy;
|
||||||
u_int32_t valid = (ath_rc_priv->single_stream ?
|
u32 valid = (ath_rc_priv->single_stream ?
|
||||||
rate_table->info[j].valid_single_stream :
|
rate_table->info[j].valid_single_stream :
|
||||||
rate_table->info[j].valid);
|
rate_table->info[j].valid);
|
||||||
|
|
||||||
@ -707,7 +707,7 @@ static u_int8_t ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
|
|||||||
WLAN_RC_CAP_MODE(capflag)) &&
|
WLAN_RC_CAP_MODE(capflag)) &&
|
||||||
!WLAN_RC_PHY_HT(phy)) {
|
!WLAN_RC_PHY_HT(phy)) {
|
||||||
|
|
||||||
u_int8_t valid_rate_count = 0;
|
u8 valid_rate_count = 0;
|
||||||
|
|
||||||
if (!ath_rc_valid_phyrate(phy, capflag, FALSE))
|
if (!ath_rc_valid_phyrate(phy, capflag, FALSE))
|
||||||
continue;
|
continue;
|
||||||
@ -726,19 +726,20 @@ static u_int8_t ath_rc_sib_setvalid_rates(struct ath_rate_node *ath_rc_priv,
|
|||||||
return hi;
|
return hi;
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int8_t ath_rc_sib_setvalid_htrates(struct ath_rate_node *ath_rc_priv,
|
static u8
|
||||||
|
ath_rc_sib_setvalid_htrates(struct ath_rate_node *ath_rc_priv,
|
||||||
const struct ath_rate_table *rate_table,
|
const struct ath_rate_table *rate_table,
|
||||||
u_int8_t *mcs_set, u_int32_t capflag)
|
u8 *mcs_set, u32 capflag)
|
||||||
{
|
{
|
||||||
u_int8_t i, j, hi = 0;
|
u8 i, j, hi = 0;
|
||||||
struct ath_tx_ratectrl *rate_ctrl =
|
struct ath_tx_ratectrl *rate_ctrl =
|
||||||
(struct ath_tx_ratectrl *)(ath_rc_priv);
|
(struct ath_tx_ratectrl *)(ath_rc_priv);
|
||||||
|
|
||||||
/* Use intersection of working rates and valid rates */
|
/* Use intersection of working rates and valid rates */
|
||||||
for (i = 0; i < ((struct ath_rateset *)mcs_set)->rs_nrates; i++) {
|
for (i = 0; i < ((struct ath_rateset *)mcs_set)->rs_nrates; i++) {
|
||||||
for (j = 0; j < rate_table->rate_cnt; j++) {
|
for (j = 0; j < rate_table->rate_cnt; j++) {
|
||||||
u_int32_t phy = rate_table->info[j].phy;
|
u32 phy = rate_table->info[j].phy;
|
||||||
u_int32_t valid = (ath_rc_priv->single_stream ?
|
u32 valid = (ath_rc_priv->single_stream ?
|
||||||
rate_table->info[j].valid_single_stream :
|
rate_table->info[j].valid_single_stream :
|
||||||
rate_table->info[j].valid);
|
rate_table->info[j].valid);
|
||||||
|
|
||||||
@ -796,6 +797,8 @@ static struct ath_rate_node *ath_rate_node_alloc(struct ath_vap *avp,
|
|||||||
|
|
||||||
anode->avp = avp;
|
anode->avp = avp;
|
||||||
anode->asc = rsc;
|
anode->asc = rsc;
|
||||||
|
avp->rc_node = anode;
|
||||||
|
|
||||||
return anode;
|
return anode;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -811,8 +814,8 @@ void ath_rate_detach(struct ath_rate_softc *asc)
|
|||||||
kfree(asc);
|
kfree(asc);
|
||||||
}
|
}
|
||||||
|
|
||||||
u_int8_t ath_rate_findrateix(struct ath_softc *sc,
|
u8 ath_rate_findrateix(struct ath_softc *sc,
|
||||||
u_int8_t dot11rate)
|
u8 dot11rate)
|
||||||
{
|
{
|
||||||
const struct ath_rate_table *ratetable;
|
const struct ath_rate_table *ratetable;
|
||||||
struct ath_rate_softc *rsc = sc->sc_rc;
|
struct ath_rate_softc *rsc = sc->sc_rc;
|
||||||
@ -824,10 +827,10 @@ u_int8_t ath_rate_findrateix(struct ath_softc *sc,
|
|||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
for (i = 0; i < ratetable->rate_cnt; i++) {
|
for (i = 0; i < ratetable->rate_cnt; i++) {
|
||||||
if ((ratetable->info[i].dot11rate & 0x7f) ==
|
if ((ratetable->info[i].dot11rate & 0x7f) == (dot11rate & 0x7f))
|
||||||
(dot11rate & 0x7f))
|
|
||||||
return i;
|
return i;
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -837,7 +840,7 @@ u_int8_t ath_rate_findrateix(struct ath_softc *sc,
|
|||||||
* with an AP. Otherwise this gets called, for example, when
|
* with an AP. Otherwise this gets called, for example, when
|
||||||
* the we transition to run state when operating as an AP.
|
* the we transition to run state when operating as an AP.
|
||||||
*/
|
*/
|
||||||
void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp, int up)
|
void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp)
|
||||||
{
|
{
|
||||||
struct ath_rate_softc *asc = sc->sc_rc;
|
struct ath_rate_softc *asc = sc->sc_rc;
|
||||||
|
|
||||||
@ -862,13 +865,14 @@ void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp, int up)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
|
static u8 ath_rc_ratefind_ht(struct ath_softc *sc,
|
||||||
struct ath_rate_node *ath_rc_priv,
|
struct ath_rate_node *ath_rc_priv,
|
||||||
const struct ath_rate_table *rate_table,
|
const struct ath_rate_table *rate_table,
|
||||||
int probe_allowed, int *is_probing, int is_retry)
|
int probe_allowed, int *is_probing,
|
||||||
|
int is_retry)
|
||||||
{
|
{
|
||||||
u_int32_t dt, best_thruput, this_thruput, now_msec;
|
u32 dt, best_thruput, this_thruput, now_msec;
|
||||||
u_int8_t rate, next_rate, best_rate, maxindex, minindex;
|
u8 rate, next_rate, best_rate, maxindex, minindex;
|
||||||
int8_t rssi_last, rssi_reduce = 0, index = 0;
|
int8_t rssi_last, rssi_reduce = 0, index = 0;
|
||||||
struct ath_tx_ratectrl *rate_ctrl = NULL;
|
struct ath_tx_ratectrl *rate_ctrl = NULL;
|
||||||
|
|
||||||
@ -896,7 +900,7 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
|
|||||||
if (dt >= 185)
|
if (dt >= 185)
|
||||||
rssi_reduce = 10;
|
rssi_reduce = 10;
|
||||||
else if (dt >= 25)
|
else if (dt >= 25)
|
||||||
rssi_reduce = (u_int8_t)((dt - 25) >> 4);
|
rssi_reduce = (u8)((dt - 25) >> 4);
|
||||||
|
|
||||||
/* Now reduce rssi_last by rssi_reduce */
|
/* Now reduce rssi_last by rssi_reduce */
|
||||||
if (rssi_last < rssi_reduce)
|
if (rssi_last < rssi_reduce)
|
||||||
@ -914,16 +918,15 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
|
|||||||
|
|
||||||
minindex = 0;
|
minindex = 0;
|
||||||
best_rate = minindex;
|
best_rate = minindex;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Try the higher rate first. It will reduce memory moving time
|
* Try the higher rate first. It will reduce memory moving time
|
||||||
* if we have very good channel characteristics.
|
* if we have very good channel characteristics.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
for (index = maxindex; index >= minindex ; index--) {
|
for (index = maxindex; index >= minindex ; index--) {
|
||||||
u_int8_t per_thres;
|
u8 per_thres;
|
||||||
|
|
||||||
rate = rate_ctrl->valid_rate_index[index];
|
rate = rate_ctrl->valid_rate_index[index];
|
||||||
|
|
||||||
if (rate > rate_ctrl->rate_max_phy)
|
if (rate > rate_ctrl->rate_max_phy)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
@ -967,7 +970,6 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
if (rate >= rate_ctrl->rate_max_phy && probe_allowed) {
|
if (rate >= rate_ctrl->rate_max_phy && probe_allowed) {
|
||||||
|
|
||||||
rate = rate_ctrl->rate_max_phy;
|
rate = rate_ctrl->rate_max_phy;
|
||||||
|
|
||||||
/* Probe the next allowed phy state */
|
/* Probe the next allowed phy state */
|
||||||
@ -1002,7 +1004,9 @@ static u_int8_t ath_rc_ratefind_ht(struct ath_softc *sc,
|
|||||||
}
|
}
|
||||||
|
|
||||||
static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table ,
|
static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table ,
|
||||||
struct ath_rc_series *series, u_int8_t tries, u_int8_t rix,
|
struct ath_rc_series *series,
|
||||||
|
u8 tries,
|
||||||
|
u8 rix,
|
||||||
int rtsctsenable)
|
int rtsctsenable)
|
||||||
{
|
{
|
||||||
series->tries = tries;
|
series->tries = tries;
|
||||||
@ -1018,13 +1022,14 @@ static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table ,
|
|||||||
series->max_4ms_framelen = rate_table->info[rix].max_4ms_framelen;
|
series->max_4ms_framelen = rate_table->info[rix].max_4ms_framelen;
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int8_t ath_rc_rate_getidx(struct ath_softc *sc,
|
static u8 ath_rc_rate_getidx(struct ath_softc *sc,
|
||||||
struct ath_rate_node *ath_rc_priv,
|
struct ath_rate_node *ath_rc_priv,
|
||||||
const struct ath_rate_table *rate_table,
|
const struct ath_rate_table *rate_table,
|
||||||
u_int8_t rix, u_int16_t stepdown, u_int16_t min_rate)
|
u8 rix, u16 stepdown,
|
||||||
|
u16 min_rate)
|
||||||
{
|
{
|
||||||
u_int32_t j;
|
u32 j;
|
||||||
u_int8_t nextindex;
|
u8 nextindex;
|
||||||
struct ath_tx_ratectrl *rate_ctrl =
|
struct ath_tx_ratectrl *rate_ctrl =
|
||||||
(struct ath_tx_ratectrl *)(ath_rc_priv);
|
(struct ath_tx_ratectrl *)(ath_rc_priv);
|
||||||
|
|
||||||
@ -1051,9 +1056,10 @@ static u_int8_t ath_rc_rate_getidx(struct ath_softc *sc,
|
|||||||
static void ath_rc_ratefind(struct ath_softc *sc,
|
static void ath_rc_ratefind(struct ath_softc *sc,
|
||||||
struct ath_rate_node *ath_rc_priv,
|
struct ath_rate_node *ath_rc_priv,
|
||||||
int num_tries, int num_rates, unsigned int rcflag,
|
int num_tries, int num_rates, unsigned int rcflag,
|
||||||
struct ath_rc_series series[], int *is_probe, int is_retry)
|
struct ath_rc_series series[], int *is_probe,
|
||||||
|
int is_retry)
|
||||||
{
|
{
|
||||||
u_int8_t try_per_rate = 0, i = 0, rix, nrix;
|
u8 try_per_rate = 0, i = 0, rix, nrix;
|
||||||
struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
|
struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
|
||||||
struct ath_rate_table *rate_table;
|
struct ath_rate_table *rate_table;
|
||||||
|
|
||||||
@ -1087,8 +1093,8 @@ static void ath_rc_ratefind(struct ath_softc *sc,
|
|||||||
|
|
||||||
/* Fill in the other rates for multirate retry */
|
/* Fill in the other rates for multirate retry */
|
||||||
for ( ; i < num_rates; i++) {
|
for ( ; i < num_rates; i++) {
|
||||||
u_int8_t try_num;
|
u8 try_num;
|
||||||
u_int8_t min_rate;
|
u8 min_rate;
|
||||||
|
|
||||||
try_num = ((i + 1) == num_rates) ?
|
try_num = ((i + 1) == num_rates) ?
|
||||||
num_tries - (try_per_rate * i) : try_per_rate ;
|
num_tries - (try_per_rate * i) : try_per_rate ;
|
||||||
@ -1120,8 +1126,8 @@ static void ath_rc_ratefind(struct ath_softc *sc,
|
|||||||
if ((sc->sc_curmode == WIRELESS_MODE_11NG_HT20) ||
|
if ((sc->sc_curmode == WIRELESS_MODE_11NG_HT20) ||
|
||||||
(sc->sc_curmode == WIRELESS_MODE_11NG_HT40PLUS) ||
|
(sc->sc_curmode == WIRELESS_MODE_11NG_HT40PLUS) ||
|
||||||
(sc->sc_curmode == WIRELESS_MODE_11NG_HT40MINUS)) {
|
(sc->sc_curmode == WIRELESS_MODE_11NG_HT40MINUS)) {
|
||||||
u_int8_t dot11rate = rate_table->info[rix].dot11rate;
|
u8 dot11rate = rate_table->info[rix].dot11rate;
|
||||||
u_int8_t phy = rate_table->info[rix].phy;
|
u8 phy = rate_table->info[rix].phy;
|
||||||
if (i == 4 &&
|
if (i == 4 &&
|
||||||
((dot11rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) ||
|
((dot11rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) ||
|
||||||
(dot11rate == 3 && phy == WLAN_RC_PHY_HT_20_SS))) {
|
(dot11rate == 3 && phy == WLAN_RC_PHY_HT_20_SS))) {
|
||||||
@ -1135,8 +1141,6 @@ static void ath_rc_ratefind(struct ath_softc *sc,
|
|||||||
/*
|
/*
|
||||||
* Return the Tx rate series.
|
* Return the Tx rate series.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
void ath_rate_findrate(struct ath_softc *sc,
|
void ath_rate_findrate(struct ath_softc *sc,
|
||||||
struct ath_rate_node *ath_rc_priv,
|
struct ath_rate_node *ath_rc_priv,
|
||||||
int num_tries,
|
int num_tries,
|
||||||
@ -1144,8 +1148,7 @@ void ath_rate_findrate(struct ath_softc *sc,
|
|||||||
unsigned int rcflag,
|
unsigned int rcflag,
|
||||||
struct ath_rc_series series[],
|
struct ath_rc_series series[],
|
||||||
int *is_probe,
|
int *is_probe,
|
||||||
int is_retry
|
int is_retry)
|
||||||
)
|
|
||||||
{
|
{
|
||||||
struct ath_vap *avp = ath_rc_priv->avp;
|
struct ath_vap *avp = ath_rc_priv->avp;
|
||||||
|
|
||||||
@ -1159,8 +1162,8 @@ void ath_rate_findrate(struct ath_softc *sc,
|
|||||||
} else {
|
} else {
|
||||||
/* Fixed rate */
|
/* Fixed rate */
|
||||||
int idx;
|
int idx;
|
||||||
u_int8_t flags;
|
u8 flags;
|
||||||
u_int32_t rix;
|
u32 rix;
|
||||||
struct ath_rate_softc *asc = ath_rc_priv->asc;
|
struct ath_rate_softc *asc = ath_rc_priv->asc;
|
||||||
struct ath_rate_table *rate_table;
|
struct ath_rate_table *rate_table;
|
||||||
|
|
||||||
@ -1169,7 +1172,7 @@ void ath_rate_findrate(struct ath_softc *sc,
|
|||||||
|
|
||||||
for (idx = 0; idx < 4; idx++) {
|
for (idx = 0; idx < 4; idx++) {
|
||||||
unsigned int mcs;
|
unsigned int mcs;
|
||||||
u_int8_t series_rix = 0;
|
u8 series_rix = 0;
|
||||||
|
|
||||||
series[idx].tries =
|
series[idx].tries =
|
||||||
IEEE80211_RATE_IDX_ENTRY(
|
IEEE80211_RATE_IDX_ENTRY(
|
||||||
@ -1222,14 +1225,14 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
int tx_rate, int xretries, int retries)
|
int tx_rate, int xretries, int retries)
|
||||||
{
|
{
|
||||||
struct ath_tx_ratectrl *rate_ctrl;
|
struct ath_tx_ratectrl *rate_ctrl;
|
||||||
u_int32_t now_msec = jiffies_to_msecs(jiffies);
|
u32 now_msec = jiffies_to_msecs(jiffies);
|
||||||
int state_change = FALSE, rate, count;
|
int state_change = FALSE, rate, count;
|
||||||
u_int8_t last_per;
|
u8 last_per;
|
||||||
struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
|
struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
|
||||||
struct ath_rate_table *rate_table =
|
struct ath_rate_table *rate_table =
|
||||||
(struct ath_rate_table *)asc->hw_rate_table[sc->sc_curmode];
|
(struct ath_rate_table *)asc->hw_rate_table[sc->sc_curmode];
|
||||||
|
|
||||||
static u_int32_t nretry_to_per_lookup[10] = {
|
static u32 nretry_to_per_lookup[10] = {
|
||||||
100 * 0 / 1,
|
100 * 0 / 1,
|
||||||
100 * 1 / 4,
|
100 * 1 / 4,
|
||||||
100 * 1 / 2,
|
100 * 1 / 2,
|
||||||
@ -1265,7 +1268,6 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
rate_ctrl->state[tx_rate].per += 30;
|
rate_ctrl->state[tx_rate].per += 30;
|
||||||
if (rate_ctrl->state[tx_rate].per > 100)
|
if (rate_ctrl->state[tx_rate].per > 100)
|
||||||
rate_ctrl->state[tx_rate].per = 100;
|
rate_ctrl->state[tx_rate].per = 100;
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
/* xretries == 2 */
|
/* xretries == 2 */
|
||||||
count = sizeof(nretry_to_per_lookup) /
|
count = sizeof(nretry_to_per_lookup) /
|
||||||
@ -1274,7 +1276,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
retries = count - 1;
|
retries = count - 1;
|
||||||
/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
|
/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
|
||||||
rate_ctrl->state[tx_rate].per =
|
rate_ctrl->state[tx_rate].per =
|
||||||
(u_int8_t)(rate_ctrl->state[tx_rate].per -
|
(u8)(rate_ctrl->state[tx_rate].per -
|
||||||
(rate_ctrl->state[tx_rate].per >> 3) +
|
(rate_ctrl->state[tx_rate].per >> 3) +
|
||||||
((100) >> 3));
|
((100) >> 3));
|
||||||
}
|
}
|
||||||
@ -1285,7 +1287,6 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
rate_ctrl->probe_rate = 0;
|
rate_ctrl->probe_rate = 0;
|
||||||
|
|
||||||
} else { /* xretries == 0 */
|
} else { /* xretries == 0 */
|
||||||
|
|
||||||
/* Update the PER. */
|
/* Update the PER. */
|
||||||
/* Make sure it doesn't index out of array's bounds. */
|
/* Make sure it doesn't index out of array's bounds. */
|
||||||
count = sizeof(nretry_to_per_lookup) /
|
count = sizeof(nretry_to_per_lookup) /
|
||||||
@ -1308,7 +1309,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
*/
|
*/
|
||||||
if (info_priv->n_frames > 0)
|
if (info_priv->n_frames > 0)
|
||||||
rate_ctrl->state[tx_rate].per
|
rate_ctrl->state[tx_rate].per
|
||||||
= (u_int8_t)
|
= (u8)
|
||||||
(rate_ctrl->state[tx_rate].per -
|
(rate_ctrl->state[tx_rate].per -
|
||||||
(rate_ctrl->state[tx_rate].per >> 3) +
|
(rate_ctrl->state[tx_rate].per >> 3) +
|
||||||
((100*(retries*info_priv->n_frames +
|
((100*(retries*info_priv->n_frames +
|
||||||
@ -1318,7 +1319,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
} else {
|
} else {
|
||||||
/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
|
/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
|
||||||
|
|
||||||
rate_ctrl->state[tx_rate].per = (u_int8_t)
|
rate_ctrl->state[tx_rate].per = (u8)
|
||||||
(rate_ctrl->state[tx_rate].per -
|
(rate_ctrl->state[tx_rate].per -
|
||||||
(rate_ctrl->state[tx_rate].per >> 3) +
|
(rate_ctrl->state[tx_rate].per >> 3) +
|
||||||
(nretry_to_per_lookup[retries] >> 3));
|
(nretry_to_per_lookup[retries] >> 3));
|
||||||
@ -1346,7 +1347,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
*/
|
*/
|
||||||
rate_ctrl->probe_rate = 0;
|
rate_ctrl->probe_rate = 0;
|
||||||
} else {
|
} else {
|
||||||
u_int8_t probe_rate = 0;
|
u8 probe_rate = 0;
|
||||||
|
|
||||||
rate_ctrl->rate_max_phy = rate_ctrl->probe_rate;
|
rate_ctrl->rate_max_phy = rate_ctrl->probe_rate;
|
||||||
probe_rate = rate_ctrl->probe_rate;
|
probe_rate = rate_ctrl->probe_rate;
|
||||||
@ -1427,7 +1428,6 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/* For all cases */
|
/* For all cases */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -1438,7 +1438,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
|
|||||||
rate_table->info[tx_rate].ratekbps <=
|
rate_table->info[tx_rate].ratekbps <=
|
||||||
rate_table->info[rate_ctrl->rate_max_phy].ratekbps) {
|
rate_table->info[rate_ctrl->rate_max_phy].ratekbps) {
|
||||||
ath_rc_get_nextlowervalid_txrate(rate_table, rate_ctrl,
|
ath_rc_get_nextlowervalid_txrate(rate_table, rate_ctrl,
|
||||||
(u_int8_t) tx_rate, &rate_ctrl->rate_max_phy);
|
(u8) tx_rate, &rate_ctrl->rate_max_phy);
|
||||||
|
|
||||||
/* Don't probe for a little while. */
|
/* Don't probe for a little while. */
|
||||||
rate_ctrl->probe_time = now_msec;
|
rate_ctrl->probe_time = now_msec;
|
||||||
@ -1563,8 +1563,8 @@ static void ath_rc_update(struct ath_softc *sc,
|
|||||||
struct ath_rate_table *rate_table;
|
struct ath_rate_table *rate_table;
|
||||||
struct ath_tx_ratectrl *rate_ctrl;
|
struct ath_tx_ratectrl *rate_ctrl;
|
||||||
struct ath_rc_series rcs[4];
|
struct ath_rc_series rcs[4];
|
||||||
u_int8_t flags;
|
u8 flags;
|
||||||
u_int32_t series = 0, rix;
|
u32 series = 0, rix;
|
||||||
|
|
||||||
memcpy(rcs, info_priv->rcs, 4 * sizeof(rcs[0]));
|
memcpy(rcs, info_priv->rcs, 4 * sizeof(rcs[0]));
|
||||||
rate_table = (struct ath_rate_table *)
|
rate_table = (struct ath_rate_table *)
|
||||||
@ -1577,7 +1577,6 @@ static void ath_rc_update(struct ath_softc *sc,
|
|||||||
* are intermediate rate failures to be processed.
|
* are intermediate rate failures to be processed.
|
||||||
*/
|
*/
|
||||||
if (final_ts_idx != 0) {
|
if (final_ts_idx != 0) {
|
||||||
|
|
||||||
/* Process intermediate rates that failed.*/
|
/* Process intermediate rates that failed.*/
|
||||||
for (series = 0; series < final_ts_idx ; series++) {
|
for (series = 0; series < final_ts_idx ; series++) {
|
||||||
if (rcs[series].tries != 0) {
|
if (rcs[series].tries != 0) {
|
||||||
@ -1641,9 +1640,9 @@ static void ath_rc_update(struct ath_softc *sc,
|
|||||||
/*
|
/*
|
||||||
* Process a tx descriptor for a completed transmit (success or failure).
|
* Process a tx descriptor for a completed transmit (success or failure).
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static void ath_rate_tx_complete(struct ath_softc *sc,
|
static void ath_rate_tx_complete(struct ath_softc *sc,
|
||||||
struct ath_node *an, struct ath_rate_node *rc_priv,
|
struct ath_node *an,
|
||||||
|
struct ath_rate_node *rc_priv,
|
||||||
struct ath_tx_info_priv *info_priv)
|
struct ath_tx_info_priv *info_priv)
|
||||||
{
|
{
|
||||||
int final_ts_idx = info_priv->tx.ts_rateindex;
|
int final_ts_idx = info_priv->tx.ts_rateindex;
|
||||||
@ -1678,8 +1677,8 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
|
|||||||
tx_status = 1;
|
tx_status = 1;
|
||||||
|
|
||||||
ath_rc_update(sc, rc_priv, info_priv, final_ts_idx, tx_status,
|
ath_rc_update(sc, rc_priv, info_priv, final_ts_idx, tx_status,
|
||||||
(is_underrun) ? ATH_11N_TXMAXTRY
|
(is_underrun) ? ATH_11N_TXMAXTRY :
|
||||||
:info_priv->tx.ts_longretry);
|
info_priv->tx.ts_longretry);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -1693,17 +1692,17 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
|
|||||||
*/
|
*/
|
||||||
static void ath_rc_sib_update(struct ath_softc *sc,
|
static void ath_rc_sib_update(struct ath_softc *sc,
|
||||||
struct ath_rate_node *ath_rc_priv,
|
struct ath_rate_node *ath_rc_priv,
|
||||||
u_int32_t capflag, int keep_state,
|
u32 capflag, int keep_state,
|
||||||
struct ath_rateset *negotiated_rates,
|
struct ath_rateset *negotiated_rates,
|
||||||
struct ath_rateset *negotiated_htrates)
|
struct ath_rateset *negotiated_htrates)
|
||||||
{
|
{
|
||||||
struct ath_rate_table *rate_table = NULL;
|
struct ath_rate_table *rate_table = NULL;
|
||||||
struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
|
struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
|
||||||
struct ath_rateset *rateset = negotiated_rates;
|
struct ath_rateset *rateset = negotiated_rates;
|
||||||
u_int8_t *ht_mcs = (u_int8_t *)negotiated_htrates;
|
u8 *ht_mcs = (u8 *)negotiated_htrates;
|
||||||
struct ath_tx_ratectrl *rate_ctrl = (struct ath_tx_ratectrl *)
|
struct ath_tx_ratectrl *rate_ctrl = (struct ath_tx_ratectrl *)
|
||||||
(ath_rc_priv);
|
(ath_rc_priv);
|
||||||
u_int8_t i, j, k, hi = 0, hthi = 0;
|
u8 i, j, k, hi = 0, hthi = 0;
|
||||||
|
|
||||||
rate_table = (struct ath_rate_table *)
|
rate_table = (struct ath_rate_table *)
|
||||||
asc->hw_rate_table[sc->sc_curmode];
|
asc->hw_rate_table[sc->sc_curmode];
|
||||||
@ -1742,7 +1741,9 @@ static void ath_rc_sib_update(struct ath_softc *sc,
|
|||||||
rateset, capflag);
|
rateset, capflag);
|
||||||
if (capflag & WLAN_RC_HT_FLAG) {
|
if (capflag & WLAN_RC_HT_FLAG) {
|
||||||
hthi = ath_rc_sib_setvalid_htrates(ath_rc_priv,
|
hthi = ath_rc_sib_setvalid_htrates(ath_rc_priv,
|
||||||
rate_table, ht_mcs, capflag);
|
rate_table,
|
||||||
|
ht_mcs,
|
||||||
|
capflag);
|
||||||
}
|
}
|
||||||
hi = A_MAX(hi, hthi);
|
hi = A_MAX(hi, hthi);
|
||||||
}
|
}
|
||||||
@ -1834,15 +1835,14 @@ static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta)
|
|||||||
rc_priv->neg_rates.rs_nrates = j;
|
rc_priv->neg_rates.rs_nrates = j;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void ath_rc_node_update(struct ieee80211_hw *hw,
|
void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv)
|
||||||
struct ath_rate_node *rc_priv)
|
|
||||||
{
|
{
|
||||||
struct ath_softc *sc = hw->priv;
|
struct ath_softc *sc = hw->priv;
|
||||||
u_int32_t capflag = 0;
|
u32 capflag = 0;
|
||||||
|
|
||||||
if (hw->conf.ht_conf.ht_supported) {
|
if (hw->conf.ht_conf.ht_supported) {
|
||||||
capflag |= ATH_RC_HT_FLAG | ATH_RC_DS_FLAG;
|
capflag |= ATH_RC_HT_FLAG | ATH_RC_DS_FLAG;
|
||||||
if (sc->sc_ht_info.tx_chan_width == HAL_HT_MACMODE_2040)
|
if (sc->sc_ht_info.tx_chan_width == ATH9K_HT_MACMODE_2040)
|
||||||
capflag |= ATH_RC_CW40_FLAG;
|
capflag |= ATH_RC_CW40_FLAG;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -149,31 +149,31 @@ struct ath_rate_table {
|
|||||||
int valid; /* Valid for use in rate control */
|
int valid; /* Valid for use in rate control */
|
||||||
int valid_single_stream;/* Valid for use in rate control
|
int valid_single_stream;/* Valid for use in rate control
|
||||||
for single stream operation */
|
for single stream operation */
|
||||||
u_int8_t phy; /* CCK/OFDM/TURBO/XR */
|
u8 phy; /* CCK/OFDM/TURBO/XR */
|
||||||
u_int32_t ratekbps; /* Rate in Kbits per second */
|
u32 ratekbps; /* Rate in Kbits per second */
|
||||||
u_int32_t user_ratekbps; /* User rate in KBits per second */
|
u32 user_ratekbps; /* User rate in KBits per second */
|
||||||
u_int8_t ratecode; /* rate that goes into
|
u8 ratecode; /* rate that goes into
|
||||||
hw descriptors */
|
hw descriptors */
|
||||||
u_int8_t short_preamble; /* Mask for enabling short preamble
|
u8 short_preamble; /* Mask for enabling short preamble
|
||||||
in rate code for CCK */
|
in rate code for CCK */
|
||||||
u_int8_t dot11rate; /* Value that goes into supported
|
u8 dot11rate; /* Value that goes into supported
|
||||||
rates info element of MLME */
|
rates info element of MLME */
|
||||||
u_int8_t ctrl_rate; /* Index of next lower basic rate,
|
u8 ctrl_rate; /* Index of next lower basic rate,
|
||||||
used for duration computation */
|
used for duration computation */
|
||||||
int8_t rssi_ack_validmin; /* Rate control related */
|
int8_t rssi_ack_validmin; /* Rate control related */
|
||||||
int8_t rssi_ack_deltamin; /* Rate control related */
|
int8_t rssi_ack_deltamin; /* Rate control related */
|
||||||
u_int8_t base_index; /* base rate index */
|
u8 base_index; /* base rate index */
|
||||||
u_int8_t cw40index; /* 40cap rate index */
|
u8 cw40index; /* 40cap rate index */
|
||||||
u_int8_t sgi_index; /* shortgi rate index */
|
u8 sgi_index; /* shortgi rate index */
|
||||||
u_int8_t ht_index; /* shortgi rate index */
|
u8 ht_index; /* shortgi rate index */
|
||||||
u_int32_t max_4ms_framelen; /* Maximum frame length(bytes)
|
u32 max_4ms_framelen; /* Maximum frame length(bytes)
|
||||||
for 4ms tx duration */
|
for 4ms tx duration */
|
||||||
} info[RATE_TABLE_SIZE];
|
} info[RATE_TABLE_SIZE];
|
||||||
u_int32_t probe_interval; /* interval for ratectrl to
|
u32 probe_interval; /* interval for ratectrl to
|
||||||
probe for other rates */
|
probe for other rates */
|
||||||
u_int32_t rssi_reduce_interval; /* interval for ratectrl
|
u32 rssi_reduce_interval; /* interval for ratectrl
|
||||||
to reduce RSSI */
|
to reduce RSSI */
|
||||||
u_int8_t initial_ratemax; /* the initial ratemax value used
|
u8 initial_ratemax; /* the initial ratemax value used
|
||||||
in ath_rc_sib_update() */
|
in ath_rc_sib_update() */
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -182,10 +182,10 @@ struct ath_rate_table {
|
|||||||
#define ATH_RC_SHORT_PREAMBLE 0x00000004
|
#define ATH_RC_SHORT_PREAMBLE 0x00000004
|
||||||
|
|
||||||
struct ath_rc_series {
|
struct ath_rc_series {
|
||||||
u_int8_t rix;
|
u8 rix;
|
||||||
u_int8_t tries;
|
u8 tries;
|
||||||
u_int8_t flags;
|
u8 flags;
|
||||||
u_int32_t max_4ms_framelen;
|
u32 max_4ms_framelen;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* rcs_flags definition */
|
/* rcs_flags definition */
|
||||||
@ -203,7 +203,7 @@ struct ath_rc_series {
|
|||||||
|
|
||||||
struct ath_tx_ratectrl_state {
|
struct ath_tx_ratectrl_state {
|
||||||
int8_t rssi_thres; /* required rssi for this rate (dB) */
|
int8_t rssi_thres; /* required rssi for this rate (dB) */
|
||||||
u_int8_t per; /* recent estimate of packet error rate (%) */
|
u8 per; /* recent estimate of packet error rate (%) */
|
||||||
};
|
};
|
||||||
|
|
||||||
struct ath_tx_ratectrl {
|
struct ath_tx_ratectrl {
|
||||||
@ -215,34 +215,34 @@ struct ath_tx_ratectrl {
|
|||||||
int32_t rssi_sum_cnt; /* count of rssi_sum for averaging */
|
int32_t rssi_sum_cnt; /* count of rssi_sum for averaging */
|
||||||
int32_t rssi_sum_rate; /* rate that we are averaging */
|
int32_t rssi_sum_rate; /* rate that we are averaging */
|
||||||
int32_t rssi_sum; /* running sum of rssi for averaging */
|
int32_t rssi_sum; /* running sum of rssi for averaging */
|
||||||
u_int32_t valid_txrate_mask; /* mask of valid rates */
|
u32 valid_txrate_mask; /* mask of valid rates */
|
||||||
u_int8_t rate_table_size; /* rate table size */
|
u8 rate_table_size; /* rate table size */
|
||||||
u_int8_t rate_max; /* max rate that has recently worked */
|
u8 rate_max; /* max rate that has recently worked */
|
||||||
u_int8_t probe_rate; /* rate we are probing at */
|
u8 probe_rate; /* rate we are probing at */
|
||||||
u_int32_t rssi_time; /* msec timestamp for last ack rssi */
|
u32 rssi_time; /* msec timestamp for last ack rssi */
|
||||||
u_int32_t rssi_down_time; /* msec timestamp for last down step */
|
u32 rssi_down_time; /* msec timestamp for last down step */
|
||||||
u_int32_t probe_time; /* msec timestamp for last probe */
|
u32 probe_time; /* msec timestamp for last probe */
|
||||||
u_int8_t hw_maxretry_pktcnt; /* num packets since we got
|
u8 hw_maxretry_pktcnt; /* num packets since we got
|
||||||
HW max retry error */
|
HW max retry error */
|
||||||
u_int8_t max_valid_rate; /* maximum number of valid rate */
|
u8 max_valid_rate; /* maximum number of valid rate */
|
||||||
u_int8_t valid_rate_index[MAX_TX_RATE_TBL]; /* valid rate index */
|
u8 valid_rate_index[MAX_TX_RATE_TBL]; /* valid rate index */
|
||||||
u_int32_t per_down_time; /* msec timstamp for last
|
u32 per_down_time; /* msec timstamp for last
|
||||||
PER down step */
|
PER down step */
|
||||||
|
|
||||||
/* 11n state */
|
/* 11n state */
|
||||||
u_int8_t valid_phy_ratecnt[WLAN_RC_PHY_MAX]; /* valid rate count */
|
u8 valid_phy_ratecnt[WLAN_RC_PHY_MAX]; /* valid rate count */
|
||||||
u_int8_t valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL];
|
u8 valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL];
|
||||||
u_int8_t rc_phy_mode;
|
u8 rc_phy_mode;
|
||||||
u_int8_t rate_max_phy; /* Phy index for the max rate */
|
u8 rate_max_phy; /* Phy index for the max rate */
|
||||||
u_int32_t rate_max_lastused; /* msec timstamp of when we
|
u32 rate_max_lastused; /* msec timstamp of when we
|
||||||
last used rateMaxPhy */
|
last used rateMaxPhy */
|
||||||
u_int32_t probe_interval; /* interval for ratectrl to probe
|
u32 probe_interval; /* interval for ratectrl to probe
|
||||||
for other rates */
|
for other rates */
|
||||||
};
|
};
|
||||||
|
|
||||||
struct ath_rateset {
|
struct ath_rateset {
|
||||||
u_int8_t rs_nrates;
|
u8 rs_nrates;
|
||||||
u_int8_t rs_rates[ATH_RATE_MAX];
|
u8 rs_rates[ATH_RATE_MAX];
|
||||||
};
|
};
|
||||||
|
|
||||||
/* per-device state */
|
/* per-device state */
|
||||||
@ -255,18 +255,18 @@ struct ath_rate_softc {
|
|||||||
/* per-node state */
|
/* per-node state */
|
||||||
struct ath_rate_node {
|
struct ath_rate_node {
|
||||||
struct ath_tx_ratectrl tx_ratectrl; /* rate control state proper */
|
struct ath_tx_ratectrl tx_ratectrl; /* rate control state proper */
|
||||||
u_int32_t prev_data_rix; /* rate idx of last data frame */
|
u32 prev_data_rix; /* rate idx of last data frame */
|
||||||
|
|
||||||
/* map of rate ix -> negotiated rate set ix */
|
/* map of rate ix -> negotiated rate set ix */
|
||||||
u_int8_t rixmap[MAX_TX_RATE_TBL];
|
u8 rixmap[MAX_TX_RATE_TBL];
|
||||||
|
|
||||||
/* map of ht rate ix -> negotiated rate set ix */
|
/* map of ht rate ix -> negotiated rate set ix */
|
||||||
u_int8_t ht_rixmap[MAX_TX_RATE_TBL];
|
u8 ht_rixmap[MAX_TX_RATE_TBL];
|
||||||
|
|
||||||
u_int8_t ht_cap; /* ht capabilities */
|
u8 ht_cap; /* ht capabilities */
|
||||||
u_int8_t ant_tx; /* current transmit antenna */
|
u8 ant_tx; /* current transmit antenna */
|
||||||
|
|
||||||
u_int8_t single_stream; /* When TRUE, only single
|
u8 single_stream; /* When TRUE, only single
|
||||||
stream Tx possible */
|
stream Tx possible */
|
||||||
struct ath_rateset neg_rates; /* Negotiated rates */
|
struct ath_rateset neg_rates; /* Negotiated rates */
|
||||||
struct ath_rateset neg_ht_rates; /* Negotiated HT rates */
|
struct ath_rateset neg_ht_rates; /* Negotiated HT rates */
|
||||||
@ -280,7 +280,7 @@ struct ath_tx_info_priv {
|
|||||||
struct ath_tx_status tx;
|
struct ath_tx_status tx;
|
||||||
int n_frames;
|
int n_frames;
|
||||||
int n_bad_frames;
|
int n_bad_frames;
|
||||||
u_int8_t min_rate;
|
u8 min_rate;
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -294,7 +294,8 @@ void ath_rate_detach(struct ath_rate_softc *asc);
|
|||||||
* Important mostly as the analog to ath_rate_newassoc when operating
|
* Important mostly as the analog to ath_rate_newassoc when operating
|
||||||
* in station mode.
|
* in station mode.
|
||||||
*/
|
*/
|
||||||
void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp, int up);
|
void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv);
|
||||||
|
void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Return the tx rate series.
|
* Return the tx rate series.
|
||||||
@ -306,8 +307,8 @@ void ath_rate_findrate(struct ath_softc *sc, struct ath_rate_node *ath_rc_priv,
|
|||||||
/*
|
/*
|
||||||
* Return rate index for given Dot11 Rate.
|
* Return rate index for given Dot11 Rate.
|
||||||
*/
|
*/
|
||||||
u_int8_t ath_rate_findrateix(struct ath_softc *sc,
|
u8 ath_rate_findrateix(struct ath_softc *sc,
|
||||||
u_int8_t dot11_rate);
|
u8 dot11_rate);
|
||||||
|
|
||||||
/* Routines to register/unregister rate control algorithm */
|
/* Routines to register/unregister rate control algorithm */
|
||||||
int ath_rate_control_register(void);
|
int ath_rate_control_register(void);
|
||||||
|
@ -75,7 +75,7 @@ static int ath_bar_rx(struct ath_softc *sc,
|
|||||||
struct sk_buff *tskb;
|
struct sk_buff *tskb;
|
||||||
struct ath_recv_status *rx_status;
|
struct ath_recv_status *rx_status;
|
||||||
int tidno, index, cindex;
|
int tidno, index, cindex;
|
||||||
u_int16_t seqno;
|
u16 seqno;
|
||||||
|
|
||||||
/* look at BAR contents */
|
/* look at BAR contents */
|
||||||
|
|
||||||
@ -148,8 +148,8 @@ static int ath_ampdu_input(struct ath_softc *sc,
|
|||||||
struct ieee80211_hdr *hdr;
|
struct ieee80211_hdr *hdr;
|
||||||
struct ath_arx_tid *rxtid;
|
struct ath_arx_tid *rxtid;
|
||||||
struct ath_rxbuf *rxbuf;
|
struct ath_rxbuf *rxbuf;
|
||||||
u_int8_t type, subtype;
|
u8 type, subtype;
|
||||||
u_int16_t rxseq;
|
u16 rxseq;
|
||||||
int tid = 0, index, cindex, rxdiff;
|
int tid = 0, index, cindex, rxdiff;
|
||||||
__le16 fc;
|
__le16 fc;
|
||||||
u8 *qc;
|
u8 *qc;
|
||||||
@ -184,7 +184,7 @@ static int ath_ampdu_input(struct ath_softc *sc,
|
|||||||
tid = qc[0] & 0xf;
|
tid = qc[0] & 0xf;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (sc->sc_opmode == HAL_M_STA) {
|
if (sc->sc_opmode == ATH9K_M_STA) {
|
||||||
/* Drop the frame not belonging to me. */
|
/* Drop the frame not belonging to me. */
|
||||||
if (memcmp(hdr->addr1, sc->sc_myaddr, ETH_ALEN)) {
|
if (memcmp(hdr->addr1, sc->sc_myaddr, ETH_ALEN)) {
|
||||||
dev_kfree_skb(skb);
|
dev_kfree_skb(skb);
|
||||||
@ -386,10 +386,10 @@ static void ath_rx_flush_tid(struct ath_softc *sc,
|
|||||||
}
|
}
|
||||||
|
|
||||||
static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
|
static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
|
||||||
u_int32_t len)
|
u32 len)
|
||||||
{
|
{
|
||||||
struct sk_buff *skb;
|
struct sk_buff *skb;
|
||||||
u_int off;
|
u32 off;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Cache-line-align. This is important (for the
|
* Cache-line-align. This is important (for the
|
||||||
@ -441,7 +441,7 @@ static void ath_rx_requeue(struct ath_softc *sc, struct sk_buff *skb)
|
|||||||
static int ath_rx_indicate(struct ath_softc *sc,
|
static int ath_rx_indicate(struct ath_softc *sc,
|
||||||
struct sk_buff *skb,
|
struct sk_buff *skb,
|
||||||
struct ath_recv_status *status,
|
struct ath_recv_status *status,
|
||||||
u_int16_t keyix)
|
u16 keyix)
|
||||||
{
|
{
|
||||||
struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf;
|
struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf;
|
||||||
struct sk_buff *nskb;
|
struct sk_buff *nskb;
|
||||||
@ -471,7 +471,7 @@ static int ath_rx_indicate(struct ath_softc *sc,
|
|||||||
static void ath_opmode_init(struct ath_softc *sc)
|
static void ath_opmode_init(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
u_int32_t rfilt, mfilt[2];
|
u32 rfilt, mfilt[2];
|
||||||
|
|
||||||
/* configure rx filter */
|
/* configure rx filter */
|
||||||
rfilt = ath_calcrxfilter(sc);
|
rfilt = ath_calcrxfilter(sc);
|
||||||
@ -515,7 +515,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
|
|||||||
*/
|
*/
|
||||||
sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN,
|
sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN,
|
||||||
min(sc->sc_cachelsz,
|
min(sc->sc_cachelsz,
|
||||||
(u_int16_t)64));
|
(u16)64));
|
||||||
|
|
||||||
DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
|
DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
|
||||||
__func__, sc->sc_cachelsz, sc->sc_rxbufsize);
|
__func__, sc->sc_cachelsz, sc->sc_rxbufsize);
|
||||||
@ -594,34 +594,34 @@ void ath_rx_cleanup(struct ath_softc *sc)
|
|||||||
* - when scanning
|
* - when scanning
|
||||||
*/
|
*/
|
||||||
|
|
||||||
u_int32_t ath_calcrxfilter(struct ath_softc *sc)
|
u32 ath_calcrxfilter(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
#define RX_FILTER_PRESERVE (HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR)
|
#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
|
||||||
u_int32_t rfilt;
|
u32 rfilt;
|
||||||
|
|
||||||
rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
|
rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
|
||||||
| HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST
|
| ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
|
||||||
| HAL_RX_FILTER_MCAST;
|
| ATH9K_RX_FILTER_MCAST;
|
||||||
|
|
||||||
/* If not a STA, enable processing of Probe Requests */
|
/* If not a STA, enable processing of Probe Requests */
|
||||||
if (sc->sc_opmode != HAL_M_STA)
|
if (sc->sc_opmode != ATH9K_M_STA)
|
||||||
rfilt |= HAL_RX_FILTER_PROBEREQ;
|
rfilt |= ATH9K_RX_FILTER_PROBEREQ;
|
||||||
|
|
||||||
/* Can't set HOSTAP into promiscous mode */
|
/* Can't set HOSTAP into promiscous mode */
|
||||||
if (sc->sc_opmode == HAL_M_MONITOR) {
|
if (sc->sc_opmode == ATH9K_M_MONITOR) {
|
||||||
rfilt |= HAL_RX_FILTER_PROM;
|
rfilt |= ATH9K_RX_FILTER_PROM;
|
||||||
/* ??? To prevent from sending ACK */
|
/* ??? To prevent from sending ACK */
|
||||||
rfilt &= ~HAL_RX_FILTER_UCAST;
|
rfilt &= ~ATH9K_RX_FILTER_UCAST;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS ||
|
if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS ||
|
||||||
sc->sc_scanning)
|
sc->sc_scanning)
|
||||||
rfilt |= HAL_RX_FILTER_BEACON;
|
rfilt |= ATH9K_RX_FILTER_BEACON;
|
||||||
|
|
||||||
/* If in HOSTAP mode, want to enable reception of PSPOLL frames
|
/* If in HOSTAP mode, want to enable reception of PSPOLL frames
|
||||||
& beacon frames */
|
& beacon frames */
|
||||||
if (sc->sc_opmode == HAL_M_HOSTAP)
|
if (sc->sc_opmode == ATH9K_M_HOSTAP)
|
||||||
rfilt |= (HAL_RX_FILTER_BEACON | HAL_RX_FILTER_PSPOLL);
|
rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
|
||||||
return rfilt;
|
return rfilt;
|
||||||
#undef RX_FILTER_PRESERVE
|
#undef RX_FILTER_PRESERVE
|
||||||
}
|
}
|
||||||
@ -677,7 +677,7 @@ start_recv:
|
|||||||
bool ath_stoprecv(struct ath_softc *sc)
|
bool ath_stoprecv(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
u_int64_t tsf;
|
u64 tsf;
|
||||||
bool stopped;
|
bool stopped;
|
||||||
|
|
||||||
ath9k_hw_stoppcurecv(ah); /* disable PCU */
|
ath9k_hw_stoppcurecv(ah); /* disable PCU */
|
||||||
@ -743,9 +743,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|||||||
struct ath_recv_status rx_status;
|
struct ath_recv_status rx_status;
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
int type, rx_processed = 0;
|
int type, rx_processed = 0;
|
||||||
u_int phyerr;
|
u32 phyerr;
|
||||||
u_int8_t chainreset = 0;
|
u8 chainreset = 0;
|
||||||
enum hal_status retval;
|
int retval;
|
||||||
__le16 fc;
|
__le16 fc;
|
||||||
|
|
||||||
do {
|
do {
|
||||||
@ -812,7 +812,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|||||||
bf->bf_daddr,
|
bf->bf_daddr,
|
||||||
PA2DESC(sc, ds->ds_link),
|
PA2DESC(sc, ds->ds_link),
|
||||||
0);
|
0);
|
||||||
if (HAL_EINPROGRESS == retval) {
|
if (retval == -EINPROGRESS) {
|
||||||
struct ath_buf *tbf;
|
struct ath_buf *tbf;
|
||||||
struct ath_desc *tds;
|
struct ath_desc *tds;
|
||||||
|
|
||||||
@ -838,7 +838,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|||||||
retval = ath9k_hw_rxprocdesc(ah,
|
retval = ath9k_hw_rxprocdesc(ah,
|
||||||
tds, tbf->bf_daddr,
|
tds, tbf->bf_daddr,
|
||||||
PA2DESC(sc, tds->ds_link), 0);
|
PA2DESC(sc, tds->ds_link), 0);
|
||||||
if (HAL_EINPROGRESS == retval) {
|
if (retval == -EINPROGRESS) {
|
||||||
spin_unlock_bh(&sc->sc_rxbuflock);
|
spin_unlock_bh(&sc->sc_rxbuflock);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -900,7 +900,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|||||||
* Enable this if you want to see
|
* Enable this if you want to see
|
||||||
* error frames in Monitor mode.
|
* error frames in Monitor mode.
|
||||||
*/
|
*/
|
||||||
if (sc->sc_opmode != HAL_M_MONITOR)
|
if (sc->sc_opmode != ATH9K_M_MONITOR)
|
||||||
goto rx_next;
|
goto rx_next;
|
||||||
#endif
|
#endif
|
||||||
/* fall thru for monitor mode handling... */
|
/* fall thru for monitor mode handling... */
|
||||||
@ -945,7 +945,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
|
|||||||
* decryption and MIC failures. For monitor mode,
|
* decryption and MIC failures. For monitor mode,
|
||||||
* we also ignore the CRC error.
|
* we also ignore the CRC error.
|
||||||
*/
|
*/
|
||||||
if (sc->sc_opmode == HAL_M_MONITOR) {
|
if (sc->sc_opmode == ATH9K_M_MONITOR) {
|
||||||
if (ds->ds_rxstat.rs_status &
|
if (ds->ds_rxstat.rs_status &
|
||||||
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
|
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
|
||||||
ATH9K_RXERR_CRC))
|
ATH9K_RXERR_CRC))
|
||||||
@ -1199,7 +1199,7 @@ int ath_rx_aggr_stop(struct ath_softc *sc,
|
|||||||
/* Rx aggregation tear down */
|
/* Rx aggregation tear down */
|
||||||
|
|
||||||
void ath_rx_aggr_teardown(struct ath_softc *sc,
|
void ath_rx_aggr_teardown(struct ath_softc *sc,
|
||||||
struct ath_node *an, u_int8_t tid)
|
struct ath_node *an, u8 tid)
|
||||||
{
|
{
|
||||||
struct ath_arx_tid *rxtid = &an->an_aggr.rx.tid[tid];
|
struct ath_arx_tid *rxtid = &an->an_aggr.rx.tid[tid];
|
||||||
|
|
||||||
|
@ -17,13 +17,14 @@
|
|||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
#include "core.h"
|
#include "core.h"
|
||||||
|
#include "hw.h"
|
||||||
#include "regd.h"
|
#include "regd.h"
|
||||||
#include "regd_common.h"
|
#include "regd_common.h"
|
||||||
|
|
||||||
static int ath9k_regd_chansort(const void *a, const void *b)
|
static int ath9k_regd_chansort(const void *a, const void *b)
|
||||||
{
|
{
|
||||||
const struct hal_channel_internal *ca = a;
|
const struct ath9k_channel *ca = a;
|
||||||
const struct hal_channel_internal *cb = b;
|
const struct ath9k_channel *cb = b;
|
||||||
|
|
||||||
return (ca->channel == cb->channel) ?
|
return (ca->channel == cb->channel) ?
|
||||||
(ca->channelFlags & CHAN_FLAGS) -
|
(ca->channelFlags & CHAN_FLAGS) -
|
||||||
@ -31,26 +32,26 @@ static int ath9k_regd_chansort(const void *a, const void *b)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
ath9k_regd_sort(void *a, u_int32_t n, u_int32_t size, ath_hal_cmp_t *cmp)
|
ath9k_regd_sort(void *a, u32 n, u32 size, ath_hal_cmp_t *cmp)
|
||||||
{
|
{
|
||||||
u_int8_t *aa = a;
|
u8 *aa = a;
|
||||||
u_int8_t *ai, *t;
|
u8 *ai, *t;
|
||||||
|
|
||||||
for (ai = aa + size; --n >= 1; ai += size)
|
for (ai = aa + size; --n >= 1; ai += size)
|
||||||
for (t = ai; t > aa; t -= size) {
|
for (t = ai; t > aa; t -= size) {
|
||||||
u_int8_t *u = t - size;
|
u8 *u = t - size;
|
||||||
if (cmp(u, t) <= 0)
|
if (cmp(u, t) <= 0)
|
||||||
break;
|
break;
|
||||||
swap(u, t, size);
|
swap(u, t, size);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int16_t ath9k_regd_get_eepromRD(struct ath_hal *ah)
|
static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah)
|
||||||
{
|
{
|
||||||
return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG;
|
return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool ath9k_regd_is_chan_bm_zero(u_int64_t *bitmask)
|
static bool ath9k_regd_is_chan_bm_zero(u64 *bitmask)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
@ -63,11 +64,11 @@ static bool ath9k_regd_is_chan_bm_zero(u_int64_t *bitmask)
|
|||||||
|
|
||||||
static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
|
static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
|
||||||
{
|
{
|
||||||
u_int16_t rd = ath9k_regd_get_eepromRD(ah);
|
u16 rd = ath9k_regd_get_eepromRD(ah);
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (rd & COUNTRY_ERD_FLAG) {
|
if (rd & COUNTRY_ERD_FLAG) {
|
||||||
u_int16_t cc = rd & ~COUNTRY_ERD_FLAG;
|
u16 cc = rd & ~COUNTRY_ERD_FLAG;
|
||||||
for (i = 0; i < ARRAY_SIZE(allCountries); i++)
|
for (i = 0; i < ARRAY_SIZE(allCountries); i++)
|
||||||
if (allCountries[i].countryCode == cc)
|
if (allCountries[i].countryCode == cc)
|
||||||
return true;
|
return true;
|
||||||
@ -84,7 +85,7 @@ static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
|
|||||||
|
|
||||||
static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
|
static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
|
||||||
{
|
{
|
||||||
u_int32_t regcap;
|
u32 regcap;
|
||||||
|
|
||||||
regcap = ah->ah_caps.halRegCap;
|
regcap = ah->ah_caps.halRegCap;
|
||||||
|
|
||||||
@ -95,9 +96,9 @@ static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
|
static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
|
||||||
u_int16_t cc)
|
u16 cc)
|
||||||
{
|
{
|
||||||
u_int16_t rd;
|
u16 rd;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (cc == CTRY_DEFAULT)
|
if (cc == CTRY_DEFAULT)
|
||||||
@ -130,12 +131,12 @@ static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int
|
static u32
|
||||||
ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
|
ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
|
||||||
struct country_code_to_enum_rd *country,
|
struct country_code_to_enum_rd *country,
|
||||||
struct regDomain *rd5GHz)
|
struct regDomain *rd5GHz)
|
||||||
{
|
{
|
||||||
u_int modesAvail;
|
u32 modesAvail;
|
||||||
|
|
||||||
modesAvail = ah->ah_caps.halWirelessModes;
|
modesAvail = ah->ah_caps.halWirelessModes;
|
||||||
|
|
||||||
@ -174,7 +175,7 @@ ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
|
|||||||
|
|
||||||
bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
|
bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
|
||||||
{
|
{
|
||||||
u_int16_t rd;
|
u16 rd;
|
||||||
|
|
||||||
rd = ath9k_regd_get_eepromRD(ah);
|
rd = ath9k_regd_get_eepromRD(ah);
|
||||||
|
|
||||||
@ -192,7 +193,7 @@ bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static struct country_code_to_enum_rd*
|
static struct country_code_to_enum_rd*
|
||||||
ath9k_regd_find_country(u_int16_t countryCode)
|
ath9k_regd_find_country(u16 countryCode)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
@ -203,15 +204,15 @@ ath9k_regd_find_country(u_int16_t countryCode)
|
|||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
static u_int16_t ath9k_regd_get_default_country(struct ath_hal *ah)
|
static u16 ath9k_regd_get_default_country(struct ath_hal *ah)
|
||||||
{
|
{
|
||||||
u_int16_t rd;
|
u16 rd;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
rd = ath9k_regd_get_eepromRD(ah);
|
rd = ath9k_regd_get_eepromRD(ah);
|
||||||
if (rd & COUNTRY_ERD_FLAG) {
|
if (rd & COUNTRY_ERD_FLAG) {
|
||||||
struct country_code_to_enum_rd *country = NULL;
|
struct country_code_to_enum_rd *country = NULL;
|
||||||
u_int16_t cc = rd & ~COUNTRY_ERD_FLAG;
|
u16 cc = rd & ~COUNTRY_ERD_FLAG;
|
||||||
|
|
||||||
country = ath9k_regd_find_country(cc);
|
country = ath9k_regd_find_country(cc);
|
||||||
if (country != NULL)
|
if (country != NULL)
|
||||||
@ -260,16 +261,16 @@ static bool ath9k_regd_is_valid_reg_domainPair(int regDmnPair)
|
|||||||
|
|
||||||
static bool
|
static bool
|
||||||
ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
|
ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
|
||||||
u_int16_t channelFlag, struct regDomain *rd)
|
u16 channelFlag, struct regDomain *rd)
|
||||||
{
|
{
|
||||||
int i, found;
|
int i, found;
|
||||||
u_int64_t flags = NO_REQ;
|
u64 flags = NO_REQ;
|
||||||
struct reg_dmn_pair_mapping *regPair = NULL;
|
struct reg_dmn_pair_mapping *regPair = NULL;
|
||||||
int regOrg;
|
int regOrg;
|
||||||
|
|
||||||
regOrg = regDmn;
|
regOrg = regDmn;
|
||||||
if (regDmn == CTRY_DEFAULT) {
|
if (regDmn == CTRY_DEFAULT) {
|
||||||
u_int16_t rdnum;
|
u16 rdnum;
|
||||||
rdnum = ath9k_regd_get_eepromRD(ah);
|
rdnum = ath9k_regd_get_eepromRD(ah);
|
||||||
|
|
||||||
if (!(rdnum & COUNTRY_ERD_FLAG)) {
|
if (!(rdnum & COUNTRY_ERD_FLAG)) {
|
||||||
@ -323,14 +324,14 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool ath9k_regd_is_bit_set(int bit, u_int64_t *bitmask)
|
static bool ath9k_regd_is_bit_set(int bit, u64 *bitmask)
|
||||||
{
|
{
|
||||||
int byteOffset, bitnum;
|
int byteOffset, bitnum;
|
||||||
u_int64_t val;
|
u64 val;
|
||||||
|
|
||||||
byteOffset = bit / 64;
|
byteOffset = bit / 64;
|
||||||
bitnum = bit - byteOffset * 64;
|
bitnum = bit - byteOffset * 64;
|
||||||
val = ((u_int64_t) 1) << bitnum;
|
val = ((u64) 1) << bitnum;
|
||||||
if (bitmask[byteOffset] & val)
|
if (bitmask[byteOffset] & val)
|
||||||
return true;
|
return true;
|
||||||
else
|
else
|
||||||
@ -338,8 +339,8 @@ static bool ath9k_regd_is_bit_set(int bit, u_int64_t *bitmask)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
ath9k_regd_add_reg_classid(u_int8_t *regclassids, u_int maxregids,
|
ath9k_regd_add_reg_classid(u8 *regclassids, u32 maxregids,
|
||||||
u_int *nregids, u_int8_t regclassid)
|
u32 *nregids, u8 regclassid)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
@ -372,7 +373,7 @@ ath9k_regd_get_eeprom_reg_ext_bits(struct ath_hal *ah,
|
|||||||
|
|
||||||
#ifdef ATH_NF_PER_CHAN
|
#ifdef ATH_NF_PER_CHAN
|
||||||
|
|
||||||
static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
|
static void ath9k_regd_init_rf_buffer(struct ath9k_channel *ichans,
|
||||||
int nchans)
|
int nchans)
|
||||||
{
|
{
|
||||||
int i, j, next;
|
int i, j, next;
|
||||||
@ -384,7 +385,7 @@ static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
|
|||||||
AR_PHY_CCA_MAX_GOOD_VALUE;
|
AR_PHY_CCA_MAX_GOOD_VALUE;
|
||||||
ichans[next].nfCalHist[i].invalidNFcount =
|
ichans[next].nfCalHist[i].invalidNFcount =
|
||||||
AR_PHY_CCA_FILTERWINDOW_LENGTH;
|
AR_PHY_CCA_FILTERWINDOW_LENGTH;
|
||||||
for (j = 0; j < HAL_NF_CAL_HIST_MAX; j++) {
|
for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
|
||||||
ichans[next].nfCalHist[i].nfCalBuffer[j] =
|
ichans[next].nfCalHist[i].nfCalBuffer[j] =
|
||||||
AR_PHY_CCA_MAX_GOOD_VALUE;
|
AR_PHY_CCA_MAX_GOOD_VALUE;
|
||||||
}
|
}
|
||||||
@ -393,22 +394,40 @@ static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
static int ath9k_regd_is_chan_present(struct ath_hal *ah,
|
||||||
|
u16 c)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < 150; i++) {
|
||||||
|
if (!ah->ah_channels[i].channel)
|
||||||
|
return -1;
|
||||||
|
else if (ah->ah_channels[i].channel == c)
|
||||||
|
return i;
|
||||||
|
}
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
static bool
|
static bool
|
||||||
ath9k_regd_add_channel(struct ath_hal *ah,
|
ath9k_regd_add_channel(struct ath_hal *ah,
|
||||||
u_int16_t c,
|
u16 c,
|
||||||
u_int16_t c_lo,
|
u16 c_lo,
|
||||||
u_int16_t c_hi,
|
u16 c_hi,
|
||||||
u_int16_t maxChan,
|
u16 maxChan,
|
||||||
u_int8_t ctl,
|
u8 ctl,
|
||||||
int pos,
|
int pos,
|
||||||
struct regDomain rd5GHz,
|
struct regDomain rd5GHz,
|
||||||
struct RegDmnFreqBand *fband,
|
struct RegDmnFreqBand *fband,
|
||||||
struct regDomain *rd,
|
struct regDomain *rd,
|
||||||
const struct cmode *cm,
|
const struct cmode *cm,
|
||||||
struct hal_channel_internal *ichans,
|
struct ath9k_channel *ichans,
|
||||||
bool enableExtendedChannels)
|
bool enableExtendedChannels)
|
||||||
{
|
{
|
||||||
struct hal_channel_internal icv;
|
struct ath9k_channel *chan;
|
||||||
|
int ret;
|
||||||
|
u32 channelFlags = 0;
|
||||||
|
u8 privFlags = 0;
|
||||||
|
|
||||||
if (!(c_lo <= c && c <= c_hi)) {
|
if (!(c_lo <= c && c <= c_hi)) {
|
||||||
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
|
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
|
||||||
@ -445,7 +464,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == HAL_M_HOSTAP)) {
|
if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == ATH9K_M_HOSTAP)) {
|
||||||
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
|
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
|
||||||
"Skipping HOSTAP channel\n");
|
"Skipping HOSTAP channel\n");
|
||||||
return false;
|
return false;
|
||||||
@ -478,54 +497,50 @@ ath9k_regd_add_channel(struct ath_hal *ah,
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
memset(&icv, 0, sizeof(icv));
|
/* Calculate channel flags */
|
||||||
icv.channel = c;
|
|
||||||
icv.channelFlags = cm->flags;
|
channelFlags = cm->flags;
|
||||||
|
|
||||||
switch (fband->channelBW) {
|
switch (fband->channelBW) {
|
||||||
case CHANNEL_HALF_BW:
|
case CHANNEL_HALF_BW:
|
||||||
icv.channelFlags |= CHANNEL_HALF;
|
channelFlags |= CHANNEL_HALF;
|
||||||
break;
|
break;
|
||||||
case CHANNEL_QUARTER_BW:
|
case CHANNEL_QUARTER_BW:
|
||||||
icv.channelFlags |= CHANNEL_QUARTER;
|
channelFlags |= CHANNEL_QUARTER;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
icv.maxRegTxPower = fband->powerDfs;
|
|
||||||
icv.antennaMax = fband->antennaMax;
|
|
||||||
icv.regDmnFlags = rd->flags;
|
|
||||||
icv.conformanceTestLimit = ctl;
|
|
||||||
if (fband->usePassScan & rd->pscan)
|
if (fband->usePassScan & rd->pscan)
|
||||||
icv.channelFlags |= CHANNEL_PASSIVE;
|
channelFlags |= CHANNEL_PASSIVE;
|
||||||
else
|
else
|
||||||
icv.channelFlags &= ~CHANNEL_PASSIVE;
|
channelFlags &= ~CHANNEL_PASSIVE;
|
||||||
if (fband->useDfs & rd->dfsMask)
|
if (fband->useDfs & rd->dfsMask)
|
||||||
icv.privFlags = CHANNEL_DFS;
|
privFlags = CHANNEL_DFS;
|
||||||
else
|
else
|
||||||
icv.privFlags = 0;
|
privFlags = 0;
|
||||||
if (rd->flags & LIMIT_FRAME_4MS)
|
if (rd->flags & LIMIT_FRAME_4MS)
|
||||||
icv.privFlags |= CHANNEL_4MS_LIMIT;
|
privFlags |= CHANNEL_4MS_LIMIT;
|
||||||
if (icv.privFlags & CHANNEL_DFS)
|
if (privFlags & CHANNEL_DFS)
|
||||||
icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
|
privFlags |= CHANNEL_DISALLOW_ADHOC;
|
||||||
if (icv.regDmnFlags & ADHOC_PER_11D)
|
if (rd->flags & ADHOC_PER_11D)
|
||||||
icv.privFlags |= CHANNEL_PER_11D_ADHOC;
|
privFlags |= CHANNEL_PER_11D_ADHOC;
|
||||||
|
|
||||||
if (icv.channelFlags & CHANNEL_PASSIVE) {
|
if (channelFlags & CHANNEL_PASSIVE) {
|
||||||
if ((icv.channel < 2412) || (icv.channel > 2462)) {
|
if ((c < 2412) || (c > 2462)) {
|
||||||
if (rd5GHz.regDmnEnum == MKK1 ||
|
if (rd5GHz.regDmnEnum == MKK1 ||
|
||||||
rd5GHz.regDmnEnum == MKK2) {
|
rd5GHz.regDmnEnum == MKK2) {
|
||||||
u_int32_t regcap = ah->ah_caps.halRegCap;
|
u32 regcap = ah->ah_caps.halRegCap;
|
||||||
if (!(regcap &
|
if (!(regcap &
|
||||||
(AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
|
(AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
|
||||||
AR_EEPROM_EEREGCAP_EN_KK_U2 |
|
AR_EEPROM_EEREGCAP_EN_KK_U2 |
|
||||||
AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) &&
|
AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) &&
|
||||||
isUNII1OddChan(icv.channel)) {
|
isUNII1OddChan(c)) {
|
||||||
icv.channelFlags &= ~CHANNEL_PASSIVE;
|
channelFlags &= ~CHANNEL_PASSIVE;
|
||||||
} else {
|
} else {
|
||||||
icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
|
privFlags |= CHANNEL_DISALLOW_ADHOC;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
|
privFlags |= CHANNEL_DISALLOW_ADHOC;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -534,14 +549,39 @@ ath9k_regd_add_channel(struct ath_hal *ah,
|
|||||||
ATH9K_MODE_SEL_11NA_HT20 |
|
ATH9K_MODE_SEL_11NA_HT20 |
|
||||||
ATH9K_MODE_SEL_11NA_HT40PLUS |
|
ATH9K_MODE_SEL_11NA_HT40PLUS |
|
||||||
ATH9K_MODE_SEL_11NA_HT40MINUS)) {
|
ATH9K_MODE_SEL_11NA_HT40MINUS)) {
|
||||||
if (icv.regDmnFlags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A))
|
if (rd->flags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A))
|
||||||
icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
|
privFlags |= CHANNEL_DISALLOW_ADHOC;
|
||||||
}
|
}
|
||||||
|
|
||||||
memcpy(&ichans[pos], &icv,
|
/* Fill in channel details */
|
||||||
sizeof(struct hal_channel_internal));
|
|
||||||
|
|
||||||
return true;
|
ret = ath9k_regd_is_chan_present(ah, c);
|
||||||
|
if (ret == -1) {
|
||||||
|
chan = &ah->ah_channels[pos];
|
||||||
|
chan->channel = c;
|
||||||
|
chan->maxRegTxPower = fband->powerDfs;
|
||||||
|
chan->antennaMax = fband->antennaMax;
|
||||||
|
chan->regDmnFlags = rd->flags;
|
||||||
|
chan->maxTxPower = AR5416_MAX_RATE_POWER;
|
||||||
|
chan->minTxPower = AR5416_MAX_RATE_POWER;
|
||||||
|
chan->channelFlags = channelFlags;
|
||||||
|
chan->privFlags = privFlags;
|
||||||
|
} else {
|
||||||
|
chan = &ah->ah_channels[ret];
|
||||||
|
chan->channelFlags |= channelFlags;
|
||||||
|
chan->privFlags |= privFlags;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set CTLs */
|
||||||
|
|
||||||
|
if ((cm->flags & CHANNEL_ALL) == CHANNEL_A)
|
||||||
|
chan->conformanceTestLimit[0] = ctl;
|
||||||
|
else if ((cm->flags & CHANNEL_ALL) == CHANNEL_B)
|
||||||
|
chan->conformanceTestLimit[1] = ctl;
|
||||||
|
else if ((cm->flags & CHANNEL_ALL) == CHANNEL_G)
|
||||||
|
chan->conformanceTestLimit[2] = ctl;
|
||||||
|
|
||||||
|
return (ret == -1) ? true : false;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool ath9k_regd_japan_check(struct ath_hal *ah,
|
static bool ath9k_regd_japan_check(struct ath_hal *ah,
|
||||||
@ -550,7 +590,7 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
|
|||||||
{
|
{
|
||||||
bool skipband = false;
|
bool skipband = false;
|
||||||
int i;
|
int i;
|
||||||
u_int32_t regcap;
|
u32 regcap;
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
|
for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
|
||||||
if (j_bandcheck[i].freqbandbit == b) {
|
if (j_bandcheck[i].freqbandbit == b) {
|
||||||
@ -575,22 +615,22 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
|
|||||||
|
|
||||||
bool
|
bool
|
||||||
ath9k_regd_init_channels(struct ath_hal *ah,
|
ath9k_regd_init_channels(struct ath_hal *ah,
|
||||||
struct hal_channel *chans, u_int maxchans,
|
u32 maxchans,
|
||||||
u_int *nchans, u_int8_t *regclassids,
|
u32 *nchans, u8 *regclassids,
|
||||||
u_int maxregids, u_int *nregids, u_int16_t cc,
|
u32 maxregids, u32 *nregids, u16 cc,
|
||||||
u_int32_t modeSelect, bool enableOutdoor,
|
u32 modeSelect, bool enableOutdoor,
|
||||||
bool enableExtendedChannels)
|
bool enableExtendedChannels)
|
||||||
{
|
{
|
||||||
u_int modesAvail;
|
u32 modesAvail;
|
||||||
u_int16_t maxChan = 7000;
|
u16 maxChan = 7000;
|
||||||
struct country_code_to_enum_rd *country = NULL;
|
struct country_code_to_enum_rd *country = NULL;
|
||||||
struct regDomain rd5GHz, rd2GHz;
|
struct regDomain rd5GHz, rd2GHz;
|
||||||
const struct cmode *cm;
|
const struct cmode *cm;
|
||||||
struct hal_channel_internal *ichans = &ah->ah_channels[0];
|
struct ath9k_channel *ichans = &ah->ah_channels[0];
|
||||||
int next = 0, b;
|
int next = 0, b;
|
||||||
u_int8_t ctl;
|
u8 ctl;
|
||||||
int regdmn;
|
int regdmn;
|
||||||
u_int16_t chanSep;
|
u16 chanSep;
|
||||||
|
|
||||||
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: cc %u mode 0x%x%s%s\n",
|
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: cc %u mode 0x%x%s%s\n",
|
||||||
__func__, cc, modeSelect,
|
__func__, cc, modeSelect,
|
||||||
@ -699,8 +739,8 @@ ath9k_regd_init_channels(struct ath_hal *ah,
|
|||||||
maxchans = ARRAY_SIZE(ah->ah_channels);
|
maxchans = ARRAY_SIZE(ah->ah_channels);
|
||||||
|
|
||||||
for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) {
|
for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) {
|
||||||
u_int16_t c, c_hi, c_lo;
|
u16 c, c_hi, c_lo;
|
||||||
u_int64_t *channelBM = NULL;
|
u64 *channelBM = NULL;
|
||||||
struct regDomain *rd = NULL;
|
struct regDomain *rd = NULL;
|
||||||
struct RegDmnFreqBand *fband = NULL, *freqs;
|
struct RegDmnFreqBand *fband = NULL, *freqs;
|
||||||
int8_t low_adj = 0, hi_adj = 0;
|
int8_t low_adj = 0, hi_adj = 0;
|
||||||
@ -843,26 +883,17 @@ done:
|
|||||||
ath9k_regd_init_rf_buffer(ichans, next);
|
ath9k_regd_init_rf_buffer(ichans, next);
|
||||||
#endif
|
#endif
|
||||||
ath9k_regd_sort(ichans, next,
|
ath9k_regd_sort(ichans, next,
|
||||||
sizeof(struct hal_channel_internal),
|
sizeof(struct ath9k_channel),
|
||||||
ath9k_regd_chansort);
|
ath9k_regd_chansort);
|
||||||
|
|
||||||
ah->ah_nchan = next;
|
ah->ah_nchan = next;
|
||||||
|
|
||||||
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Channel list:\n");
|
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Channel list:\n");
|
||||||
for (i = 0; i < next; i++) {
|
for (i = 0; i < next; i++) {
|
||||||
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
|
DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
|
||||||
"chan: %d flags: 0x%x\n",
|
"chan: %d flags: 0x%x\n",
|
||||||
ichans[i].channel,
|
ah->ah_channels[i].channel,
|
||||||
ichans[i].channelFlags);
|
ah->ah_channels[i].channelFlags);
|
||||||
chans[i].channel = ichans[i].channel;
|
|
||||||
chans[i].channelFlags = ichans[i].channelFlags;
|
|
||||||
chans[i].privFlags = ichans[i].privFlags;
|
|
||||||
chans[i].maxRegTxPower = ichans[i].maxRegTxPower;
|
|
||||||
}
|
|
||||||
|
|
||||||
ath9k_hw_get_chip_power_limits(ah, chans, next);
|
|
||||||
for (i = 0; i < next; i++) {
|
|
||||||
ichans[i].maxTxPower = chans[i].maxTxPower;
|
|
||||||
ichans[i].minTxPower = chans[i].minTxPower;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
*nchans = next;
|
*nchans = next;
|
||||||
@ -883,11 +914,11 @@ done:
|
|||||||
return next != 0;
|
return next != 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
struct hal_channel_internal*
|
struct ath9k_channel*
|
||||||
ath9k_regd_check_channel(struct ath_hal *ah,
|
ath9k_regd_check_channel(struct ath_hal *ah,
|
||||||
const struct hal_channel *c)
|
const struct ath9k_channel *c)
|
||||||
{
|
{
|
||||||
struct hal_channel_internal *base, *cc;
|
struct ath9k_channel *base, *cc;
|
||||||
|
|
||||||
int flags = c->channelFlags & CHAN_FLAGS;
|
int flags = c->channelFlags & CHAN_FLAGS;
|
||||||
int n, lim;
|
int n, lim;
|
||||||
@ -936,11 +967,11 @@ ath9k_regd_check_channel(struct ath_hal *ah,
|
|||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
u_int
|
u32
|
||||||
ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
|
ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
|
||||||
struct hal_channel *chan)
|
struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
struct hal_channel_internal *ichan = NULL;
|
struct ath9k_channel *ichan = NULL;
|
||||||
|
|
||||||
ichan = ath9k_regd_check_channel(ah, chan);
|
ichan = ath9k_regd_check_channel(ah, chan);
|
||||||
if (!ichan)
|
if (!ichan)
|
||||||
@ -949,10 +980,10 @@ ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
|
|||||||
return ichan->antennaMax;
|
return ichan->antennaMax;
|
||||||
}
|
}
|
||||||
|
|
||||||
u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan)
|
u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan)
|
||||||
{
|
{
|
||||||
u_int ctl = NO_CTL;
|
u32 ctl = NO_CTL;
|
||||||
struct hal_channel_internal *ichan;
|
struct ath9k_channel *ichan;
|
||||||
|
|
||||||
if (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) {
|
if (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) {
|
||||||
if (IS_CHAN_B(chan))
|
if (IS_CHAN_B(chan))
|
||||||
@ -964,9 +995,15 @@ u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan)
|
|||||||
} else {
|
} else {
|
||||||
ichan = ath9k_regd_check_channel(ah, chan);
|
ichan = ath9k_regd_check_channel(ah, chan);
|
||||||
if (ichan != NULL) {
|
if (ichan != NULL) {
|
||||||
ctl = ichan->conformanceTestLimit;
|
/* FIXME */
|
||||||
|
if (IS_CHAN_A(ichan))
|
||||||
|
ctl = ichan->conformanceTestLimit[0];
|
||||||
|
else if (IS_CHAN_B(ichan))
|
||||||
|
ctl = ichan->conformanceTestLimit[1];
|
||||||
|
else if (IS_CHAN_G(ichan))
|
||||||
|
ctl = ichan->conformanceTestLimit[2];
|
||||||
|
|
||||||
if (IS_CHAN_PUREG(chan) && (ctl & 0xf) == CTL_11B)
|
if (IS_CHAN_G(chan) && (ctl & 0xf) == CTL_11B)
|
||||||
ctl = (ctl & ~0xf) | CTL_11G;
|
ctl = (ctl & ~0xf) | CTL_11G;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -974,9 +1011,9 @@ u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan)
|
|||||||
}
|
}
|
||||||
|
|
||||||
void ath9k_regd_get_current_country(struct ath_hal *ah,
|
void ath9k_regd_get_current_country(struct ath_hal *ah,
|
||||||
struct hal_country_entry *ctry)
|
struct ath9k_country_entry *ctry)
|
||||||
{
|
{
|
||||||
u_int16_t rd = ath9k_regd_get_eepromRD(ah);
|
u16 rd = ath9k_regd_get_eepromRD(ah);
|
||||||
|
|
||||||
ctry->isMultidomain = false;
|
ctry->isMultidomain = false;
|
||||||
if (rd == CTRY_DEFAULT)
|
if (rd == CTRY_DEFAULT)
|
||||||
|
@ -20,57 +20,57 @@
|
|||||||
#include "ath9k.h"
|
#include "ath9k.h"
|
||||||
|
|
||||||
#define BMLEN 2
|
#define BMLEN 2
|
||||||
#define BMZERO {(u_int64_t) 0, (u_int64_t) 0}
|
#define BMZERO {(u64) 0, (u64) 0}
|
||||||
|
|
||||||
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
|
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
|
||||||
{((((_fa >= 0) && (_fa < 64)) ? \
|
{((((_fa >= 0) && (_fa < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fa) : (u_int64_t) 0) | \
|
(((u64) 1) << _fa) : (u64) 0) | \
|
||||||
(((_fb >= 0) && (_fb < 64)) ? \
|
(((_fb >= 0) && (_fb < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fb) : (u_int64_t) 0) | \
|
(((u64) 1) << _fb) : (u64) 0) | \
|
||||||
(((_fc >= 0) && (_fc < 64)) ? \
|
(((_fc >= 0) && (_fc < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fc) : (u_int64_t) 0) | \
|
(((u64) 1) << _fc) : (u64) 0) | \
|
||||||
(((_fd >= 0) && (_fd < 64)) ? \
|
(((_fd >= 0) && (_fd < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fd) : (u_int64_t) 0) | \
|
(((u64) 1) << _fd) : (u64) 0) | \
|
||||||
(((_fe >= 0) && (_fe < 64)) ? \
|
(((_fe >= 0) && (_fe < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fe) : (u_int64_t) 0) | \
|
(((u64) 1) << _fe) : (u64) 0) | \
|
||||||
(((_ff >= 0) && (_ff < 64)) ? \
|
(((_ff >= 0) && (_ff < 64)) ? \
|
||||||
(((u_int64_t) 1) << _ff) : (u_int64_t) 0) | \
|
(((u64) 1) << _ff) : (u64) 0) | \
|
||||||
(((_fg >= 0) && (_fg < 64)) ? \
|
(((_fg >= 0) && (_fg < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fg) : (u_int64_t) 0) | \
|
(((u64) 1) << _fg) : (u64) 0) | \
|
||||||
(((_fh >= 0) && (_fh < 64)) ? \
|
(((_fh >= 0) && (_fh < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fh) : (u_int64_t) 0) | \
|
(((u64) 1) << _fh) : (u64) 0) | \
|
||||||
(((_fi >= 0) && (_fi < 64)) ? \
|
(((_fi >= 0) && (_fi < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fi) : (u_int64_t) 0) | \
|
(((u64) 1) << _fi) : (u64) 0) | \
|
||||||
(((_fj >= 0) && (_fj < 64)) ? \
|
(((_fj >= 0) && (_fj < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fj) : (u_int64_t) 0) | \
|
(((u64) 1) << _fj) : (u64) 0) | \
|
||||||
(((_fk >= 0) && (_fk < 64)) ? \
|
(((_fk >= 0) && (_fk < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fk) : (u_int64_t) 0) | \
|
(((u64) 1) << _fk) : (u64) 0) | \
|
||||||
(((_fl >= 0) && (_fl < 64)) ? \
|
(((_fl >= 0) && (_fl < 64)) ? \
|
||||||
(((u_int64_t) 1) << _fl) : (u_int64_t) 0) | \
|
(((u64) 1) << _fl) : (u64) 0) | \
|
||||||
((((_fa > 63) && (_fa < 128)) ? \
|
((((_fa > 63) && (_fa < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fa - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fa - 64)) : (u64) 0) | \
|
||||||
(((_fb > 63) && (_fb < 128)) ? \
|
(((_fb > 63) && (_fb < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fb - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fb - 64)) : (u64) 0) | \
|
||||||
(((_fc > 63) && (_fc < 128)) ? \
|
(((_fc > 63) && (_fc < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fc - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fc - 64)) : (u64) 0) | \
|
||||||
(((_fd > 63) && (_fd < 128)) ? \
|
(((_fd > 63) && (_fd < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fd - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fd - 64)) : (u64) 0) | \
|
||||||
(((_fe > 63) && (_fe < 128)) ? \
|
(((_fe > 63) && (_fe < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fe - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fe - 64)) : (u64) 0) | \
|
||||||
(((_ff > 63) && (_ff < 128)) ? \
|
(((_ff > 63) && (_ff < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_ff - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_ff - 64)) : (u64) 0) | \
|
||||||
(((_fg > 63) && (_fg < 128)) ? \
|
(((_fg > 63) && (_fg < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fg - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fg - 64)) : (u64) 0) | \
|
||||||
(((_fh > 63) && (_fh < 128)) ? \
|
(((_fh > 63) && (_fh < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fh - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fh - 64)) : (u64) 0) | \
|
||||||
(((_fi > 63) && (_fi < 128)) ? \
|
(((_fi > 63) && (_fi < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fi - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fi - 64)) : (u64) 0) | \
|
||||||
(((_fj > 63) && (_fj < 128)) ? \
|
(((_fj > 63) && (_fj < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fj - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fj - 64)) : (u64) 0) | \
|
||||||
(((_fk > 63) && (_fk < 128)) ? \
|
(((_fk > 63) && (_fk < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fk - 64)) : (u_int64_t) 0) | \
|
(((u64) 1) << (_fk - 64)) : (u64) 0) | \
|
||||||
(((_fl > 63) && (_fl < 128)) ? \
|
(((_fl > 63) && (_fl < 128)) ? \
|
||||||
(((u_int64_t) 1) << (_fl - 64)) : (u_int64_t) 0)))}
|
(((u64) 1) << (_fl - 64)) : (u64) 0)))}
|
||||||
|
|
||||||
#define DEF_REGDMN FCC1_FCCA
|
#define DEF_REGDMN FCC1_FCCA
|
||||||
#define DEF_DMN_5 FCC1
|
#define DEF_DMN_5 FCC1
|
||||||
@ -126,10 +126,10 @@
|
|||||||
#define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
|
#define CHAN_FLAGS (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
|
||||||
|
|
||||||
#define swap(_a, _b, _size) { \
|
#define swap(_a, _b, _size) { \
|
||||||
u_int8_t *s = _b; \
|
u8 *s = _b; \
|
||||||
int i = _size; \
|
int i = _size; \
|
||||||
do { \
|
do { \
|
||||||
u_int8_t tmp = *_a; \
|
u8 tmp = *_a; \
|
||||||
*_a++ = *s; \
|
*_a++ = *s; \
|
||||||
*s++ = tmp; \
|
*s++ = tmp; \
|
||||||
} while (--i); \
|
} while (--i); \
|
||||||
@ -150,23 +150,23 @@
|
|||||||
typedef int ath_hal_cmp_t(const void *, const void *);
|
typedef int ath_hal_cmp_t(const void *, const void *);
|
||||||
|
|
||||||
struct reg_dmn_pair_mapping {
|
struct reg_dmn_pair_mapping {
|
||||||
u_int16_t regDmnEnum;
|
u16 regDmnEnum;
|
||||||
u_int16_t regDmn5GHz;
|
u16 regDmn5GHz;
|
||||||
u_int16_t regDmn2GHz;
|
u16 regDmn2GHz;
|
||||||
u_int32_t flags5GHz;
|
u32 flags5GHz;
|
||||||
u_int32_t flags2GHz;
|
u32 flags2GHz;
|
||||||
u_int64_t pscanMask;
|
u64 pscanMask;
|
||||||
u_int16_t singleCC;
|
u16 singleCC;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct ccmap {
|
struct ccmap {
|
||||||
char isoName[3];
|
char isoName[3];
|
||||||
u_int16_t countryCode;
|
u16 countryCode;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct country_code_to_enum_rd {
|
struct country_code_to_enum_rd {
|
||||||
u_int16_t countryCode;
|
u16 countryCode;
|
||||||
u_int16_t regDmnEnum;
|
u16 regDmnEnum;
|
||||||
const char *isoName;
|
const char *isoName;
|
||||||
const char *name;
|
const char *name;
|
||||||
bool allow11g;
|
bool allow11g;
|
||||||
@ -176,52 +176,52 @@ struct country_code_to_enum_rd {
|
|||||||
bool allow11ng40;
|
bool allow11ng40;
|
||||||
bool allow11na20;
|
bool allow11na20;
|
||||||
bool allow11na40;
|
bool allow11na40;
|
||||||
u_int16_t outdoorChanStart;
|
u16 outdoorChanStart;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct RegDmnFreqBand {
|
struct RegDmnFreqBand {
|
||||||
u_int16_t lowChannel;
|
u16 lowChannel;
|
||||||
u_int16_t highChannel;
|
u16 highChannel;
|
||||||
u_int8_t powerDfs;
|
u8 powerDfs;
|
||||||
u_int8_t antennaMax;
|
u8 antennaMax;
|
||||||
u_int8_t channelBW;
|
u8 channelBW;
|
||||||
u_int8_t channelSep;
|
u8 channelSep;
|
||||||
u_int64_t useDfs;
|
u64 useDfs;
|
||||||
u_int64_t usePassScan;
|
u64 usePassScan;
|
||||||
u_int8_t regClassId;
|
u8 regClassId;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct regDomain {
|
struct regDomain {
|
||||||
u_int16_t regDmnEnum;
|
u16 regDmnEnum;
|
||||||
u_int8_t conformanceTestLimit;
|
u8 conformanceTestLimit;
|
||||||
u_int64_t dfsMask;
|
u64 dfsMask;
|
||||||
u_int64_t pscan;
|
u64 pscan;
|
||||||
u_int32_t flags;
|
u32 flags;
|
||||||
u_int64_t chan11a[BMLEN];
|
u64 chan11a[BMLEN];
|
||||||
u_int64_t chan11a_turbo[BMLEN];
|
u64 chan11a_turbo[BMLEN];
|
||||||
u_int64_t chan11a_dyn_turbo[BMLEN];
|
u64 chan11a_dyn_turbo[BMLEN];
|
||||||
u_int64_t chan11b[BMLEN];
|
u64 chan11b[BMLEN];
|
||||||
u_int64_t chan11g[BMLEN];
|
u64 chan11g[BMLEN];
|
||||||
u_int64_t chan11g_turbo[BMLEN];
|
u64 chan11g_turbo[BMLEN];
|
||||||
};
|
};
|
||||||
|
|
||||||
struct cmode {
|
struct cmode {
|
||||||
u_int32_t mode;
|
u32 mode;
|
||||||
u_int32_t flags;
|
u32 flags;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define YES true
|
#define YES true
|
||||||
#define NO false
|
#define NO false
|
||||||
|
|
||||||
struct japan_bandcheck {
|
struct japan_bandcheck {
|
||||||
u_int16_t freqbandbit;
|
u16 freqbandbit;
|
||||||
u_int32_t eepromflagtocheck;
|
u32 eepromflagtocheck;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct common_mode_power {
|
struct common_mode_power {
|
||||||
u_int16_t lchan;
|
u16 lchan;
|
||||||
u_int16_t hchan;
|
u16 hchan;
|
||||||
u_int8_t pwrlvl;
|
u8 pwrlvl;
|
||||||
};
|
};
|
||||||
|
|
||||||
enum CountryCode {
|
enum CountryCode {
|
||||||
@ -407,6 +407,6 @@ enum CountryCode {
|
|||||||
};
|
};
|
||||||
|
|
||||||
void ath9k_regd_get_current_country(struct ath_hal *ah,
|
void ath9k_regd_get_current_country(struct ath_hal *ah,
|
||||||
struct hal_country_entry *ctry);
|
struct ath9k_country_entry *ctry);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -37,7 +37,7 @@
|
|||||||
|
|
||||||
#define OFDM_SIFS_TIME 16
|
#define OFDM_SIFS_TIME 16
|
||||||
|
|
||||||
static u_int32_t bits_per_symbol[][2] = {
|
static u32 bits_per_symbol[][2] = {
|
||||||
/* 20MHz 40MHz */
|
/* 20MHz 40MHz */
|
||||||
{ 26, 54 }, /* 0: BPSK */
|
{ 26, 54 }, /* 0: BPSK */
|
||||||
{ 52, 108 }, /* 1: QPSK 1/2 */
|
{ 52, 108 }, /* 1: QPSK 1/2 */
|
||||||
@ -180,7 +180,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc,
|
|||||||
|
|
||||||
/* Get transmit rate index using rate in Kbps */
|
/* Get transmit rate index using rate in Kbps */
|
||||||
|
|
||||||
static int ath_tx_findindex(const struct hal_rate_table *rt, int rate)
|
static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
int ndx = 0;
|
int ndx = 0;
|
||||||
@ -198,7 +198,7 @@ static int ath_tx_findindex(const struct hal_rate_table *rt, int rate)
|
|||||||
/* Check if it's okay to send out aggregates */
|
/* Check if it's okay to send out aggregates */
|
||||||
|
|
||||||
static int ath_aggr_query(struct ath_softc *sc,
|
static int ath_aggr_query(struct ath_softc *sc,
|
||||||
struct ath_node *an, u_int8_t tidno)
|
struct ath_node *an, u8 tidno)
|
||||||
{
|
{
|
||||||
struct ath_atx_tid *tid;
|
struct ath_atx_tid *tid;
|
||||||
tid = ATH_AN_2_TID(an, tidno);
|
tid = ATH_AN_2_TID(an, tidno);
|
||||||
@ -209,9 +209,9 @@ static int ath_aggr_query(struct ath_softc *sc,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static enum hal_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
|
static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
|
||||||
{
|
{
|
||||||
enum hal_pkt_type htype;
|
enum ath9k_pkt_type htype;
|
||||||
__le16 fc;
|
__le16 fc;
|
||||||
|
|
||||||
fc = hdr->frame_control;
|
fc = hdr->frame_control;
|
||||||
@ -219,15 +219,15 @@ static enum hal_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
|
|||||||
/* Calculate Atheros packet type from IEEE80211 packet header */
|
/* Calculate Atheros packet type from IEEE80211 packet header */
|
||||||
|
|
||||||
if (ieee80211_is_beacon(fc))
|
if (ieee80211_is_beacon(fc))
|
||||||
htype = HAL_PKT_TYPE_BEACON;
|
htype = ATH9K_PKT_TYPE_BEACON;
|
||||||
else if (ieee80211_is_probe_resp(fc))
|
else if (ieee80211_is_probe_resp(fc))
|
||||||
htype = HAL_PKT_TYPE_PROBE_RESP;
|
htype = ATH9K_PKT_TYPE_PROBE_RESP;
|
||||||
else if (ieee80211_is_atim(fc))
|
else if (ieee80211_is_atim(fc))
|
||||||
htype = HAL_PKT_TYPE_ATIM;
|
htype = ATH9K_PKT_TYPE_ATIM;
|
||||||
else if (ieee80211_is_pspoll(fc))
|
else if (ieee80211_is_pspoll(fc))
|
||||||
htype = HAL_PKT_TYPE_PSPOLL;
|
htype = ATH9K_PKT_TYPE_PSPOLL;
|
||||||
else
|
else
|
||||||
htype = HAL_PKT_TYPE_NORMAL;
|
htype = ATH9K_PKT_TYPE_NORMAL;
|
||||||
|
|
||||||
return htype;
|
return htype;
|
||||||
}
|
}
|
||||||
@ -248,7 +248,8 @@ static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
|
|||||||
txctl->min_rate = tx_info_priv->min_rate;
|
txctl->min_rate = tx_info_priv->min_rate;
|
||||||
} else if (ieee80211_is_data(fc)) {
|
} else if (ieee80211_is_data(fc)) {
|
||||||
if (ieee80211_is_nullfunc(fc) ||
|
if (ieee80211_is_nullfunc(fc) ||
|
||||||
(tx_info->flags & IEEE80211_TX_CTL_EAPOL_FRAME)) {
|
/* Port Access Entity (IEEE 802.1X) */
|
||||||
|
(skb->protocol == cpu_to_be16(0x888E))) {
|
||||||
txctl->use_minrate = 1;
|
txctl->use_minrate = 1;
|
||||||
txctl->min_rate = tx_info_priv->min_rate;
|
txctl->min_rate = tx_info_priv->min_rate;
|
||||||
}
|
}
|
||||||
@ -268,11 +269,11 @@ static int ath_tx_prepare(struct ath_softc *sc,
|
|||||||
struct ieee80211_hdr *hdr;
|
struct ieee80211_hdr *hdr;
|
||||||
struct ath_rc_series *rcs;
|
struct ath_rc_series *rcs;
|
||||||
struct ath_txq *txq = NULL;
|
struct ath_txq *txq = NULL;
|
||||||
const struct hal_rate_table *rt;
|
const struct ath9k_rate_table *rt;
|
||||||
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
|
||||||
struct ath_tx_info_priv *tx_info_priv;
|
struct ath_tx_info_priv *tx_info_priv;
|
||||||
int hdrlen;
|
int hdrlen;
|
||||||
u_int8_t rix, antenna;
|
u8 rix, antenna;
|
||||||
__le16 fc;
|
__le16 fc;
|
||||||
u8 *qc;
|
u8 *qc;
|
||||||
|
|
||||||
@ -307,19 +308,19 @@ static int ath_tx_prepare(struct ath_softc *sc,
|
|||||||
|
|
||||||
/* Fill Key related fields */
|
/* Fill Key related fields */
|
||||||
|
|
||||||
txctl->keytype = HAL_KEY_TYPE_CLEAR;
|
txctl->keytype = ATH9K_KEY_TYPE_CLEAR;
|
||||||
txctl->keyix = HAL_TXKEYIX_INVALID;
|
txctl->keyix = ATH9K_TXKEYIX_INVALID;
|
||||||
|
|
||||||
if (!(tx_info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
|
if (tx_info->control.hw_key) {
|
||||||
txctl->keyix = tx_info->control.hw_key->hw_key_idx;
|
txctl->keyix = tx_info->control.hw_key->hw_key_idx;
|
||||||
txctl->frmlen += tx_info->control.icv_len;
|
txctl->frmlen += tx_info->control.icv_len;
|
||||||
|
|
||||||
if (sc->sc_keytype == HAL_CIPHER_WEP)
|
if (sc->sc_keytype == ATH9K_CIPHER_WEP)
|
||||||
txctl->keytype = HAL_KEY_TYPE_WEP;
|
txctl->keytype = ATH9K_KEY_TYPE_WEP;
|
||||||
else if (sc->sc_keytype == HAL_CIPHER_TKIP)
|
else if (sc->sc_keytype == ATH9K_CIPHER_TKIP)
|
||||||
txctl->keytype = HAL_KEY_TYPE_TKIP;
|
txctl->keytype = ATH9K_KEY_TYPE_TKIP;
|
||||||
else if (sc->sc_keytype == HAL_CIPHER_AES_CCM)
|
else if (sc->sc_keytype == ATH9K_CIPHER_AES_CCM)
|
||||||
txctl->keytype = HAL_KEY_TYPE_AES;
|
txctl->keytype = ATH9K_KEY_TYPE_AES;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Fill packet type */
|
/* Fill packet type */
|
||||||
@ -353,12 +354,12 @@ static int ath_tx_prepare(struct ath_softc *sc,
|
|||||||
|
|
||||||
/* Fill flags */
|
/* Fill flags */
|
||||||
|
|
||||||
txctl->flags = HAL_TXDESC_CLRDMASK; /* needed for crypto errors */
|
txctl->flags = ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
|
||||||
|
|
||||||
if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
|
if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
|
||||||
tx_info->flags |= HAL_TXDESC_NOACK;
|
tx_info->flags |= ATH9K_TXDESC_NOACK;
|
||||||
if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
|
if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
|
||||||
tx_info->flags |= HAL_TXDESC_RTSENA;
|
tx_info->flags |= ATH9K_TXDESC_RTSENA;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Setup for rate calculations.
|
* Setup for rate calculations.
|
||||||
@ -373,7 +374,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
|
|||||||
(tx_info->flags & IEEE80211_TX_CTL_AMPDU));
|
(tx_info->flags & IEEE80211_TX_CTL_AMPDU));
|
||||||
|
|
||||||
if (is_multicast_ether_addr(hdr->addr1)) {
|
if (is_multicast_ether_addr(hdr->addr1)) {
|
||||||
rcs[0].rix = (u_int8_t)
|
rcs[0].rix = (u8)
|
||||||
ath_tx_findindex(rt, txctl->mcast_rate);
|
ath_tx_findindex(rt, txctl->mcast_rate);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -390,7 +391,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
|
|||||||
* not overridden, since it has been
|
* not overridden, since it has been
|
||||||
* incremented by the fragmentation routine.
|
* incremented by the fragmentation routine.
|
||||||
*/
|
*/
|
||||||
if (likely(!(txctl->flags & HAL_TXDESC_FRAG_IS_ON)) &&
|
if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) &&
|
||||||
txctl->ht && sc->sc_txaggr) {
|
txctl->ht && sc->sc_txaggr) {
|
||||||
struct ath_atx_tid *tid;
|
struct ath_atx_tid *tid;
|
||||||
|
|
||||||
@ -416,8 +417,8 @@ static int ath_tx_prepare(struct ath_softc *sc,
|
|||||||
* Calculate duration. This logically belongs in the 802.11
|
* Calculate duration. This logically belongs in the 802.11
|
||||||
* layer but it lacks sufficient information to calculate it.
|
* layer but it lacks sufficient information to calculate it.
|
||||||
*/
|
*/
|
||||||
if ((txctl->flags & HAL_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) {
|
if ((txctl->flags & ATH9K_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) {
|
||||||
u_int16_t dur;
|
u16 dur;
|
||||||
/*
|
/*
|
||||||
* XXX not right with fragmentation.
|
* XXX not right with fragmentation.
|
||||||
*/
|
*/
|
||||||
@ -475,7 +476,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
|
|||||||
*/
|
*/
|
||||||
spin_lock_bh(&txq->axq_lock);
|
spin_lock_bh(&txq->axq_lock);
|
||||||
if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
|
if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
|
||||||
txctl->flags |= HAL_TXDESC_INTREQ;
|
txctl->flags |= ATH9K_TXDESC_INTREQ;
|
||||||
txq->axq_intrcnt = 0;
|
txq->axq_intrcnt = 0;
|
||||||
}
|
}
|
||||||
spin_unlock_bh(&txq->axq_lock);
|
spin_unlock_bh(&txq->axq_lock);
|
||||||
@ -619,8 +620,8 @@ static int ath_tx_num_badfrms(struct ath_softc *sc,
|
|||||||
int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
|
int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
|
||||||
struct ath_buf *bf_last = bf->bf_lastbf;
|
struct ath_buf *bf_last = bf->bf_lastbf;
|
||||||
struct ath_desc *ds = bf_last->bf_desc;
|
struct ath_desc *ds = bf_last->bf_desc;
|
||||||
u_int16_t seq_st = 0;
|
u16 seq_st = 0;
|
||||||
u_int32_t ba[WME_BA_BMP_SIZE >> 5];
|
u32 ba[WME_BA_BMP_SIZE >> 5];
|
||||||
int ba_index;
|
int ba_index;
|
||||||
int nbad = 0;
|
int nbad = 0;
|
||||||
int isaggr = 0;
|
int isaggr = 0;
|
||||||
@ -685,16 +686,16 @@ static void ath_tx_update_baw(struct ath_softc *sc,
|
|||||||
* half_gi - to use 4us v/s 3.6 us for symbol time
|
* half_gi - to use 4us v/s 3.6 us for symbol time
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static u_int32_t ath_pkt_duration(struct ath_softc *sc,
|
static u32 ath_pkt_duration(struct ath_softc *sc,
|
||||||
u_int8_t rix,
|
u8 rix,
|
||||||
struct ath_buf *bf,
|
struct ath_buf *bf,
|
||||||
int width,
|
int width,
|
||||||
int half_gi,
|
int half_gi,
|
||||||
bool shortPreamble)
|
bool shortPreamble)
|
||||||
{
|
{
|
||||||
const struct hal_rate_table *rt = sc->sc_currates;
|
const struct ath9k_rate_table *rt = sc->sc_currates;
|
||||||
u_int32_t nbits, nsymbits, duration, nsymbols;
|
u32 nbits, nsymbits, duration, nsymbols;
|
||||||
u_int8_t rc;
|
u8 rc;
|
||||||
int streams, pktlen;
|
int streams, pktlen;
|
||||||
|
|
||||||
pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_frmlen;
|
pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_frmlen;
|
||||||
@ -734,14 +735,14 @@ static u_int32_t ath_pkt_duration(struct ath_softc *sc,
|
|||||||
static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
const struct hal_rate_table *rt;
|
const struct ath9k_rate_table *rt;
|
||||||
struct ath_desc *ds = bf->bf_desc;
|
struct ath_desc *ds = bf->bf_desc;
|
||||||
struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
|
struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
|
||||||
struct hal_11n_rate_series series[4];
|
struct ath9k_11n_rate_series series[4];
|
||||||
int i, flags, rtsctsena = 0, dynamic_mimops = 0;
|
int i, flags, rtsctsena = 0, dynamic_mimops = 0;
|
||||||
u_int ctsduration = 0;
|
u32 ctsduration = 0;
|
||||||
u_int8_t rix = 0, cix, ctsrate = 0;
|
u8 rix = 0, cix, ctsrate = 0;
|
||||||
u_int32_t aggr_limit_with_rts = sc->sc_rtsaggrlimit;
|
u32 aggr_limit_with_rts = sc->sc_rtsaggrlimit;
|
||||||
struct ath_node *an = (struct ath_node *) bf->bf_node;
|
struct ath_node *an = (struct ath_node *) bf->bf_node;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -754,7 +755,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
|
flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
|
||||||
cix = rt->info[rix].controlRate;
|
cix = rt->info[rix].controlRate;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -765,11 +766,11 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
if (sc->sc_protmode != PROT_M_NONE &&
|
if (sc->sc_protmode != PROT_M_NONE &&
|
||||||
(rt->info[rix].phy == PHY_OFDM ||
|
(rt->info[rix].phy == PHY_OFDM ||
|
||||||
rt->info[rix].phy == PHY_HT) &&
|
rt->info[rix].phy == PHY_HT) &&
|
||||||
(bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
|
(bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
|
||||||
if (sc->sc_protmode == PROT_M_RTSCTS)
|
if (sc->sc_protmode == PROT_M_RTSCTS)
|
||||||
flags = HAL_TXDESC_RTSENA;
|
flags = ATH9K_TXDESC_RTSENA;
|
||||||
else if (sc->sc_protmode == PROT_M_CTSONLY)
|
else if (sc->sc_protmode == PROT_M_CTSONLY)
|
||||||
flags = HAL_TXDESC_CTSENA;
|
flags = ATH9K_TXDESC_CTSENA;
|
||||||
|
|
||||||
cix = rt->info[sc->sc_protrix].controlRate;
|
cix = rt->info[sc->sc_protrix].controlRate;
|
||||||
rtsctsena = 1;
|
rtsctsena = 1;
|
||||||
@ -786,14 +787,14 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
* 802.11g protection not needed, use our default behavior
|
* 802.11g protection not needed, use our default behavior
|
||||||
*/
|
*/
|
||||||
if (!rtsctsena)
|
if (!rtsctsena)
|
||||||
flags = HAL_TXDESC_RTSENA;
|
flags = ATH9K_TXDESC_RTSENA;
|
||||||
/*
|
/*
|
||||||
* For dynamic MIMO PS, RTS needs to precede the first aggregate
|
* For dynamic MIMO PS, RTS needs to precede the first aggregate
|
||||||
* and the second aggregate should have any protection at all.
|
* and the second aggregate should have any protection at all.
|
||||||
*/
|
*/
|
||||||
if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
|
if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
|
||||||
if (!bf->bf_aggrburst) {
|
if (!bf->bf_aggrburst) {
|
||||||
flags = HAL_TXDESC_RTSENA;
|
flags = ATH9K_TXDESC_RTSENA;
|
||||||
dynamic_mimops = 1;
|
dynamic_mimops = 1;
|
||||||
} else {
|
} else {
|
||||||
flags = 0;
|
flags = 0;
|
||||||
@ -806,7 +807,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
*/
|
*/
|
||||||
if (sc->sc_config.ath_aggr_prot &&
|
if (sc->sc_config.ath_aggr_prot &&
|
||||||
(!bf->bf_isaggr || (bf->bf_isaggr && bf->bf_al < 8192))) {
|
(!bf->bf_isaggr || (bf->bf_isaggr && bf->bf_al < 8192))) {
|
||||||
flags = HAL_TXDESC_RTSENA;
|
flags = ATH9K_TXDESC_RTSENA;
|
||||||
cix = rt->info[sc->sc_protrix].controlRate;
|
cix = rt->info[sc->sc_protrix].controlRate;
|
||||||
rtsctsena = 1;
|
rtsctsena = 1;
|
||||||
}
|
}
|
||||||
@ -820,7 +821,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
* while we are bursting the second aggregate the
|
* while we are bursting the second aggregate the
|
||||||
* RTS is cleared.
|
* RTS is cleared.
|
||||||
*/
|
*/
|
||||||
flags &= ~(HAL_TXDESC_RTSENA);
|
flags &= ~(ATH9K_TXDESC_RTSENA);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -836,7 +837,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
/*
|
/*
|
||||||
* Setup HAL rate series
|
* Setup HAL rate series
|
||||||
*/
|
*/
|
||||||
memzero(series, sizeof(struct hal_11n_rate_series) * 4);
|
memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
|
||||||
|
|
||||||
for (i = 0; i < 4; i++) {
|
for (i = 0; i < 4; i++) {
|
||||||
if (!bf->bf_rcs[i].tries)
|
if (!bf->bf_rcs[i].tries)
|
||||||
@ -851,11 +852,11 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
|
|
||||||
series[i].RateFlags = (
|
series[i].RateFlags = (
|
||||||
(bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
|
(bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
|
||||||
HAL_RATESERIES_RTS_CTS : 0) |
|
ATH9K_RATESERIES_RTS_CTS : 0) |
|
||||||
((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
|
((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
|
||||||
HAL_RATESERIES_2040 : 0) |
|
ATH9K_RATESERIES_2040 : 0) |
|
||||||
((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
|
((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
|
||||||
HAL_RATESERIES_HALFGI : 0);
|
ATH9K_RATESERIES_HALFGI : 0);
|
||||||
|
|
||||||
series[i].PktDuration = ath_pkt_duration(
|
series[i].PktDuration = ath_pkt_duration(
|
||||||
sc, rix, bf,
|
sc, rix, bf,
|
||||||
@ -882,14 +883,14 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (rtsctsena)
|
if (rtsctsena)
|
||||||
series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
|
series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set RTS for all rates if node is in dynamic powersave
|
* Set RTS for all rates if node is in dynamic powersave
|
||||||
* mode and we are using dual stream rates.
|
* mode and we are using dual stream rates.
|
||||||
*/
|
*/
|
||||||
if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
|
if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
|
||||||
series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
|
series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -906,7 +907,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
* NB: CTS is assumed the same size as an ACK so we can
|
* NB: CTS is assumed the same size as an ACK so we can
|
||||||
* use the precalculated ACK durations.
|
* use the precalculated ACK durations.
|
||||||
*/
|
*/
|
||||||
if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */
|
if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */
|
||||||
ctsduration += bf->bf_shpreamble ?
|
ctsduration += bf->bf_shpreamble ?
|
||||||
rt->info[cix].spAckDuration :
|
rt->info[cix].spAckDuration :
|
||||||
rt->info[cix].lpAckDuration;
|
rt->info[cix].lpAckDuration;
|
||||||
@ -914,7 +915,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
|
|
||||||
ctsduration += series[0].PktDuration;
|
ctsduration += series[0].PktDuration;
|
||||||
|
|
||||||
if ((bf->bf_flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */
|
if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */
|
||||||
ctsduration += bf->bf_shpreamble ?
|
ctsduration += bf->bf_shpreamble ?
|
||||||
rt->info[rix].spAckDuration :
|
rt->info[rix].spAckDuration :
|
||||||
rt->info[rix].lpAckDuration;
|
rt->info[rix].lpAckDuration;
|
||||||
@ -924,7 +925,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
|
|||||||
* Disable multi-rate retry when using RTS/CTS by clearing
|
* Disable multi-rate retry when using RTS/CTS by clearing
|
||||||
* series 1, 2 and 3.
|
* series 1, 2 and 3.
|
||||||
*/
|
*/
|
||||||
memzero(&series[1], sizeof(struct hal_11n_rate_series) * 3);
|
memzero(&series[1], sizeof(struct ath9k_11n_rate_series) * 3);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -1019,8 +1020,8 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
|
|||||||
struct ath_desc *ds = bf_last->bf_desc;
|
struct ath_desc *ds = bf_last->bf_desc;
|
||||||
struct ath_buf *bf_next, *bf_lastq = NULL;
|
struct ath_buf *bf_next, *bf_lastq = NULL;
|
||||||
struct list_head bf_head, bf_pending;
|
struct list_head bf_head, bf_pending;
|
||||||
u_int16_t seq_st = 0;
|
u16 seq_st = 0;
|
||||||
u_int32_t ba[WME_BA_BMP_SIZE >> 5];
|
u32 ba[WME_BA_BMP_SIZE >> 5];
|
||||||
int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
|
int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
|
||||||
int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
|
int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
|
||||||
|
|
||||||
@ -1046,7 +1047,7 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
|
|||||||
* when perform internal reset in this routine.
|
* when perform internal reset in this routine.
|
||||||
* Only enable reset in STA mode for now.
|
* Only enable reset in STA mode for now.
|
||||||
*/
|
*/
|
||||||
if (sc->sc_opmode == HAL_M_STA)
|
if (sc->sc_opmode == ATH9K_M_STA)
|
||||||
needreset = 1;
|
needreset = 1;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
@ -1258,7 +1259,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
|
|||||||
struct ieee80211_tx_info *tx_info;
|
struct ieee80211_tx_info *tx_info;
|
||||||
struct ath_tx_info_priv *tx_info_priv;
|
struct ath_tx_info_priv *tx_info_priv;
|
||||||
int nacked, txok, nbad = 0, isrifs = 0;
|
int nacked, txok, nbad = 0, isrifs = 0;
|
||||||
enum hal_status status;
|
int status;
|
||||||
|
|
||||||
DPRINTF(sc, ATH_DBG_QUEUE,
|
DPRINTF(sc, ATH_DBG_QUEUE,
|
||||||
"%s: tx queue %d (%x), link %p\n", __func__,
|
"%s: tx queue %d (%x), link %p\n", __func__,
|
||||||
@ -1307,7 +1308,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
|
|||||||
ds = lastbf->bf_desc; /* NB: last decriptor */
|
ds = lastbf->bf_desc; /* NB: last decriptor */
|
||||||
|
|
||||||
status = ath9k_hw_txprocdesc(ah, ds);
|
status = ath9k_hw_txprocdesc(ah, ds);
|
||||||
if (status == HAL_EINPROGRESS) {
|
if (status == -EINPROGRESS) {
|
||||||
spin_unlock_bh(&txq->axq_lock);
|
spin_unlock_bh(&txq->axq_lock);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -1363,7 +1364,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
|
|||||||
if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
|
if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
|
||||||
tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
|
tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
|
||||||
if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
|
if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
|
||||||
(bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
|
(bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
|
||||||
if (ds->ds_txstat.ts_status == 0)
|
if (ds->ds_txstat.ts_status == 0)
|
||||||
nacked++;
|
nacked++;
|
||||||
|
|
||||||
@ -1429,11 +1430,11 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
|
|||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
int i;
|
int i;
|
||||||
int npend = 0;
|
int npend = 0;
|
||||||
enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
|
enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
|
||||||
|
|
||||||
/* XXX return value */
|
/* XXX return value */
|
||||||
if (!sc->sc_invalid) {
|
if (!sc->sc_invalid) {
|
||||||
for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
|
||||||
if (ATH_TXQ_SETUP(sc, i)) {
|
if (ATH_TXQ_SETUP(sc, i)) {
|
||||||
ath_tx_stopdma(sc, &sc->sc_txq[i]);
|
ath_tx_stopdma(sc, &sc->sc_txq[i]);
|
||||||
|
|
||||||
@ -1446,7 +1447,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (npend) {
|
if (npend) {
|
||||||
enum hal_status status;
|
int status;
|
||||||
|
|
||||||
/* TxDMA not stopped, reset the hal */
|
/* TxDMA not stopped, reset the hal */
|
||||||
DPRINTF(sc, ATH_DBG_XMIT,
|
DPRINTF(sc, ATH_DBG_XMIT,
|
||||||
@ -1466,7 +1467,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
|
|||||||
spin_unlock_bh(&sc->sc_resetlock);
|
spin_unlock_bh(&sc->sc_resetlock);
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
|
||||||
if (ATH_TXQ_SETUP(sc, i))
|
if (ATH_TXQ_SETUP(sc, i))
|
||||||
ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
|
ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
|
||||||
}
|
}
|
||||||
@ -1559,15 +1560,15 @@ static int ath_tx_send_ampdu(struct ath_softc *sc,
|
|||||||
* returns aggr limit based on lowest of the rates
|
* returns aggr limit based on lowest of the rates
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static u_int32_t ath_lookup_rate(struct ath_softc *sc,
|
static u32 ath_lookup_rate(struct ath_softc *sc,
|
||||||
struct ath_buf *bf)
|
struct ath_buf *bf)
|
||||||
{
|
{
|
||||||
const struct hal_rate_table *rt = sc->sc_currates;
|
const struct ath9k_rate_table *rt = sc->sc_currates;
|
||||||
struct sk_buff *skb;
|
struct sk_buff *skb;
|
||||||
struct ieee80211_tx_info *tx_info;
|
struct ieee80211_tx_info *tx_info;
|
||||||
struct ath_tx_info_priv *tx_info_priv;
|
struct ath_tx_info_priv *tx_info_priv;
|
||||||
u_int32_t max_4ms_framelen, frame_length;
|
u32 max_4ms_framelen, frame_length;
|
||||||
u_int16_t aggr_limit, legacy = 0, maxampdu;
|
u16 aggr_limit, legacy = 0, maxampdu;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
|
|
||||||
@ -1607,7 +1608,7 @@ static u_int32_t ath_lookup_rate(struct ath_softc *sc,
|
|||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
aggr_limit = min(max_4ms_framelen,
|
aggr_limit = min(max_4ms_framelen,
|
||||||
(u_int32_t)ATH_AMPDU_LIMIT_DEFAULT);
|
(u32)ATH_AMPDU_LIMIT_DEFAULT);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* h/w can accept aggregates upto 16 bit lengths (65535).
|
* h/w can accept aggregates upto 16 bit lengths (65535).
|
||||||
@ -1629,12 +1630,12 @@ static u_int32_t ath_lookup_rate(struct ath_softc *sc,
|
|||||||
|
|
||||||
static int ath_compute_num_delims(struct ath_softc *sc,
|
static int ath_compute_num_delims(struct ath_softc *sc,
|
||||||
struct ath_buf *bf,
|
struct ath_buf *bf,
|
||||||
u_int16_t frmlen)
|
u16 frmlen)
|
||||||
{
|
{
|
||||||
const struct hal_rate_table *rt = sc->sc_currates;
|
const struct ath9k_rate_table *rt = sc->sc_currates;
|
||||||
u_int32_t nsymbits, nsymbols, mpdudensity;
|
u32 nsymbits, nsymbols, mpdudensity;
|
||||||
u_int16_t minlen;
|
u16 minlen;
|
||||||
u_int8_t rc, flags, rix;
|
u8 rc, flags, rix;
|
||||||
int width, half_gi, ndelim, mindelim;
|
int width, half_gi, ndelim, mindelim;
|
||||||
|
|
||||||
/* Select standard number of delimiters based on frame length alone */
|
/* Select standard number of delimiters based on frame length alone */
|
||||||
@ -1646,7 +1647,7 @@ static int ath_compute_num_delims(struct ath_softc *sc,
|
|||||||
* TODO - this could be improved to be dependent on the rate.
|
* TODO - this could be improved to be dependent on the rate.
|
||||||
* The hardware can keep up at lower rates, but not higher rates
|
* The hardware can keep up at lower rates, but not higher rates
|
||||||
*/
|
*/
|
||||||
if (bf->bf_keytype != HAL_KEY_TYPE_CLEAR)
|
if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
|
||||||
ndelim += ATH_AGGR_ENCRYPTDELIM;
|
ndelim += ATH_AGGR_ENCRYPTDELIM;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -1707,7 +1708,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
|
|||||||
struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
|
struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
|
||||||
struct list_head bf_head;
|
struct list_head bf_head;
|
||||||
int rl = 0, nframes = 0, ndelim;
|
int rl = 0, nframes = 0, ndelim;
|
||||||
u_int16_t aggr_limit = 0, al = 0, bpad = 0,
|
u16 aggr_limit = 0, al = 0, bpad = 0,
|
||||||
al_delta, h_baw = tid->baw_size / 2;
|
al_delta, h_baw = tid->baw_size / 2;
|
||||||
enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
|
enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
|
||||||
int prev_al = 0, is_ds_rate = 0;
|
int prev_al = 0, is_ds_rate = 0;
|
||||||
@ -1981,7 +1982,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
|
|||||||
static int ath_tx_start_dma(struct ath_softc *sc,
|
static int ath_tx_start_dma(struct ath_softc *sc,
|
||||||
struct sk_buff *skb,
|
struct sk_buff *skb,
|
||||||
struct scatterlist *sg,
|
struct scatterlist *sg,
|
||||||
u_int32_t n_sg,
|
u32 n_sg,
|
||||||
struct ath_tx_control *txctl)
|
struct ath_tx_control *txctl)
|
||||||
{
|
{
|
||||||
struct ath_node *an = txctl->an;
|
struct ath_node *an = txctl->an;
|
||||||
@ -2047,7 +2048,7 @@ static int ath_tx_start_dma(struct ath_softc *sc,
|
|||||||
ds,
|
ds,
|
||||||
bf->bf_frmlen, /* frame length */
|
bf->bf_frmlen, /* frame length */
|
||||||
txctl->atype, /* Atheros packet type */
|
txctl->atype, /* Atheros packet type */
|
||||||
min(txctl->txpower, (u_int16_t)60), /* txpower */
|
min(txctl->txpower, (u16)60), /* txpower */
|
||||||
txctl->keyix, /* key cache index */
|
txctl->keyix, /* key cache index */
|
||||||
txctl->keytype, /* key type */
|
txctl->keytype, /* key type */
|
||||||
txctl->flags); /* flags */
|
txctl->flags); /* flags */
|
||||||
@ -2208,14 +2209,14 @@ int ath_tx_cleanup(struct ath_softc *sc)
|
|||||||
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
|
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
struct hal_txq_info qi;
|
struct ath9k_txq_info qi;
|
||||||
int qnum;
|
int qnum;
|
||||||
|
|
||||||
memzero(&qi, sizeof(qi));
|
memzero(&qi, sizeof(qi));
|
||||||
qi.tqi_subtype = subtype;
|
qi.tqi_subtype = subtype;
|
||||||
qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
|
qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
|
||||||
qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
|
qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
|
||||||
qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
|
qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
|
||||||
qi.tqi_compBuf = 0;
|
qi.tqi_compBuf = 0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -2233,7 +2234,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
|
|||||||
* The UAPSD queue is an exception, since we take a desc-
|
* The UAPSD queue is an exception, since we take a desc-
|
||||||
* based intr on the EOSP frames.
|
* based intr on the EOSP frames.
|
||||||
*/
|
*/
|
||||||
if (qtype == HAL_TX_QUEUE_UAPSD)
|
if (qtype == ATH9K_TX_QUEUE_UAPSD)
|
||||||
qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
|
qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
|
||||||
else
|
else
|
||||||
qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
|
qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
|
||||||
@ -2299,7 +2300,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
|
|||||||
__func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
|
__func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
|
txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
|
||||||
if (txq != NULL) {
|
if (txq != NULL) {
|
||||||
sc->sc_haltype2q[haltype] = txq->axq_qnum;
|
sc->sc_haltype2q[haltype] = txq->axq_qnum;
|
||||||
return 1;
|
return 1;
|
||||||
@ -2312,7 +2313,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
|
|||||||
int qnum;
|
int qnum;
|
||||||
|
|
||||||
switch (qtype) {
|
switch (qtype) {
|
||||||
case HAL_TX_QUEUE_DATA:
|
case ATH9K_TX_QUEUE_DATA:
|
||||||
if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
|
if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
|
||||||
DPRINTF(sc, ATH_DBG_FATAL,
|
DPRINTF(sc, ATH_DBG_FATAL,
|
||||||
"%s: HAL AC %u out of range, max %zu!\n",
|
"%s: HAL AC %u out of range, max %zu!\n",
|
||||||
@ -2322,10 +2323,10 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
|
|||||||
}
|
}
|
||||||
qnum = sc->sc_haltype2q[haltype];
|
qnum = sc->sc_haltype2q[haltype];
|
||||||
break;
|
break;
|
||||||
case HAL_TX_QUEUE_BEACON:
|
case ATH9K_TX_QUEUE_BEACON:
|
||||||
qnum = sc->sc_bhalq;
|
qnum = sc->sc_bhalq;
|
||||||
break;
|
break;
|
||||||
case HAL_TX_QUEUE_CAB:
|
case ATH9K_TX_QUEUE_CAB:
|
||||||
qnum = sc->sc_cabq->axq_qnum;
|
qnum = sc->sc_cabq->axq_qnum;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
@ -2336,11 +2337,11 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
|
|||||||
|
|
||||||
/* Update parameters for a transmit queue */
|
/* Update parameters for a transmit queue */
|
||||||
|
|
||||||
int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *qi0)
|
int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_txq_info *qi0)
|
||||||
{
|
{
|
||||||
struct ath_hal *ah = sc->sc_ah;
|
struct ath_hal *ah = sc->sc_ah;
|
||||||
int error = 0;
|
int error = 0;
|
||||||
struct hal_txq_info qi;
|
struct ath9k_txq_info qi;
|
||||||
|
|
||||||
if (qnum == sc->sc_bhalq) {
|
if (qnum == sc->sc_bhalq) {
|
||||||
/*
|
/*
|
||||||
@ -2375,7 +2376,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *qi0)
|
|||||||
|
|
||||||
int ath_cabq_update(struct ath_softc *sc)
|
int ath_cabq_update(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
struct hal_txq_info qi;
|
struct ath9k_txq_info qi;
|
||||||
int qnum = sc->sc_cabq->axq_qnum;
|
int qnum = sc->sc_cabq->axq_qnum;
|
||||||
struct ath_beacon_config conf;
|
struct ath_beacon_config conf;
|
||||||
|
|
||||||
@ -2383,10 +2384,10 @@ int ath_cabq_update(struct ath_softc *sc)
|
|||||||
/*
|
/*
|
||||||
* Ensure the readytime % is within the bounds.
|
* Ensure the readytime % is within the bounds.
|
||||||
*/
|
*/
|
||||||
if (sc->sc_config.cabqReadytime < HAL_READY_TIME_LO_BOUND)
|
if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
|
||||||
sc->sc_config.cabqReadytime = HAL_READY_TIME_LO_BOUND;
|
sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
|
||||||
else if (sc->sc_config.cabqReadytime > HAL_READY_TIME_HI_BOUND)
|
else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
|
||||||
sc->sc_config.cabqReadytime = HAL_READY_TIME_HI_BOUND;
|
sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
|
||||||
|
|
||||||
ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
|
ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
|
||||||
qi.tqi_readyTime =
|
qi.tqi_readyTime =
|
||||||
@ -2422,16 +2423,16 @@ int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
|
|||||||
|
|
||||||
void ath_tx_tasklet(struct ath_softc *sc)
|
void ath_tx_tasklet(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
u_int64_t tsf = ath9k_hw_gettsf64(sc->sc_ah);
|
u64 tsf = ath9k_hw_gettsf64(sc->sc_ah);
|
||||||
int i, nacked = 0;
|
int i, nacked = 0;
|
||||||
u_int32_t qcumask = ((1 << HAL_NUM_TX_QUEUES) - 1);
|
u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
|
||||||
|
|
||||||
ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
|
ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Process each active queue.
|
* Process each active queue.
|
||||||
*/
|
*/
|
||||||
for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
|
||||||
if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
|
if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
|
||||||
nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
|
nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
|
||||||
}
|
}
|
||||||
@ -2516,12 +2517,12 @@ void ath_draintxq(struct ath_softc *sc, bool retry_tx)
|
|||||||
ath_drain_txdataq(sc, retry_tx);
|
ath_drain_txdataq(sc, retry_tx);
|
||||||
}
|
}
|
||||||
|
|
||||||
u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum)
|
u32 ath_txq_depth(struct ath_softc *sc, int qnum)
|
||||||
{
|
{
|
||||||
return sc->sc_txq[qnum].axq_depth;
|
return sc->sc_txq[qnum].axq_depth;
|
||||||
}
|
}
|
||||||
|
|
||||||
u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
|
u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
|
||||||
{
|
{
|
||||||
return sc->sc_txq[qnum].axq_aggr_depth;
|
return sc->sc_txq[qnum].axq_aggr_depth;
|
||||||
}
|
}
|
||||||
@ -2620,7 +2621,7 @@ int ath_tx_aggr_stop(struct ath_softc *sc,
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
void ath_tx_aggr_teardown(struct ath_softc *sc,
|
void ath_tx_aggr_teardown(struct ath_softc *sc,
|
||||||
struct ath_node *an, u_int8_t tid)
|
struct ath_node *an, u8 tid)
|
||||||
{
|
{
|
||||||
struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
|
struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
|
||||||
struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
|
struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
|
||||||
@ -2784,19 +2785,19 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
|
|||||||
switch (acno) {
|
switch (acno) {
|
||||||
case WME_AC_BE:
|
case WME_AC_BE:
|
||||||
ac->qnum = ath_tx_get_qnum(sc,
|
ac->qnum = ath_tx_get_qnum(sc,
|
||||||
HAL_TX_QUEUE_DATA, HAL_WME_AC_BE);
|
ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
|
||||||
break;
|
break;
|
||||||
case WME_AC_BK:
|
case WME_AC_BK:
|
||||||
ac->qnum = ath_tx_get_qnum(sc,
|
ac->qnum = ath_tx_get_qnum(sc,
|
||||||
HAL_TX_QUEUE_DATA, HAL_WME_AC_BK);
|
ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
|
||||||
break;
|
break;
|
||||||
case WME_AC_VI:
|
case WME_AC_VI:
|
||||||
ac->qnum = ath_tx_get_qnum(sc,
|
ac->qnum = ath_tx_get_qnum(sc,
|
||||||
HAL_TX_QUEUE_DATA, HAL_WME_AC_VI);
|
ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
|
||||||
break;
|
break;
|
||||||
case WME_AC_VO:
|
case WME_AC_VO:
|
||||||
ac->qnum = ath_tx_get_qnum(sc,
|
ac->qnum = ath_tx_get_qnum(sc,
|
||||||
HAL_TX_QUEUE_DATA, HAL_WME_AC_VO);
|
ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -2812,7 +2813,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc,
|
|||||||
struct ath_atx_ac *ac, *ac_tmp;
|
struct ath_atx_ac *ac, *ac_tmp;
|
||||||
struct ath_atx_tid *tid, *tid_tmp;
|
struct ath_atx_tid *tid, *tid_tmp;
|
||||||
struct ath_txq *txq;
|
struct ath_txq *txq;
|
||||||
for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
|
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
|
||||||
if (ATH_TXQ_SETUP(sc, i)) {
|
if (ATH_TXQ_SETUP(sc, i)) {
|
||||||
txq = &sc->sc_txq[i];
|
txq = &sc->sc_txq[i];
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user