From a510aa32acf2db7519028511cc931319cfbe62c8 Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Fri, 29 Oct 2010 11:53:42 +0800 Subject: [PATCH] [uboot-xburst] move lcd init more early Signed-off-by: Xiangfu Liu --- .../files/drivers/video/nanonote_gpm940b0.c | 4 -- .../files/drivers/video/nanonote_gpm940b0.h | 10 +--- .../nand_spl/board/xburst/nanonote/Makefile | 9 +--- .../files/nand_spl/nand_boot_jz4740.c | 53 +++++++------------ 4 files changed, 23 insertions(+), 53 deletions(-) diff --git a/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c b/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c index 203bebecc..dc0b363de 100644 --- a/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c +++ b/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c @@ -78,13 +78,9 @@ extern int flush_cache_all(void); void lcd_ctrl_init (void *lcdbase) { - __lcd_display_pin_init(); - jz_lcd_init_mem(lcdbase, &panel_info); jz_lcd_desc_init(&panel_info); jz_lcd_hw_init(&panel_info); - - __lcd_display_on() ; } /* diff --git a/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h b/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h index 7cafaa496..efe491edb 100644 --- a/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h +++ b/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h @@ -22,8 +22,6 @@ #ifndef __QI_LB60_GPM940B0_H__ #define __QI_LB60_GPM940B0_H__ -#include - struct lcd_desc{ unsigned int next_desc; /* LCDDAx */ unsigned int databuf; /* LCDSAx */ @@ -98,7 +96,6 @@ do { \ __gpio_set_pin(SPCK); \ __gpio_clear_pin(SPDA); \ __gpio_clear_pin(SPEN); \ - udelay(25); \ value=((a<<8)|(b&0xFF)); \ for(no=0;no<16;no++) \ { \ @@ -107,13 +104,10 @@ do { \ __gpio_set_pin(SPDA); \ else \ __gpio_clear_pin(SPDA); \ - udelay(25); \ __gpio_set_pin(SPCK); \ value=(value<<1); \ - udelay(25); \ } \ __gpio_set_pin(SPEN); \ - udelay(100); \ } while (0) #define __lcd_display_pin_init() \ @@ -127,10 +121,10 @@ do { \ #define __lcd_display_on() \ do { \ __spi_write_reg1(0x05, 0x1e); \ - __spi_write_reg1(0x05, 0xc6); \ + __spi_write_reg1(0x05, 0x5e); \ __spi_write_reg1(0x07, 0x8d); \ __spi_write_reg1(0x13, 0x01); \ - __spi_write_reg1(0x05, 0xc7); \ + __spi_write_reg1(0x05, 0x5f); \ } while (0) #define __lcd_display_off() \ diff --git a/package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile b/package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile index 6034293be..18dc13903 100644 --- a/package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile +++ b/package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile @@ -61,8 +61,6 @@ $(nandobj)u-boot-spl: $(OBJS) -o $(nandobj)u-boot-spl # create symbolic links for common files - -# from cpu directory $(obj)start.S: @rm -f $(obj)start.S ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S @@ -83,12 +81,10 @@ $(obj)jz_serial.c: @rm -f $(obj)jz_serial.c ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c -# from nand_spl directory $(obj)nand_boot_jz4740.c: @rm -f $(obj)nand_boot_jz4740.c ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c - -######################################################################### + ln -s $(SRCTREE)/drivers/video/nanonote_gpm940b0.h $(obj)nanonote_gpm940b0.h $(obj)%.o: $(obj)%.S $(CC) $(AFLAGS) -c -o $@ $< @@ -96,9 +92,6 @@ $(obj)%.o: $(obj)%.S $(obj)%.o: $(obj)%.c $(CC) $(CFLAGS) -c -o $@ $< -# defines $(obj).depend target include $(SRCTREE)/rules.mk sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c b/package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c index 64cac97fe..e4ac486f2 100644 --- a/package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c +++ b/package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c @@ -21,8 +21,8 @@ #include #include -#include #include +#include "nanonote_gpm940b0.h" #define KEY_U_OUT (32 * 2 + 16) #define KEY_U_IN (32 * 3 + 19) @@ -30,15 +30,10 @@ /* * NAND flash definitions */ - #define NAND_DATAPORT 0xb8000000 #define NAND_ADDRPORT 0xb8010000 #define NAND_COMMPORT 0xb8008000 -#define ECC_BLOCK 512 -#define ECC_POS 6 -#define PAR_SIZE 9 - #define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1) #define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1)) #define __nand_ecc_rs_encoding() \ @@ -48,14 +43,6 @@ #define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) #define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) #define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) - -static inline void __nand_dev_ready(void) -{ - unsigned int timeout = 10000; - while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--); - while (!(REG_GPIO_PXPIN(2) & 0x40000000)); -} - #define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n)) #define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) #define __nand_data8() REG8(NAND_DATAPORT) @@ -75,6 +62,13 @@ static inline void __nand_dev_ready(void) #define NAND_ROW_CYCLE 2 #endif +static inline void __nand_dev_ready(void) +{ + unsigned int timeout = 10000; + while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--); + while (!(REG_GPIO_PXPIN(2) & 0x40000000)); +} + /* * NAND flash parameters */ @@ -84,7 +78,6 @@ static int ecc_count = 4; static int page_per_block = 64; static int bad_block_pos = 0; static int block_size = 131072; - static unsigned char oob_buf[128] = {0}; /* @@ -198,7 +191,6 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf) /* * Read page data */ - /* Send READ0 command */ __nand_cmd(NAND_CMD_READ0); @@ -233,16 +225,11 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf) __nand_ecc_rs_decoding(); /* Read data */ - nand_read_buf((void *)tmpbuf, ECC_BLOCK); + nand_read_buf((void *)tmpbuf, CONFIG_SYS_NAND_ECCSIZE); /* Set PAR values */ - for (j = 0; j < PAR_SIZE; j++) { -#if defined(CONFIG_SYS_NAND_ECC_POS) - *paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j]; -#else - *paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j]; -#endif - } + for (j = 0; j < CONFIG_SYS_NAND_ECCBYTES; j++) + *paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*CONFIG_SYS_NAND_ECCBYTES + j]; /* Set PRDY */ REG_EMC_NFECR |= EMC_NFECR_PRDY; @@ -257,12 +244,11 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf) stat = REG_EMC_NFINTS; if (stat & EMC_NFINTS_ERR) { /* Error occurred */ - /* serial_puts("\n Error occurred\n"); */ + /* serial_puts("Error occurred\n"); */ if (stat & EMC_NFINTS_UNCOR) { /* Uncorrectable error occurred */ - /* serial_puts("\nUncorrectable error occurred\n"); */ - } - else { + /* serial_puts("Uncorrectable error occurred\n"); */ + } else { unsigned int errcnt, index, mask; errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; @@ -292,8 +278,7 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf) } } } - - tmpbuf += ECC_BLOCK; + tmpbuf += CONFIG_SYS_NAND_ECCSIZE; } return 0; @@ -342,13 +327,12 @@ static void gpio_init(void) /* * Initialize SDRAM pins */ - __gpio_as_sdram_32bit(); + __gpio_as_sdram_16bit_4720(); /* * Initialize UART0 pins */ __gpio_as_uart0(); - __gpio_jtag_to_uart0(); } @@ -375,6 +359,9 @@ void nand_boot(void) gpio_init(); pll_init(); + __lcd_display_pin_init(); + __lcd_display_on() ; + serial_init(); sdram_init(); jz_nand_init(); @@ -392,7 +379,7 @@ void nand_boot(void) page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE; bad_block_pos = (page_size == 512) ? 5 : 0; oob_size = page_size / 32; - ecc_count = page_size / ECC_BLOCK; + ecc_count = page_size / CONFIG_SYS_NAND_ECCSIZE; /* * Load U-Boot image from NAND into RAM