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fix compile errors due to API changes

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This commit is contained in:
Marek Lindner 2009-07-04 16:23:51 +08:00 committed by Xiangfu Liu
parent 28779100a8
commit a59fa712ba
1 changed files with 7 additions and 7 deletions
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14
target/linux/xburst/patches-2.6.28/100-arch.patch
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@ -180,7 +180,7 @@
+# Commond Ingenic JZ4730 series +# Commond Ingenic JZ4730 series
+# +#
+core-$(CONFIG_SOC_JZ4730) += arch/mips/jz4730/ +core-$(CONFIG_SOC_JZ4730) += arch/mips/jz4730/
+cflags-$(CONFIG_SOC_JZ4730) += -Iinclude/asm-mips/mach-jz4730 +cflags-$(CONFIG_SOC_JZ4730) += -Iarch/mips/include/asm/mach-jz4730
+load-$(CONFIG_SOC_JZ4730) += 0xffffffff80010000 +load-$(CONFIG_SOC_JZ4730) += 0xffffffff80010000
+ +
+# +#
@ -188,7 +188,7 @@
+# +#
+ +
+core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/ +core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/
+cflags-$(CONFIG_SOC_JZ4740) += -Iinclude/asm-mips/mach-jz4740 +cflags-$(CONFIG_SOC_JZ4740) += -Iarch/mips/include/asm/mach-jz4740
+load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000 +load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000
+ +
+# +#
@ -196,7 +196,7 @@
+# +#
+ +
+core-$(CONFIG_SOC_JZ4750) += arch/mips/jz4750/ +core-$(CONFIG_SOC_JZ4750) += arch/mips/jz4750/
+cflags-$(CONFIG_SOC_JZ4750) += -Iinclude/asm-mips/mach-jz4750 +cflags-$(CONFIG_SOC_JZ4750) += -Iarch/mips/include/asm/mach-jz4750
+load-$(CONFIG_SOC_JZ4750) += 0xffffffff80010000 +load-$(CONFIG_SOC_JZ4750) += 0xffffffff80010000
+ +
+# +#
@ -204,7 +204,7 @@
+# +#
+ +
+core-$(CONFIG_SOC_JZ4750D) += arch/mips/jz4750d/ +core-$(CONFIG_SOC_JZ4750D) += arch/mips/jz4750d/
+cflags-$(CONFIG_SOC_JZ4750D) += -Iinclude/asm-mips/mach-jz4750d +cflags-$(CONFIG_SOC_JZ4750D) += -Iarch/mips/include/asm/mach-jz4750d
+load-$(CONFIG_SOC_JZ4750D) += 0xffffffff80010000 +load-$(CONFIG_SOC_JZ4750D) += 0xffffffff80010000
+ +
+# +#
@ -28743,7 +28743,7 @@
} }
} }
+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c) +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
+{ +{
+ decode_configs(c); + decode_configs(c);
+ c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */ + c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */
@ -28768,7 +28768,7 @@
cpu_probe_nxp(c, cpu); cpu_probe_nxp(c, cpu);
break; break;
+ case PRID_COMP_INGENIC: + case PRID_COMP_INGENIC:
+ cpu_probe_ingenic(c); + cpu_probe_ingenic(c, cpu);
+ break; + break;
} }
@ -28831,7 +28831,7 @@
+ case CPU_JZRISC: + case CPU_JZRISC:
+ tlbw(p); + tlbw(p);
+ i_nop(p); + uasm_i_nop(p);
+ break; + break;
+ +
default: default: