qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-12-26 02:55:32 +02:00
Code

[brcm63xx] fix some SPI register definitions and platform-device registration code

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14787 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian 2009-03-08 12:13:52 +00:00
parent 128eb3aeef
commit a5c53df418
4 changed files with 26 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
target/linux/brcm63xx/files/arch/mips/bcm63xx/dev-spi.c
View File

@ -9,8 +9,10 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <bcm63xx_cpu.h> #include <bcm63xx_cpu.h>
#include <bcm63xx_dev_spi.h> #include <bcm63xx_dev_spi.h>
#include <bcm63xx_regs.h>
static struct resource spi_resources[] = { static struct resource spi_resources[] = {
{ {
@ -35,7 +37,9 @@ static struct platform_device bcm63xx_spi_device = {
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(spi_resources), .num_resources = ARRAY_SIZE(spi_resources),
.resource = spi_resources, .resource = spi_resources,
.dev.pdata = &spi_pdata; .dev = {
.platform_data = &spi_pdata,
},
}; };
int __init bcm63xx_spi_register(void) int __init bcm63xx_spi_register(void)
@ -46,12 +50,12 @@ int __init bcm63xx_spi_register(void)
spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI); spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
/* Fill in platform data */ /* Fill in platform data */
if (CPU_IS_BCM6338() || CPU_IS_BCM6348()) { if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
spi_pdata.msg_fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE; spi_pdata.msg_fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
spi_pdata.rx_fifo_size = SPI_BCM_6338_SPI_RX_DATA_SIZE; spi_pdata.rx_fifo_size = SPI_BCM_6338_SPI_RX_DATA_SIZE;
} }
if (CPU_IS_BCM6358()) { if (BCMCPU_IS_6358()) {
spi_pdata.msg_fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE; spi_pdata.msg_fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
spi_pdata.rx_fifo_size = SPI_BCM_6358_SPI_RX_DATA_SIZE; spi_pdata.rx_fifo_size = SPI_BCM_6358_SPI_RX_DATA_SIZE;
} }

2
target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
View File

@ -396,7 +396,7 @@ switch (reg) {
case SPI_MSG_DATA: case SPI_MSG_DATA:
return SPI_BCM_6358_SPI_MSG_DATA; return SPI_BCM_6358_SPI_MSG_DATA;
case SPI_RX_DATA: case SPI_RX_DATA:
return SPI_BCM_6358_SPI_RX_FIFO; return SPI_BCM_6358_SPI_RX_DATA;
} }
#endif #endif
#endif #endif

2
target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_dev_spi.h
View File

@ -3,7 +3,7 @@
#include <linux/types.h> #include <linux/types.h>
int bcm63xx_spi_register(void); int __init bcm63xx_spi_register(void);
struct bcm63xx_spi_pdata { struct bcm63xx_spi_pdata {
unsigned int msg_fifo_size; unsigned int msg_fifo_size;

32
target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
View File

@ -794,8 +794,8 @@
#define SPI_BCM_6358_SPI_MSG_DATA 0x02 #define SPI_BCM_6358_SPI_MSG_DATA 0x02
#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e #define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
#define SPI_BCM_6358_SPI_RX_FIFO 0x400 #define SPI_BCM_6358_SPI_RX_DATA 0x400
#define SPI_BCM_6358_SPI_RX_FIFO_SIZE 0x220 #define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */ #define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
@ -815,17 +815,17 @@
/* Shared SPI definitions */ /* Shared SPI definitions */
/* Message configuration */ /* Message configuration */
#define SPI_FD_RW 0 #define SPI_FD_RW 0x00
#define SPI_HD_W 1 #define SPI_HD_W 0x01
#define SPI_HD_R 2 #define SPI_HD_R 0x02
#define SPI_BYTE_CNT_SHIFT 0 #define SPI_BYTE_CNT_SHIFT 0
#define SPI_MSG_TYPE_SHIFT 14 #define SPI_MSG_TYPE_SHIFT 14
/* Command */ /* Command */
#define SPI_CMD_NOOP 0 #define SPI_CMD_NOOP 0x01
#define SPI_CMD_SOFT_RESET 1 #define SPI_CMD_SOFT_RESET 0x02
#define SPI_CMD_HARD_RESET 2 #define SPI_CMD_HARD_RESET 0x04
#define SPI_CMD_START_IMMEDIATE 3 #define SPI_CMD_START_IMMEDIATE 0x08
#define SPI_CMD_COMMAND_SHIFT 0 #define SPI_CMD_COMMAND_SHIFT 0
#define SPI_CMD_COMMAND_MASK 0x000f #define SPI_CMD_COMMAND_MASK 0x000f
#define SPI_CMD_DEVICE_ID_SHIFT 4 #define SPI_CMD_DEVICE_ID_SHIFT 4
@ -851,12 +851,14 @@
#define SPI_SERIAL_BUSY 0x08 #define SPI_SERIAL_BUSY 0x08
/* Clock configuration */ /* Clock configuration */
#define SPI_CLK_0_391MHZ 1 #define SPI_CLK_20MHZ 0x00
#define SPI_CLK_0_781MHZ 2 /* default */ #define SPI_CLK_0_391MHZ 0x01
#define SPI_CLK_1_563MHZ 3 #define SPI_CLK_0_781MHZ 0x02 /* default */
#define SPI_CLK_3_125MHZ 4 #define SPI_CLK_1_563MHZ 0x03
#define SPI_CLK_6_250MHZ 5 #define SPI_CLK_3_125MHZ 0x04
#define SPI_CLK_12_50MHZ 6 #define SPI_CLK_6_250MHZ 0x05
#define SPI_CLK_12_50MHZ 0x06
#define SPI_CLK_25MHZ 0x07
#define SPI_CLK_MASK 0x07 #define SPI_CLK_MASK 0x07
#define SPI_SSOFFTIME_MASK 0x38 #define SPI_SSOFFTIME_MASK 0x38
#define SPI_SSOFFTIME_SHIFT 3 #define SPI_SSOFFTIME_SHIFT 3