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git://projects.qi-hardware.com/openwrt-xburst.git
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uboot: provide a working usbboot mode
This commit is contained in:
Lars-Peter Clausen
parent
592aaa1ba6
commit
a6402204c8
@ -7206,7 +7206,7 @@ new file mode 100644
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index 0000000..6c3788f
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--- /dev/null
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+++ b/cpu/mips/usb_boot.S
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@@ -0,0 +1,821 @@
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@@ -0,0 +1,880 @@
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+/*
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+ * for jz4740 usb boot
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+ *
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@ -7240,6 +7240,65 @@ index 0000000..6c3788f
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+// So init caches first and then dispatch to a proper boot routine.
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+//----------------------------------------------------------------------
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+
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+.macro load_addr reg addr
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+ li \reg, 0x80000000
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+ addiu \reg, \reg, \addr
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+ la $2, usbboot_begin
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+ subu \reg, \reg, $2
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+.endm
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+
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+usb_boot:
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+ //--------------------------------------------------------------
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+ // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
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+ //--------------------------------------------------------------
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+ la $9, 0xB0000000 // CPCCR: Clock Control Register
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+ la $8, 0x42041110 // I:S:M:P=1:2:2:2
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+ sw $8, 0($9)
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+
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+ la $9, 0xB0000010 // CPPCR: PLL Control Register
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+ la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
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+ sw $8, 0($9)
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+
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+ mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
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+ nop
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+
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+ mtc0 $0, $16 // CP0_CONFIG
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+ nop
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+
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+ // Relocate code to beginning of the ram
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+
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+ la $2, usbboot_begin
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+ la $3, usbboot_end
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+ li $4, 0x80000000
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+
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+1:
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+ lw $5, 0($2)
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+ sw $5, 0($4)
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+ addiu $2, $2, 4
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+ bne $2, $3, 1b
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+ addiu $4, $4, 4
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+
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+ li $2, 0x80000000
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+ ori $3, $2, 0
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+ addiu $3, $3, usbboot_end
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+ la $4, usbboot_begin
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+ subu $3, $3, $4
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+
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+
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+2:
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+ cache 0x0, 0($2) // Index_Invalidate_I
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+ cache 0x1, 0($2) // Index_Writeback_Inv_D
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+ addiu $2, $2, 32
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+ subu $4, $3, $2
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+ bgtz $4, 2b
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+ nop
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+
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+ load_addr $3, usb_boot_return
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+
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+ jr $3
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+
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+usbboot_begin:
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+
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+init_caches:
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+ li $2, 3 // cacheable for kseg0 access
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+ mtc0 $2, $16 // CP0_CONFIG
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@ -7282,20 +7341,31 @@ index 0000000..6c3788f
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+ // $20: jump target address
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+ //--------------------------------------------------------------
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+xfer_d2i:
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+ ori $2, $28, 0 // start address
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+ add $3, $2, $19 // end addres
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+ addiu $3, $3, -4
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+
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+xfer_a_word:
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+ lw $4, 0($2)
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+ mtc0 $4, $28, 1 // CP0_DATALO
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+ cache 0xc, 0($2) // Index_Store_Data_I
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+ bne $2, $3, xfer_a_word
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+ addiu $2, $2, 4
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+ ori $8, $20, 0
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+ addu $9, $8, $19 // total 16KB
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+
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+ mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
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+1:
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+ cache 0x0, 0($8) // Index_Invalidate_I
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+ cache 0x1, 0($8) // Index_Writeback_Inv_D
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+ bne $8, $9, 1b
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+ addiu $8, $8, 32
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+
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+ jalr $20 // jump, and place the return address in $31
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+ // flush write-buffer
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+ sync
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+
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+ // Invalidate BTB
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+ mfc0 $8, $16, 7 // CP0_CONFIG
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+ nop
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+ ori $8, 2
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+ mtc0 $8, $16, 7
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+ nop
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+
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+ // Overwrite config to disable ram initalisation
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+ li $2, 0xff
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+ sb $2, 20($20)
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+
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+ jalr $20
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+ nop
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+
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+icache_return:
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@ -7307,18 +7377,6 @@ index 0000000..6c3788f
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+ nop
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+
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+
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+usb_boot:
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+ //--------------------------------------------------------------
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+ // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
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+ //--------------------------------------------------------------
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+ la $9, 0xB0000000 // CPCCR: Clock Control Register
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+ la $8, 0x42041110 // I:S:M:P=1:2:2:2
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+ sw $8, 0($9)
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+
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+ la $9, 0xB0000010 // CPPCR: PLL Control Register
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+ la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
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+ sw $8, 0($9)
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+
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+usb_boot_return:
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+ //--------------------------------------------------------------
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+ // Enable the USB PHY
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@ -7460,7 +7518,7 @@ index 0000000..6c3788f
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+ nop
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+
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+__ep0_get_cpu_info:
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+ la $20, cpu_info_data // data pointer to transfer
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+ load_addr $20, cpu_info_data // data pointer to transfer
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+ li $21, 8 // bytes left to transfer
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+ li $22, 1 // set EP0 to TX state
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+ li $23, 0 // NoData = 0
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@ -7524,7 +7582,7 @@ index 0000000..6c3788f
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+ or $20, $9, $8 // target address
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+
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+ b xfer_d2i
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+ li $19, 0x4000 // 16KB data length
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+ li $19, 0x2000 // 16KB data length
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+
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+__ep0_prog_start2:
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+ li $9, 0x48 // SVDOUTPKTRDY and DATAEND
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@ -7600,7 +7658,7 @@ index 0000000..6c3788f
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+ nop
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+
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+___ep0_get_dev_desc:
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+ la $20, device_desc // data pointer
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+ load_addr $20, device_desc // data pointer
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+ li $22, 1 // set EP0 to TX state
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+ sub $8, $21, 18
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+ blez $8, _ep0_idle_state_fini // wLength <= 18
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@ -7610,7 +7668,7 @@ index 0000000..6c3788f
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+ nop
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+
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+___ep0_get_dev_qualifier:
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+ la $20, dev_qualifier // data pointer
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+ load_addr $20, dev_qualifier // data pointer
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+ li $22, 1 // set EP0 to TX state
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+ sub $8, $21, 10
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+ blez $8, _ep0_idle_state_fini // wLength <= 10
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@ -7620,12 +7678,12 @@ index 0000000..6c3788f
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+ nop
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+
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+___ep0_get_conf_desc:
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+ la $20, config_desc_fs // data pointer of FS mode
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+ load_addr $20, config_desc_fs // data pointer of FS mode
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+ lbu $8, 0x01($27) // read POWER
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+ andi $8, 0x10 // test HS_MODE
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+ beqz $8, ___ep0_get_conf_desc2
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+ nop
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+ la $20, config_desc_hs // data pointer of HS mode
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+ load_addr $20, config_desc_hs // data pointer of HS mode
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+
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+___ep0_get_conf_desc2:
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+ li $22, 1 // set EP0 to TX state
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@ -7649,17 +7707,17 @@ index 0000000..6c3788f
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+ nop
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+
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+___ep0_get_string_lang_ids:
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+ la $20, string_lang_ids // data pointer
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+ load_addr $20, string_lang_ids // data pointer
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+ b _ep0_idle_state_fini
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+ li $21, 4 // data length
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+
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+___ep0_get_string_manufacture:
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+ la $20, string_manufacture // data pointer
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+ load_addr $20, string_manufacture // data pointer
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+ b _ep0_idle_state_fini
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+ li $21, 16 // data length
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+
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+___ep0_get_string_product:
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+ la $20, string_product // data pointer
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+ load_addr $20, string_product // data pointer
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+ b _ep0_idle_state_fini
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+ li $21, 46 // data length
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+
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@ -8026,6 +8084,7 @@ index 0000000..6c3788f
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+ .byte 0x30
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+ .byte 0x56
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+ .byte 0x31
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+usbboot_end:
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+
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+ .set reorder
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diff --git a/include/asm-mips/jz4740.h b/include/asm-mips/jz4740.h
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