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[mcs814x] group SYSDBG register defines in mcs814x.h

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32488 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian 2012-06-23 11:03:45 +00:00
parent 01532c0031
commit a699bb193a
3 changed files with 22 additions and 20 deletions
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11
target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/clock.c
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@ -16,17 +16,6 @@
#include <mach/mcs814x.h> #include <mach/mcs814x.h>
/* System configuration registers offsets */
#define SYSDBG_BS1 0x00
#define SYSDBG_SYSCTL 0x08
#define SYSCTL_EMAC (1 << 0)
#define SYSCTL_CIPHER (1 << 16)
#define SYSDBG_PLL_CTL 0x3C
#define CPU_FREQ_SHIFT 27
#define CPU_FREQ_MASK 0x0F
#define SDRAM_FREQ_BIT (1 << 22)
#define KHZ 1000 #define KHZ 1000
#define MHZ (KHZ * KHZ) #define MHZ (KHZ * KHZ)

11
target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/common.c
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@ -32,13 +32,6 @@ static struct map_desc mcs814x_io_desc[] __initdata = {
}, },
}; };
#define SYSDBG_BS2 0x04
#define LED_CFG_MASK 0x03
#define CPU_MODE_SHIFT 23
#define CPU_MODE_MASK 0x03
#define SYSDBG_SYSCTL_MAC 0x1d
struct cpu_mode { struct cpu_mode {
const char *name; const char *name;
int gpio_start; int gpio_start;
@ -96,9 +89,9 @@ static void mcs814x_eth_buffer_shifting_set(u8 value)
reg = __raw_readb(_CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC); reg = __raw_readb(_CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC);
if (value) if (value)
reg |= 0x01; reg |= BUF_SHIFT_BIT;
else else
reg &= ~0x01; reg &= ~BUF_SHIFT_BIT;
__raw_writeb(reg, _CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC); __raw_writeb(reg, _CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC);
} }

20
target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/include/mach/mcs814x.h
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@ -30,5 +30,25 @@
#define _CONFADDR_DBGLED (_VIRT_CONFADDR + _CONFOFFSET_DBGLED) #define _CONFADDR_DBGLED (_VIRT_CONFADDR + _CONFOFFSET_DBGLED)
#define _CONFADDR_SYSDBG (_VIRT_CONFADDR + _CONFOFFSET_SYSDBG) #define _CONFADDR_SYSDBG (_VIRT_CONFADDR + _CONFOFFSET_SYSDBG)
/* System configuration and bootstrap registers */
#define SYSDBG_BS1 0x00
#define CPU_FREQ_SHIFT 27
#define CPU_FREQ_MASK 0x0F
#define SDRAM_FREQ_BIT (1 << 22)
#define SYSDBG_BS2 0x04
#define LED_CFG_MASK 0x03
#define CPU_MODE_SHIFT 23
#define CPU_MODE_MASK 0x03
#define SYSDBG_SYSCTL_MAC 0x1d
#define BUF_SHIFT_BIT (1 << 0)
#define SYSDBG_SYSCTL 0x08
#define SYSCTL_EMAC (1 << 0)
#define SYSCTL_CIPHER (1 << 16)
#define SYSDBG_PLL_CTL 0x3C
#endif /* __ASM_ARCH_MCS814X_H */ #endif /* __ASM_ARCH_MCS814X_H */