mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
uboot-xburst: update to 2010.06
uboot-xburst: don't install empty dir
This commit is contained in:
Xiangfu Liu
Xiangfu
@@ -21,8 +21,8 @@
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#include "nanonote_gpm940b0.h"
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#define KEY_U_OUT (32 * 2 + 16)
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#define KEY_U_IN (32 * 3 + 19)
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@@ -30,15 +30,10 @@
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/*
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* NAND flash definitions
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*/
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#define NAND_DATAPORT 0xb8000000
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#define NAND_ADDRPORT 0xb8010000
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#define NAND_COMMPORT 0xb8008000
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#define ECC_BLOCK 512
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#define ECC_POS 6
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#define PAR_SIZE 9
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#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
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#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define __nand_ecc_rs_encoding() \
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@@ -48,14 +43,6 @@
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#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
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#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
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#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
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static inline void __nand_dev_ready(void)
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{
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unsigned int timeout = 10000;
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while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
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while (!(REG_GPIO_PXPIN(2) & 0x40000000));
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}
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#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
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#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
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#define __nand_data8() REG8(NAND_DATAPORT)
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@@ -75,6 +62,13 @@ static inline void __nand_dev_ready(void)
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#define NAND_ROW_CYCLE 2
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#endif
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static inline void __nand_dev_ready(void)
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{
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unsigned int timeout = 10000;
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while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
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while (!(REG_GPIO_PXPIN(2) & 0x40000000));
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}
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/*
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* NAND flash parameters
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*/
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@@ -84,7 +78,6 @@ static int ecc_count = 4;
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static int page_per_block = 64;
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static int bad_block_pos = 0;
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static int block_size = 131072;
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static unsigned char oob_buf[128] = {0};
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/*
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@@ -167,7 +160,7 @@ static int nand_read_oob(int page_addr, uchar *buf, int size)
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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#ifdef NAND_ROW_CYCLE == 3
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#if defined NAND_ROW_CYCLE && NAND_ROW_CYCLE == 3
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__nand_addr((page_addr >> 16) & 0xff);
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#endif
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@@ -198,7 +191,6 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
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/*
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* Read page data
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*/
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/* Send READ0 command */
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__nand_cmd(NAND_CMD_READ0);
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@@ -210,7 +202,7 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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#if NAND_ROW_CYCLE == 3
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#if defined NAND_ROW_CYCLE && NAND_ROW_CYCLE == 3
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__nand_addr((page_addr >> 16) & 0xff);
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#endif
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@@ -233,16 +225,11 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
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__nand_ecc_rs_decoding();
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/* Read data */
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nand_read_buf((void *)tmpbuf, ECC_BLOCK);
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nand_read_buf((void *)tmpbuf, CONFIG_SYS_NAND_ECCSIZE);
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/* Set PAR values */
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for (j = 0; j < PAR_SIZE; j++) {
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#if defined(CONFIG_SYS_NAND_ECC_POS)
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*paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j];
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#else
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*paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j];
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#endif
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}
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for (j = 0; j < CONFIG_SYS_NAND_ECCBYTES; j++)
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*paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*CONFIG_SYS_NAND_ECCBYTES + j];
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/* Set PRDY */
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REG_EMC_NFECR |= EMC_NFECR_PRDY;
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@@ -257,12 +244,11 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
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stat = REG_EMC_NFINTS;
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if (stat & EMC_NFINTS_ERR) {
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/* Error occurred */
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/* serial_puts("\n Error occurred\n"); */
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/* serial_puts("Error occurred\n"); */
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if (stat & EMC_NFINTS_UNCOR) {
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/* Uncorrectable error occurred */
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/* serial_puts("\nUncorrectable error occurred\n"); */
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}
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else {
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/* serial_puts("Uncorrectable error occurred\n"); */
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} else {
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unsigned int errcnt, index, mask;
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errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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@@ -292,8 +278,7 @@ static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
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}
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}
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}
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tmpbuf += ECC_BLOCK;
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tmpbuf += CONFIG_SYS_NAND_ECCSIZE;
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}
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return 0;
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@@ -333,7 +318,6 @@ static void nand_load(int offs, int uboot_size, uchar *dst)
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}
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static void jz_nand_init(void) {
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/* Optimize the timing of nand */
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REG_EMC_SMCR1 = 0x094c4400;
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}
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@@ -343,38 +327,26 @@ static void gpio_init(void)
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/*
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* Initialize SDRAM pins
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*/
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#if defined(CONFIG_JZ4720)
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__gpio_as_sdram_16bit_4720();
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#elif defined(CONFIG_JZ4725)
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__gpio_as_sdram_16bit_4725();
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#else
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__gpio_as_sdram_32bit();
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#endif
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/*
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* Initialize UART0 pins
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*/
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__gpio_as_uart0();
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__gpio_jtag_to_uart0();
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}
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static int is_usb_boot()
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{
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int keyU = 0;
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__gpio_as_input(KEY_U_IN);
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__gpio_enable_pull(KEY_U_IN);
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__gpio_as_output(KEY_U_OUT);
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__gpio_clear_pin(KEY_U_OUT);
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__gpio_as_input(KEY_U_IN);
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__gpio_enable_pull(KEY_U_IN);
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if (__gpio_get_pin(KEY_U_IN) == 0)
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return 1;
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__gpio_as_output(KEY_U_OUT);
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__gpio_clear_pin(KEY_U_OUT);
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keyU = __gpio_get_pin(KEY_U_IN);
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if (keyU)
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serial_puts("[U] not pressed\n");
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else
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serial_puts("[U] pressed\n");
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return !keyU;
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return 0;
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}
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void nand_boot(void)
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@@ -384,28 +356,30 @@ void nand_boot(void)
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/*
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* Init hardware
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*/
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jz_nand_init();
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gpio_init();
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serial_init();
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serial_puts("\n\nNAND Secondary Program Loader\n\n");
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pll_init();
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__lcd_display_pin_init();
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__lcd_display_on() ;
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serial_init();
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sdram_init();
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jz_nand_init();
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serial_puts("\nNAND Boot\n");
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#if defined(CONFIG_NANONOTE)
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if(is_usb_boot()) {
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serial_puts("enter USB BOOT mode\n");
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serial_puts("[U] pressed, goto USBBOOT mode\n");
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usb_boot();
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}
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#endif
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page_size = CONFIG_SYS_NAND_PAGE_SIZE;
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block_size = CONFIG_SYS_NAND_BLOCK_SIZE;
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page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
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bad_block_pos = (page_size == 512) ? 5 : 0;
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oob_size = page_size / 32;
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ecc_count = page_size / ECC_BLOCK;
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ecc_count = page_size / CONFIG_SYS_NAND_ECCSIZE;
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/*
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* Load U-Boot image from NAND into RAM
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@@ -417,13 +391,9 @@ void nand_boot(void)
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serial_puts("Starting U-Boot ...\n");
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/*
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* Flush caches
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*/
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/* Flush caches */
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flush_cache_all();
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/*
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* Jump to U-Boot image
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*/
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/* Jump to U-Boot image */
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(*uboot)();
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}
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