mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2025-04-21 12:27:27 +03:00
danube to ifxmips transition
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9825 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
@@ -1,5 +1,5 @@
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/*
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* drivers/net/danube_mii0.c
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* drivers/net/ifxmips_mii0.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -17,7 +17,7 @@
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*
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* Copyright (C) 2005 Infineon
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*
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* Rewrite of Infineon Danube code, thanks to infineon for the support,
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* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
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* software and hardware
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*
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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@@ -41,16 +41,16 @@
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#include <asm/checksum.h>
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#include <linux/init.h>
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#include <asm/delay.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_mii0.h>
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#include <asm/danube/danube_dma.h>
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#include <asm/danube/danube_pmu.h>
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#include <asm/ifxmips/ifxmips.h>
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#include <asm/ifxmips/ifxmips_mii0.h>
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#include <asm/ifxmips/ifxmips_dma.h>
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#include <asm/ifxmips/ifxmips_pmu.h>
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static struct net_device danube_mii0_dev;
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static struct net_device ifxmips_mii0_dev;
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static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
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void
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danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
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ifxmips_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
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{
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u32 val = MDIO_ACC_REQUEST |
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((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
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@@ -62,7 +62,7 @@ danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
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}
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unsigned short
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danube_read_mdio (u32 phy_addr, u32 phy_reg)
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ifxmips_read_mdio (u32 phy_addr, u32 phy_reg)
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{
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u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
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((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
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@@ -76,7 +76,7 @@ danube_read_mdio (u32 phy_addr, u32 phy_reg)
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}
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int
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danube_switch_open (struct net_device *dev)
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ifxmips_switch_open (struct net_device *dev)
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{
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struct switch_priv* priv = (struct switch_priv*)dev->priv;
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struct dma_device_info* dma_dev = priv->dma_device;
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@@ -230,12 +230,12 @@ dma_intr_handler (struct dma_device_info* dma_dev, int status)
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switch (status)
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{
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case RCV_INT:
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switch_hw_receive(&danube_mii0_dev, dma_dev);
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switch_hw_receive(&ifxmips_mii0_dev, dma_dev);
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break;
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case TX_BUF_FULL_INT:
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printk("tx buffer full\n");
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netif_stop_queue(&danube_mii0_dev);
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netif_stop_queue(&ifxmips_mii0_dev);
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for (i = 0; i < dma_dev->max_tx_chan_num; i++)
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{
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if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
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@@ -247,7 +247,7 @@ dma_intr_handler (struct dma_device_info* dma_dev, int status)
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for (i = 0; i < dma_dev->max_tx_chan_num; i++)
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dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
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netif_wake_queue(&danube_mii0_dev);
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netif_wake_queue(&ifxmips_mii0_dev);
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break;
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}
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@@ -255,7 +255,7 @@ dma_intr_handler (struct dma_device_info* dma_dev, int status)
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}
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unsigned char*
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danube_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
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ifxmips_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
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{
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unsigned char *buffer = NULL;
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struct sk_buff *skb = NULL;
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@@ -273,7 +273,7 @@ danube_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
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}
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void
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danube_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
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ifxmips_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
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{
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struct sk_buff *skb = NULL;
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@@ -287,7 +287,7 @@ danube_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
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}
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static struct net_device_stats*
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danube_get_stats (struct net_device *dev)
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ifxmips_get_stats (struct net_device *dev)
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{
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return (struct net_device_stats *)dev->priv;
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}
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@@ -303,10 +303,10 @@ switch_init (struct net_device *dev)
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printk("%s up\n", dev->name);
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dev->open = danube_switch_open;
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dev->open = ifxmips_switch_open;
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dev->stop = switch_release;
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dev->hard_start_xmit = switch_tx;
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dev->get_stats = danube_get_stats;
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dev->get_stats = ifxmips_get_stats;
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dev->tx_timeout = switch_tx_timeout;
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dev->watchdog_timeo = 10 * HZ;
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dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
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@@ -324,8 +324,8 @@ switch_init (struct net_device *dev)
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return -ENODEV;
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}
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priv->dma_device->buffer_alloc = &danube_etop_dma_buffer_alloc;
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priv->dma_device->buffer_free = &danube_etop_dma_buffer_free;
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priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
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priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
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priv->dma_device->intr_handler = &dma_intr_handler;
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priv->dma_device->max_rx_chan_num = 4;
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@@ -371,10 +371,10 @@ switch_init (struct net_device *dev)
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}
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static void
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danube_sw_chip_init (int mode)
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ifxmips_sw_chip_init (int mode)
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{
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danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
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danube_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
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ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
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ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
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if(mode == REV_MII_MODE)
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writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
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@@ -393,21 +393,21 @@ switch_init_module(void)
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{
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int result = 0;
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danube_mii0_dev.init = switch_init;
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ifxmips_mii0_dev.init = switch_init;
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strcpy(danube_mii0_dev.name, "eth%d");
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strcpy(ifxmips_mii0_dev.name, "eth%d");
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SET_MODULE_OWNER(dev);
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result = register_netdev(&danube_mii0_dev);
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result = register_netdev(&ifxmips_mii0_dev);
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if (result)
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{
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printk("error %i registering device \"%s\"\n", result, danube_mii0_dev.name);
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printk("error %i registering device \"%s\"\n", result, ifxmips_mii0_dev.name);
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goto out;
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}
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/* danube eval kit connects the phy/switch in REV mode */
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danube_sw_chip_init(REV_MII_MODE);
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printk("danube MAC driver loaded!\n");
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/* ifxmips eval kit connects the phy/switch in REV mode */
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ifxmips_sw_chip_init(REV_MII_MODE);
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printk("ifxmips MAC driver loaded!\n");
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out:
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return result;
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@@ -416,15 +416,15 @@ out:
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static void __exit
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switch_cleanup(void)
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{
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struct switch_priv *priv = (struct switch_priv*)danube_mii0_dev.priv;
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struct switch_priv *priv = (struct switch_priv*)ifxmips_mii0_dev.priv;
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printk("danube_mii0 cleanup\n");
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printk("ifxmips_mii0 cleanup\n");
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dma_device_unregister(priv->dma_device);
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dma_device_release(priv->dma_device);
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kfree(priv->dma_device);
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kfree(danube_mii0_dev.priv);
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unregister_netdev(&danube_mii0_dev);
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kfree(ifxmips_mii0_dev.priv);
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unregister_netdev(&ifxmips_mii0_dev);
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return;
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}
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