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[ar71xx] fix the PCI byte lane enable generation code, based on a patch by Chris Dearman

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12617 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2008-09-17 13:29:47 +00:00
parent 40b17025ed
commit ac1c761834
1 changed files with 6 additions and 5 deletions
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11
target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
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@@ -59,17 +59,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
/* Byte lane enable bits */ /* Byte lane enable bits */
static u8 ble_table[4][4] = { static u8 ble_table[4][4] = {
{0xf, 0xe, 0xd, 0xc}, {0x0, 0xf, 0xf, 0xf},
{0xc, 0x9, 0x3, 0x1}, {0xe, 0xd, 0xb, 0x7},
{0x0, 0x0, 0x0, 0x0}, {0xc, 0xf, 0x3, 0xf},
{0x0, 0x0, 0x0, 0x0}, {0xf, 0xf, 0xf, 0xf},
}; };
static inline u32 ar71xx_pci_get_ble(int where, int size, int local) static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{ {
u32 t; u32 t;
t = ble_table[size][where & 3]; t = ble_table[size & 3][where & 3];
BUG_ON(t == 0xf);
t <<= (local) ? 20 : 4; t <<= (local) ? 20 : 4;
return t; return t;
} }