mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-13 07:29:22 +02:00
clean up mmu/cache patch for bcm4710 - improves stability a lot
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@1297 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
parent
d3b10c676c
commit
b0fa7eb5fd
@ -1,114 +1,6 @@
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diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
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--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-05-28 17:42:03.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-05-28 21:48:55.000000000 +0200
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@@ -90,6 +90,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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#ifdef CONFIG_SMP
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mfc0 k1, CP0_CONTEXT
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la k0, pgd_current
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diff -urN linux.old/arch/mips/mm/pg-r4k.c linux.dev/arch/mips/mm/pg-r4k.c
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--- linux.old/arch/mips/mm/pg-r4k.c 2005-01-19 15:09:29.000000000 +0100
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+++ linux.dev/arch/mips/mm/pg-r4k.c 2005-05-28 21:57:52.000000000 +0200
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@@ -180,6 +180,7 @@
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static inline void build_cdex_s(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if ((store_offset & (cpu_scache_line_size() - 1)))
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@@ -192,10 +193,12 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static inline void build_cdex_p(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if (store_offset & (cpu_dcache_line_size() - 1))
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@@ -218,6 +221,7 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static void __build_store_reg(int reg)
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diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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--- linux.old/include/asm-mips/stackframe.h 2002-11-29 00:53:15.000000000 +0100
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+++ linux.dev/include/asm-mips/stackframe.h 2005-05-28 21:53:03.000000000 +0200
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@@ -172,6 +172,46 @@
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rfe; \
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.set pop
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+#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
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+
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+#define RESTORE_SOME \
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+ .set push; \
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+ .set reorder; \
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+ mfc0 t0, CP0_STATUS; \
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+ .set pop; \
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+ ori t0, 0x1f; \
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+ xori t0, 0x1f; \
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+ mtc0 t0, CP0_STATUS; \
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+ li v1, 0xff00; \
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+ and t0, v1; \
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+ lw v0, PT_STATUS(sp); \
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+ nor v1, $0, v1; \
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+ and v0, v1; \
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+ or v0, t0; \
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+ ori v1, v0, ST0_IE; \
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+ xori v1, v1, ST0_IE; \
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+ mtc0 v1, CP0_STATUS; \
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+ mtc0 v0, CP0_STATUS; \
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+ lw v1, PT_EPC(sp); \
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+ mtc0 v1, CP0_EPC; \
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+ lw $31, PT_R31(sp); \
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+ lw $28, PT_R28(sp); \
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+ lw $25, PT_R25(sp); \
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+ lw $7, PT_R7(sp); \
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+ lw $6, PT_R6(sp); \
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+ lw $5, PT_R5(sp); \
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+ lw $4, PT_R4(sp); \
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+ lw $3, PT_R3(sp); \
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+ lw $2, PT_R2(sp)
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+
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+#define RESTORE_SP_AND_RET \
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+ lw sp, PT_R29(sp); \
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+ nop; \
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+ nop; \
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+ .set mips3; \
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+ eret; \
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+ .set mips0
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+
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#else
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#define RESTORE_SOME \
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diff -urN linux.old/arch/mips/mm/tlbex-r4k.S linux.dev/arch/mips/mm/tlbex-r4k.S
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--- linux.old/arch/mips/mm/tlbex-r4k.S 2005-05-28 17:42:03.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-r4k.S 2005-05-29 15:04:43.000000000 +0200
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@@ -168,6 +168,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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GET_PGD(k0, k1) # get pgd pointer
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mfc0 k0, CP0_BADVADDR # Get faulting address
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srl k0, k0, _PGDIR_SHIFT # get pgd only bits
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diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
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diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
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--- linux.old/arch/mips/kernel/entry.S 2003-08-25 13:44:40.000000000 +0200
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--- linux.old/arch/mips/kernel/entry.S 2005-06-26 16:27:01.000000000 +0200
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+++ linux.dev/arch/mips/kernel/entry.S 2005-06-01 20:10:36.000000000 +0200
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+++ linux.dev/arch/mips/kernel/entry.S 2005-06-29 20:24:54.000000000 +0200
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@@ -100,6 +100,10 @@
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@@ -100,6 +100,10 @@
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* and R4400 SC and MC versions.
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* and R4400 SC and MC versions.
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*/
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*/
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@ -121,8 +13,8 @@ diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
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mfc0 k0, CP0_INDEX
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mfc0 k0, CP0_INDEX
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#endif
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#endif
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-06-01 18:42:44.000000000 +0200
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--- linux.old/arch/mips/mm/c-r4k.c 2005-06-26 16:27:01.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-01 18:49:07.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-30 22:24:29.000000000 +0200
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@@ -14,6 +14,12 @@
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@@ -14,6 +14,12 @@
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#include <linux/mm.h>
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#include <linux/mm.h>
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#include <linux/bitops.h>
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#include <linux/bitops.h>
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@ -136,276 +28,143 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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#include <asm/bcache.h>
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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#include <asm/cacheops.h>
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@@ -390,6 +396,11 @@
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@@ -40,6 +46,7 @@
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addr = start & ~(dc_lsize - 1);
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.bc_inv = (void *)no_sc_noop
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aend = (end - 1) & ~(dc_lsize - 1);
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};
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+#ifdef CONFIG_BCM4710
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+static int bcm4710 = 0;
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+ BCM4710_FILL_TLB(addr);
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struct bcache_ops *bcops = &no_sc_ops;
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+ BCM4710_FILL_TLB(aend);
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+#endif
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#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
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@@ -266,6 +273,7 @@
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r4k_blast_dcache();
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r4k_blast_icache();
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+ if (!bcm4710)
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switch (current_cpu_data.cputype) {
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case CPU_R4000SC:
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case CPU_R4000MC:
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@@ -304,10 +312,10 @@
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* Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
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* only flush the primary caches but R10000 and R12000 behave sane ...
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*/
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- if (current_cpu_data.cputype == CPU_R4000SC ||
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+ if (!bcm4710 && (current_cpu_data.cputype == CPU_R4000SC ||
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current_cpu_data.cputype == CPU_R4000MC ||
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current_cpu_data.cputype == CPU_R4400SC ||
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- current_cpu_data.cputype == CPU_R4400MC)
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+ current_cpu_data.cputype == CPU_R4400MC))
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r4k_blast_scache();
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}
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@@ -383,12 +391,15 @@
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long addr, aend;
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+ addr = start & ~(dc_lsize - 1);
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+ aend = (end - 1) & ~(dc_lsize - 1);
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+
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+
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if (!cpu_has_ic_fills_f_dc) {
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if (end - start > dcache_size)
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r4k_blast_dcache();
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else {
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- addr = start & ~(dc_lsize - 1);
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- aend = (end - 1) & ~(dc_lsize - 1);
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(aend);
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while (1) {
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while (1) {
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/* Hit_Writeback_Inv_D */
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/* Hit_Writeback_Inv_D */
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protected_writeback_dcache_line(addr);
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@@ -403,8 +414,6 @@
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@@ -405,6 +416,10 @@
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if (end - start > icache_size)
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r4k_blast_icache();
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else {
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else {
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addr = start & ~(ic_lsize - 1);
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- addr = start & ~(ic_lsize - 1);
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aend = (end - 1) & ~(ic_lsize - 1);
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- aend = (end - 1) & ~(ic_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(addr);
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+ BCM4710_FILL_TLB(aend);
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+#endif
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while (1) {
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while (1) {
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/* Hit_Invalidate_I */
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/* Hit_Invalidate_I */
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protected_flush_icache_line(addr);
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protected_flush_icache_line(addr);
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@@ -487,6 +502,10 @@
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@@ -443,7 +452,8 @@
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if (cpu_has_subset_pcaches) {
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unsigned long addr = (unsigned long) page_address(page);
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a = addr & ~(sc_lsize - 1);
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- r4k_blast_scache_page(addr);
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end = (addr + size - 1) & ~(sc_lsize - 1);
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+ if (!bcm4710)
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+#ifdef CONFIG_BCM4710
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+ r4k_blast_scache_page(addr);
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+ BCM4710_FILL_TLB(a);
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ClearPageDcacheDirty(page);
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+ BCM4710_FILL_TLB(end);
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+#endif
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return;
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while (1) {
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@@ -451,6 +461,7 @@
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flush_scache_line(a); /* Hit_Writeback_Inv_SD */
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if (a == end)
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if (!cpu_has_ic_fills_f_dc) {
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@@ -509,6 +528,10 @@
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unsigned long addr = (unsigned long) page_address(page);
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+
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r4k_blast_dcache_page(addr);
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ClearPageDcacheDirty(page);
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}
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@@ -477,7 +488,7 @@
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/* Catch bad driver code */
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BUG_ON(size == 0);
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- if (cpu_has_subset_pcaches) {
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+ if (!bcm4710 && cpu_has_subset_pcaches) {
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unsigned long sc_lsize = current_cpu_data.scache.linesz;
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if (size >= scache_size) {
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@@ -509,6 +520,8 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+ BCM4710_FILL_TLB(end);
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+#endif
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while (1) {
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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if (a == end)
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@@ -537,6 +560,10 @@
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@@ -527,7 +540,7 @@
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/* Catch bad driver code */
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BUG_ON(size == 0);
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a = addr & ~(sc_lsize - 1);
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- if (cpu_has_subset_pcaches) {
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end = (addr + size - 1) & ~(sc_lsize - 1);
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+ if (!bcm4710 && (cpu_has_subset_pcaches)) {
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+#ifdef CONFIG_BCM4710
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unsigned long sc_lsize = current_cpu_data.scache.linesz;
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if (size >= scache_size) {
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@@ -554,6 +567,8 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+ BCM4710_FILL_TLB(end);
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+#endif
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while (1) {
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while (1) {
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flush_scache_line(a); /* Hit_Writeback_Inv_SD */
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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if (a == end)
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@@ -576,6 +603,10 @@
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@@ -577,6 +592,8 @@
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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+#ifdef CONFIG_BCM4710
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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+#endif
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R4600_HIT_CACHEOP_WAR_IMPL;
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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if (MIPS4K_ICACHE_REFILL_WAR) {
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--- linux.old/include/asm-mips/r4kcache.h 2005-06-01 18:42:43.000000000 +0200
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@@ -986,10 +1003,12 @@
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+++ linux.dev/include/asm-mips/r4kcache.h 2005-06-01 19:07:11.000000000 +0200
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case CPU_R4000MC:
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@@ -15,6 +15,25 @@
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case CPU_R4400SC:
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#include <asm/asm.h>
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case CPU_R4400MC:
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#include <asm/cacheops.h>
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- probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
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- sc_present = probe_scache_kseg1(config);
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+#ifdef CONFIG_BCM4710
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- if (sc_present)
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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- c->options |= MIPS_CPU_CACHE_CDEX_S;
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+
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+ if (!bcm4710) {
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+ probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+ sc_present = probe_scache_kseg1(config);
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+
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+ if (sc_present)
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+#define cache_op(op,addr) \
|
+ c->options |= MIPS_CPU_CACHE_CDEX_S;
|
||||||
+ BCM4710_DUMMY_RREG(); \
|
|
||||||
+ __asm__ __volatile__( \
|
|
||||||
+ " .set noreorder \n" \
|
|
||||||
+ " .set mips3\n\t \n" \
|
|
||||||
+ " cache %0, %1 \n" \
|
|
||||||
+ " .set mips0 \n" \
|
|
||||||
+ " .set reorder" \
|
|
||||||
+ : \
|
|
||||||
+ : "i" (op), "m" (*(unsigned char *)(addr)))
|
|
||||||
+
|
|
||||||
+#else
|
|
||||||
+
|
|
||||||
#define cache_op(op,addr) \
|
|
||||||
__asm__ __volatile__( \
|
|
||||||
" .set noreorder \n" \
|
|
||||||
@@ -24,6 +43,8 @@
|
|
||||||
" .set reorder" \
|
|
||||||
: \
|
|
||||||
: "i" (op), "m" (*(unsigned char *)(addr)))
|
|
||||||
+#endif
|
|
||||||
+
|
|
||||||
|
|
||||||
static inline void flush_icache_line_indexed(unsigned long addr)
|
|
||||||
{
|
|
||||||
@@ -32,6 +53,9 @@
|
|
||||||
|
|
||||||
static inline void flush_dcache_line_indexed(unsigned long addr)
|
|
||||||
{
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache_op(Index_Writeback_Inv_D, addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
@@ -47,6 +71,10 @@
|
|
||||||
|
|
||||||
static inline void flush_dcache_line(unsigned long addr)
|
|
||||||
{
|
|
||||||
+
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache_op(Hit_Writeback_Inv_D, addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
@@ -91,6 +119,9 @@
|
|
||||||
*/
|
|
||||||
static inline void protected_writeback_dcache_line(unsigned long addr)
|
|
||||||
{
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
__asm__ __volatile__(
|
|
||||||
".set noreorder\n\t"
|
|
||||||
".set mips3\n"
|
|
||||||
@@ -148,8 +179,12 @@
|
|
||||||
unsigned long ws, addr;
|
|
||||||
|
|
||||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
||||||
- for (addr = start; addr < end; addr += 0x200)
|
|
||||||
+ for (addr = start; addr < end; addr += 0x200) {
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
|
|
||||||
+ }
|
+ }
|
||||||
}
|
break;
|
||||||
|
|
||||||
static inline void blast_dcache16_page(unsigned long page)
|
case CPU_R10000:
|
||||||
@@ -158,6 +193,9 @@
|
@@ -1041,6 +1060,19 @@
|
||||||
unsigned long end = start + PAGE_SIZE;
|
|
||||||
|
|
||||||
do {
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache16_unroll32(start,Hit_Writeback_Inv_D);
|
|
||||||
start += 0x200;
|
|
||||||
} while (start < end);
|
|
||||||
@@ -173,8 +211,12 @@
|
|
||||||
unsigned long ws, addr;
|
|
||||||
|
|
||||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
||||||
- for (addr = start; addr < end; addr += 0x200)
|
|
||||||
+ for (addr = start; addr < end; addr += 0x200) {
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
|
|
||||||
+ }
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void blast_icache16(void)
|
|
||||||
@@ -196,7 +238,13 @@
|
|
||||||
unsigned long start = page;
|
|
||||||
unsigned long end = start + PAGE_SIZE;
|
|
||||||
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_FILL_TLB(start);
|
|
||||||
+#endif
|
|
||||||
do {
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache16_unroll32(start,Hit_Invalidate_I);
|
|
||||||
start += 0x200;
|
|
||||||
} while (start < end);
|
|
||||||
@@ -291,8 +339,12 @@
|
|
||||||
unsigned long ws, addr;
|
|
||||||
|
|
||||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
||||||
- for (addr = start; addr < end; addr += 0x400)
|
|
||||||
+ for (addr = start; addr < end; addr += 0x400) {
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
|
||||||
+ }
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void blast_dcache32_page(unsigned long page)
|
|
||||||
@@ -300,7 +352,13 @@
|
|
||||||
unsigned long start = page;
|
|
||||||
unsigned long end = start + PAGE_SIZE;
|
|
||||||
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ __asm__ __volatile__("nop;nop;nop;nop");
|
|
||||||
+#endif
|
|
||||||
do {
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+#endif
|
|
||||||
cache32_unroll32(start,Hit_Writeback_Inv_D);
|
|
||||||
start += 0x400;
|
|
||||||
} while (start < end);
|
|
||||||
@@ -339,6 +397,9 @@
|
|
||||||
unsigned long start = page;
|
|
||||||
unsigned long end = start + PAGE_SIZE;
|
|
||||||
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_FILL_TLB(start);
|
|
||||||
+#endif
|
|
||||||
do {
|
|
||||||
cache32_unroll32(start,Hit_Invalidate_I);
|
|
||||||
start += 0x400;
|
|
||||||
diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|
||||||
--- linux.old/arch/mips/mm/c-r4k.c 2005-06-01 18:49:07.000000000 +0200
|
|
||||||
+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-03 12:11:13.000000000 +0200
|
|
||||||
@@ -51,6 +51,7 @@
|
|
||||||
#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
|
|
||||||
#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020)
|
|
||||||
|
|
||||||
+#ifndef CONFIG_BCM4710
|
|
||||||
#define R4600_HIT_CACHEOP_WAR_IMPL \
|
|
||||||
do { \
|
|
||||||
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
|
|
||||||
@@ -58,11 +59,17 @@
|
|
||||||
if (R4600_V1_HIT_CACHEOP_WAR) \
|
|
||||||
__asm__ __volatile__("nop;nop;nop;nop"); \
|
|
||||||
} while (0)
|
|
||||||
+#else
|
|
||||||
+#define R4600_HIT_CACHEOP_WAR_IMPL
|
|
||||||
+#endif
|
|
||||||
|
|
||||||
static void (* r4k_blast_dcache_page)(unsigned long addr);
|
|
||||||
|
|
||||||
static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
|
|
||||||
{
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_FILL_TLB(addr);
|
|
||||||
+#endif
|
|
||||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
|
||||||
blast_dcache32_page(addr);
|
|
||||||
}
|
|
||||||
@@ -581,6 +588,10 @@
|
|
||||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
|
||||||
a = addr & ~(dc_lsize - 1);
|
|
||||||
end = (addr + size - 1) & ~(dc_lsize - 1);
|
|
||||||
+#ifdef CONFIG_BCM4710
|
|
||||||
+ BCM4710_FILL_TLB(a);
|
|
||||||
+ BCM4710_FILL_TLB(end);
|
|
||||||
+#endif
|
|
||||||
while (1) {
|
|
||||||
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
|
||||||
if (a == end)
|
|
||||||
diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|
||||||
--- linux.old/arch/mips/mm/c-r4k.c 2005-06-11 19:39:17.000000000 +0200
|
|
||||||
+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-11 19:54:48.000000000 +0200
|
|
||||||
@@ -1083,6 +1083,19 @@
|
|
||||||
static inline void coherency_setup(void)
|
static inline void coherency_setup(void)
|
||||||
{
|
{
|
||||||
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
|
||||||
@ -425,7 +184,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* c0_status.cu=0 specifies that updates by the sc instruction use
|
* c0_status.cu=0 specifies that updates by the sc instruction use
|
||||||
@@ -1104,6 +1117,42 @@
|
@@ -1062,6 +1094,42 @@
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -468,7 +227,19 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||||||
void __init ld_mmu_r4xx0(void)
|
void __init ld_mmu_r4xx0(void)
|
||||||
{
|
{
|
||||||
extern void build_clear_page(void);
|
extern void build_clear_page(void);
|
||||||
@@ -1159,47 +1208,9 @@
|
@@ -1073,6 +1141,11 @@
|
||||||
|
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
|
||||||
|
memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
|
||||||
|
|
||||||
|
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & PRID_REV_MASK) == 0)
|
||||||
|
+ bcm4710 = 1;
|
||||||
|
+ else
|
||||||
|
+ bcm4710 = 0;
|
||||||
|
+
|
||||||
|
probe_pcache();
|
||||||
|
setup_scache();
|
||||||
|
|
||||||
|
@@ -1117,47 +1190,9 @@
|
||||||
|
|
||||||
build_clear_page();
|
build_clear_page();
|
||||||
build_copy_page();
|
build_copy_page();
|
||||||
@ -518,3 +289,271 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
|
|||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
|
||||||
|
--- linux.old/arch/mips/mm/tlb-r4k.c 2005-06-26 16:24:26.000000000 +0200
|
||||||
|
+++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-06-29 20:29:16.000000000 +0200
|
||||||
|
@@ -38,6 +38,7 @@
|
||||||
|
old_ctx = read_c0_entryhi();
|
||||||
|
write_c0_entrylo0(0);
|
||||||
|
write_c0_entrylo1(0);
|
||||||
|
+ BARRIER;
|
||||||
|
|
||||||
|
entry = read_c0_wired();
|
||||||
|
|
||||||
|
@@ -47,6 +48,7 @@
|
||||||
|
write_c0_index(entry);
|
||||||
|
mtc0_tlbw_hazard();
|
||||||
|
tlb_write_indexed();
|
||||||
|
+ BARRIER;
|
||||||
|
entry++;
|
||||||
|
}
|
||||||
|
tlbw_use_hazard();
|
||||||
|
@@ -98,6 +100,7 @@
|
||||||
|
write_c0_entryhi(KSEG0 + idx*0x2000);
|
||||||
|
mtc0_tlbw_hazard();
|
||||||
|
tlb_write_indexed();
|
||||||
|
+ BARRIER;
|
||||||
|
}
|
||||||
|
tlbw_use_hazard();
|
||||||
|
write_c0_entryhi(oldpid);
|
||||||
|
@@ -136,6 +139,7 @@
|
||||||
|
tlbw_use_hazard();
|
||||||
|
|
||||||
|
finish:
|
||||||
|
+ BARRIER;
|
||||||
|
write_c0_entryhi(oldpid);
|
||||||
|
local_irq_restore(flags);
|
||||||
|
}
|
||||||
|
@@ -204,6 +208,7 @@
|
||||||
|
pmdp = pmd_offset(pgdp, address);
|
||||||
|
idx = read_c0_index();
|
||||||
|
ptep = pte_offset(pmdp, address);
|
||||||
|
+ BARRIER;
|
||||||
|
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||||
|
write_c0_entrylo0(ptep->pte_high);
|
||||||
|
ptep++;
|
||||||
|
@@ -220,6 +225,7 @@
|
||||||
|
tlb_write_indexed();
|
||||||
|
tlbw_use_hazard();
|
||||||
|
write_c0_entryhi(pid);
|
||||||
|
+ BARRIER;
|
||||||
|
local_irq_restore(flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -317,6 +323,7 @@
|
||||||
|
}
|
||||||
|
|
||||||
|
write_c0_index(temp_tlb_entry);
|
||||||
|
+ BARRIER;
|
||||||
|
write_c0_pagemask(pagemask);
|
||||||
|
write_c0_entryhi(entryhi);
|
||||||
|
write_c0_entrylo0(entrylo0);
|
||||||
|
diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
|
||||||
|
--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-06-26 16:27:01.000000000 +0200
|
||||||
|
+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-06-29 20:24:54.000000000 +0200
|
||||||
|
@@ -90,6 +90,9 @@
|
||||||
|
.set noat
|
||||||
|
LEAF(except_vec0_r4000)
|
||||||
|
.set mips3
|
||||||
|
+#ifdef CONFIG_BCM4704
|
||||||
|
+ nop
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_SMP
|
||||||
|
mfc0 k1, CP0_CONTEXT
|
||||||
|
la k0, pgd_current
|
||||||
|
diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
|
||||||
|
--- linux.old/include/asm-mips/r4kcache.h 2005-06-26 16:27:01.000000000 +0200
|
||||||
|
+++ linux.dev/include/asm-mips/r4kcache.h 2005-06-30 22:39:42.000000000 +0200
|
||||||
|
@@ -15,6 +15,18 @@
|
||||||
|
#include <asm/asm.h>
|
||||||
|
#include <asm/cacheops.h>
|
||||||
|
|
||||||
|
+#ifdef CONFIG_BCM4710
|
||||||
|
+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
||||||
|
+#else
|
||||||
|
+#define BCM4710_DUMMY_RREG()
|
||||||
|
+
|
||||||
|
+#define BCM4710_FILL_TLB(addr)
|
||||||
|
+#define BCM4710_PROTECTED_FILL_TLB(addr)
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
#define cache_op(op,addr) \
|
||||||
|
__asm__ __volatile__( \
|
||||||
|
" .set noreorder \n" \
|
||||||
|
@@ -32,6 +44,7 @@
|
||||||
|
|
||||||
|
static inline void flush_dcache_line_indexed(unsigned long addr)
|
||||||
|
{
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Index_Writeback_Inv_D, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -47,6 +60,7 @@
|
||||||
|
|
||||||
|
static inline void flush_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache_op(Hit_Writeback_Inv_D, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -91,6 +105,7 @@
|
||||||
|
*/
|
||||||
|
static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||||
|
{
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
__asm__ __volatile__(
|
||||||
|
".set noreorder\n\t"
|
||||||
|
".set mips3\n"
|
||||||
|
@@ -148,8 +163,10 @@
|
||||||
|
unsigned long ws, addr;
|
||||||
|
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||||
|
- for (addr = start; addr < end; addr += 0x200)
|
||||||
|
+ for (addr = start; addr < end; addr += 0x200) {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void blast_dcache16_page(unsigned long page)
|
||||||
|
@@ -157,7 +174,9 @@
|
||||||
|
unsigned long start = page;
|
||||||
|
unsigned long end = start + PAGE_SIZE;
|
||||||
|
|
||||||
|
+ BCM4710_FILL_TLB(start);
|
||||||
|
do {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache16_unroll32(start,Hit_Writeback_Inv_D);
|
||||||
|
start += 0x200;
|
||||||
|
} while (start < end);
|
||||||
|
@@ -173,8 +192,10 @@
|
||||||
|
unsigned long ws, addr;
|
||||||
|
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||||
|
- for (addr = start; addr < end; addr += 0x200)
|
||||||
|
+ for (addr = start; addr < end; addr += 0x200) {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void blast_icache16(void)
|
||||||
|
@@ -196,6 +217,7 @@
|
||||||
|
unsigned long start = page;
|
||||||
|
unsigned long end = start + PAGE_SIZE;
|
||||||
|
|
||||||
|
+ BCM4710_FILL_TLB(start);
|
||||||
|
do {
|
||||||
|
cache16_unroll32(start,Hit_Invalidate_I);
|
||||||
|
start += 0x200;
|
||||||
|
@@ -281,6 +303,7 @@
|
||||||
|
: "r" (base), \
|
||||||
|
"i" (op));
|
||||||
|
|
||||||
|
+
|
||||||
|
static inline void blast_dcache32(void)
|
||||||
|
{
|
||||||
|
unsigned long start = KSEG0;
|
||||||
|
@@ -291,8 +314,10 @@
|
||||||
|
unsigned long ws, addr;
|
||||||
|
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||||
|
- for (addr = start; addr < end; addr += 0x400)
|
||||||
|
+ for (addr = start; addr < end; addr += 0x400) {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void blast_dcache32_page(unsigned long page)
|
||||||
|
@@ -300,7 +325,9 @@
|
||||||
|
unsigned long start = page;
|
||||||
|
unsigned long end = start + PAGE_SIZE;
|
||||||
|
|
||||||
|
+ BCM4710_FILL_TLB(start);
|
||||||
|
do {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache32_unroll32(start,Hit_Writeback_Inv_D);
|
||||||
|
start += 0x400;
|
||||||
|
} while (start < end);
|
||||||
|
@@ -316,8 +343,10 @@
|
||||||
|
unsigned long ws, addr;
|
||||||
|
|
||||||
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||||
|
- for (addr = start; addr < end; addr += 0x400)
|
||||||
|
+ for (addr = start; addr < end; addr += 0x400) {
|
||||||
|
+ BCM4710_DUMMY_RREG();
|
||||||
|
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void blast_icache32(void)
|
||||||
|
@@ -339,6 +368,7 @@
|
||||||
|
unsigned long start = page;
|
||||||
|
unsigned long end = start + PAGE_SIZE;
|
||||||
|
|
||||||
|
+ BCM4710_FILL_TLB(start);
|
||||||
|
do {
|
||||||
|
cache32_unroll32(start,Hit_Invalidate_I);
|
||||||
|
start += 0x400;
|
||||||
|
@@ -443,6 +473,7 @@
|
||||||
|
unsigned long start = page;
|
||||||
|
unsigned long end = start + PAGE_SIZE;
|
||||||
|
|
||||||
|
+ BCM4710_FILL_TLB(start);
|
||||||
|
do {
|
||||||
|
cache64_unroll32(start,Hit_Invalidate_I);
|
||||||
|
start += 0x800;
|
||||||
|
diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
|
||||||
|
--- linux.old/include/asm-mips/stackframe.h 2005-06-26 16:27:01.000000000 +0200
|
||||||
|
+++ linux.dev/include/asm-mips/stackframe.h 2005-06-30 19:04:46.000000000 +0200
|
||||||
|
@@ -172,6 +172,46 @@
|
||||||
|
rfe; \
|
||||||
|
.set pop
|
||||||
|
|
||||||
|
+#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
|
||||||
|
+
|
||||||
|
+#define RESTORE_SOME \
|
||||||
|
+ .set push; \
|
||||||
|
+ .set reorder; \
|
||||||
|
+ mfc0 t0, CP0_STATUS; \
|
||||||
|
+ .set pop; \
|
||||||
|
+ ori t0, 0x1f; \
|
||||||
|
+ xori t0, 0x1f; \
|
||||||
|
+ mtc0 t0, CP0_STATUS; \
|
||||||
|
+ li v1, 0xff00; \
|
||||||
|
+ and t0, v1; \
|
||||||
|
+ lw v0, PT_STATUS(sp); \
|
||||||
|
+ nor v1, $0, v1; \
|
||||||
|
+ and v0, v1; \
|
||||||
|
+ or v0, t0; \
|
||||||
|
+ ori v1, v0, ST0_IE; \
|
||||||
|
+ xori v1, v1, ST0_IE; \
|
||||||
|
+ mtc0 v1, CP0_STATUS; \
|
||||||
|
+ mtc0 v0, CP0_STATUS; \
|
||||||
|
+ lw v1, PT_EPC(sp); \
|
||||||
|
+ mtc0 v1, CP0_EPC; \
|
||||||
|
+ lw $31, PT_R31(sp); \
|
||||||
|
+ lw $28, PT_R28(sp); \
|
||||||
|
+ lw $25, PT_R25(sp); \
|
||||||
|
+ lw $7, PT_R7(sp); \
|
||||||
|
+ lw $6, PT_R6(sp); \
|
||||||
|
+ lw $5, PT_R5(sp); \
|
||||||
|
+ lw $4, PT_R4(sp); \
|
||||||
|
+ lw $3, PT_R3(sp); \
|
||||||
|
+ lw $2, PT_R2(sp)
|
||||||
|
+
|
||||||
|
+#define RESTORE_SP_AND_RET \
|
||||||
|
+ lw sp, PT_R29(sp); \
|
||||||
|
+ nop; \
|
||||||
|
+ nop; \
|
||||||
|
+ .set mips3; \
|
||||||
|
+ eret; \
|
||||||
|
+ .set mips0
|
||||||
|
+
|
||||||
|
#else
|
||||||
|
|
||||||
|
#define RESTORE_SOME \
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user