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git://projects.qi-hardware.com/openwrt-xburst.git
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this patch add uboot-xburst package
uboot-xburst-avt2 uboot-xburst-n516 uboot-xburst-qi_lb60 uboot-xburst-sakc Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
Xiangfu Liu
250
package/uboot-xburst/files/drivers/mtd/nand/jz4740_nand.c
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250
package/uboot-xburst/files/drivers/mtd/nand/jz4740_nand.c
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/*
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* Platform independend driver for JZ4740.
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*
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* Copyright (c) 2007 Ingenic Semiconductor Inc.
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* Author: <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
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#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
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#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
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#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
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#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
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#define BIT(x) (1 << (x))
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#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
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#define JZ_NAND_ECC_CTRL_RS BIT(2)
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#define JZ_NAND_ECC_CTRL_RESET BIT(1)
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#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
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static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
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.eccbytes = 72,
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.eccpos = {
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12, 13, 14, 15, 16, 17, 18, 19,
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20, 21, 22, 23, 24, 25, 26, 27,
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28, 29, 30, 31, 32, 33, 34, 35,
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36, 37, 38, 39, 40, 41, 42, 43,
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44, 45, 46, 47, 48, 49, 50, 51,
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52, 53, 54, 55, 56, 57, 58, 59,
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60, 61, 62, 63, 64, 65, 66, 67,
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68, 69, 70, 71, 72, 73, 74, 75,
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76, 77, 78, 79, 80, 81, 82, 83},
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.oobfree = {
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{.offset = 2,
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.length = 10},
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{.offset = 84,
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.length = 44}}
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};
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static int is_reading;
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static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_ALE)
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this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
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else if (ctrl & NAND_CLE)
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this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
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else
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this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
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if (ctrl & NAND_NCE)
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REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
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else
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REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static int jz_nand_device_ready(struct mtd_info *mtd)
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{
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udelay(20);
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return (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
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}
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void board_nand_select_device(struct nand_chip *nand, int chip)
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{
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/*
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* Don't use "chip" to address the NAND device,
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* generate the cs from the address where it is encoded.
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*/
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}
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static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat,
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u_char* ecc_code)
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{
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uint32_t reg, status;
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int i;
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volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
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if(is_reading)
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return 0;
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do {
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status = REG_EMC_NFINTS;
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} while(!(status & EMC_NFINTS_ENCF));
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__nand_ecc_disable();
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for(i = 0; i < 9; i++)
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ecc_code[i] = *(paraddr + i);
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return 0;
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}
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static void jz_nand_hwctl(struct mtd_info* mtd, int mode)
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{
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uint32_t reg;
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REG_EMC_NFINTS = 0;
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reg = REG_EMC_NFECR;
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reg |= JZ_NAND_ECC_CTRL_RESET;
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reg |= JZ_NAND_ECC_CTRL_ENABLE;
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reg |= JZ_NAND_ECC_CTRL_RS;
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switch(mode) {
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case NAND_ECC_READ:
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reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
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is_reading = 1;
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break;
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case NAND_ECC_WRITE:
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reg |= JZ_NAND_ECC_CTRL_ENCODING;
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is_reading = 0;
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break;
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default:
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break;
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}
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REG_EMC_NFECR = reg;
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}
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/* Correct 1~9-bit errors in 512-bytes data */
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static void jz_rs_correct(unsigned char *dat, int idx, int mask)
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{
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int i;
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idx--;
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i = idx + (idx >> 3);
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if (i >= 512)
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return;
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mask <<= (idx & 0x7);
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dat[i] ^= mask & 0xff;
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if (i < 511)
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dat[i+1] ^= (mask >> 8) & 0xff;
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}
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static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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int k;
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uint32_t reg, status;
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volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
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/* Set PAR values */
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static uint8_t all_ff_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f};
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if (read_ecc[0] == 0xff &&
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read_ecc[1] == 0xff &&
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read_ecc[2] == 0xff &&
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read_ecc[3] == 0xff &&
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read_ecc[4] == 0xff &&
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read_ecc[5] == 0xff &&
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read_ecc[6] == 0xff &&
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read_ecc[7] == 0xff &&
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read_ecc[8] == 0xff) {
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for (k = 0; k < 9; k++)
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*(paraddr + k) = all_ff_ecc[k];
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} else {
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for (k = 0; k < 9; k++)
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*(paraddr + k) = read_ecc[k];
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}
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/* Set PRDY */
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REG_EMC_NFECR |= EMC_NFECR_PRDY;
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/* Wait for completion */
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do {
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status = REG_EMC_NFINTS;
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} while (!(status & EMC_NFINTS_DECF));
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__nand_ecc_disable();
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/* Check decoding */
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if (status & EMC_NFINTS_ERR) {
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if (status & EMC_NFINTS_UNCOR) {
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printk("uncorrectable ecc\n");
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while(1);
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return -1;
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}
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uint32_t errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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switch (errcnt) {
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case 4:
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jz_rs_correct(dat,
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(REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
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(REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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case 3:
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jz_rs_correct(dat,
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(REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
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(REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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case 2:
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jz_rs_correct(dat,
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(REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
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(REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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case 1:
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jz_rs_correct(dat,
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(REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
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(REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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return errcnt;
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default:
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break;
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}
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}
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return 0;
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}
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/*
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* Main initialization routine
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*/
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int board_nand_init(struct nand_chip *nand)
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{
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/* EMC setup, Set NFE bit */
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REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
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REG_EMC_SMCR1 = 0x094c4400;
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/* REG_EMC_SMCR3 = 0x04444400; */
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nand->IO_ADDR_R = JZ_NAND_DATA_ADDR;
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nand->IO_ADDR_W = JZ_NAND_DATA_ADDR;
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nand->cmd_ctrl = jz_nand_cmd_ctrl;
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nand->dev_ready = jz_nand_device_ready;
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nand->ecc.hwctl = jz_nand_hwctl;
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nand->ecc.correct = jz_nand_rs_correct_data;
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nand->ecc.calculate = jz_nand_rs_calculate_ecc;
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nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
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nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
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nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
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nand->ecc.layout = &qi_lb60_ecclayout_2gb;
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nand->chip_delay = 50;
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return 0;
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}
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#endif /* (CONFIG_CMD_NAND) */
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