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[adm8668] cleanup PCI controller code
At some point we should make the ADM5120 PCI controller driver a real platform driver and share that one between the two targets. Signed-off-by: Florian Fainelli <florian@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34553 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian
parent
822331ca3c
commit
b96a534bb2
@ -2,6 +2,6 @@
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# something witty --neutronscott
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#
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obj-y := irq.o pci.o prom.o platform.o proc.o \
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obj-y := irq.o prom.o platform.o proc.o \
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setup.o clock.o time.o early_printk.o \
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net_core.o net_intr.o
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@ -1,171 +0,0 @@
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/*
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* Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/pci.h>
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#include <adm8668.h>
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volatile u32* pci_config_address_reg = (volatile u32*)KSEG1ADDR(PCICFG_BASE);
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volatile u32* pci_config_data_reg = (volatile u32*)KSEG1ADDR(PCIDAT_BASE);
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#define PCI_ENABLE 0x80000000
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#define ADMPCI_IO_BASE 0x12600000
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#define ADMPCI_IO_SIZE 0x1fffff
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#define ADMPCI_MEM_BASE 0x16000000
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#define ADMPCI_MEM_SIZE 0x7ffffff
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#define PCI_CMM_IOACC_EN 0x1
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#define PCI_CMM_MEMACC_EN 0x2
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#define PCI_CMM_MASTER_EN 0x4
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#define PCI_CMM_DEF (PCI_CMM_IOACC_EN | PCI_CMM_MEMACC_EN | PCI_CMM_MASTER_EN)
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#define PCI_DEF_CACHE_LINE_SZ 0
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#define PCI_DEF_LATENCY_TIMER 0x20
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#define PCI_DEF_CACHE_LATENCY ((PCI_DEF_LATENCY_TIMER << 8) | PCI_DEF_CACHE_LINE_SZ)
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#define cfgaddr(bus, devfn, where) ( \
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(bus ? ((bus->number & 0xff) << 0x10) : 0) | \
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((devfn & 0xff) << 0x08) | \
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(where & 0xfc)) | PCI_ENABLE
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/* assumed little endian */
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static int adm8668_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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switch (size)
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{
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case 1:
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*pci_config_address_reg = cfgaddr(bus, devfn, where);
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*val = (le32_to_cpu(*pci_config_data_reg) >> ((where&3)<<3)) & 0xff;
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break;
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case 2:
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if (where & 1)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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*pci_config_address_reg = cfgaddr(bus, devfn, where);
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*val = (le32_to_cpu(*pci_config_data_reg) >> ((where&3)<<3)) & 0xffff;
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break;
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case 4:
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if (where & 3)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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*pci_config_address_reg = cfgaddr(bus, devfn, where);
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*val = le32_to_cpu(*pci_config_data_reg);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int adm8668_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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switch (size)
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{
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case 1:
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*pci_config_address_reg = cfgaddr(bus, devfn, where);
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*(volatile u8 *)(((int)pci_config_data_reg) + (where & 3)) = val;
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break;
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case 2:
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if (where & 1)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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*pci_config_address_reg = cfgaddr(bus, devfn, where);
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*(volatile u16 *)(((int)pci_config_data_reg) + (where & 2)) = val;
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break;
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case 4:
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if (where & 3)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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*pci_config_address_reg = cfgaddr(bus, devfn, where);
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*pci_config_data_reg = (val);
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}
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops adm8668_pci_ops = {
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.read = adm8668_read_config,
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.write = adm8668_write_config
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};
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struct resource pciioport_resource = {
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.name = "adm8668_pci",
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.start = ADMPCI_IO_BASE,
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.end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE,
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.flags = IORESOURCE_IO
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};
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struct resource pciiomem_resource = {
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.name = "adm8668_pci",
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.start = ADMPCI_MEM_BASE,
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.end = ADMPCI_MEM_BASE + ADMPCI_MEM_SIZE,
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.flags = IORESOURCE_MEM
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};
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#ifdef CONFIG_ADM8668_DISABLE_PCI
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struct pci_controller mips_pci_channels[] = {
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{ NULL, NULL, NULL , NULL , NULL}
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};
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#else
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struct pci_controller mips_pci_channels = {
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.pci_ops = &adm8668_pci_ops,
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.io_resource = &pciioport_resource,
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.mem_resource = &pciiomem_resource,
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};
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#endif
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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switch (slot)
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{
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case 1:
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return 14;
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case 2:
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return 13;
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case 3:
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return 12;
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default:
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return dev->irq;
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}
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static int __init adm8668_pci_init(void)
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{
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void __iomem *io_map_base;
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printk("adm8668_pci_init()\n");
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/* what's an io port? this is MIPS... *shrug* */
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ioport_resource.start = ADMPCI_IO_BASE;
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ioport_resource.end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE;
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io_map_base = ioremap(ADMPCI_IO_BASE, ADMPCI_IO_SIZE);
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if (!io_map_base)
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printk("io_map_base didn't work.\n");
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mips_pci_channels.io_map_base = (unsigned long)io_map_base;
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register_pci_controller(&mips_pci_channels);
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/* this needed? linksys' gpl 2.4 did it... */
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adm8668_write_config(NULL, 0, PCI_CACHE_LINE_SIZE, 2, 0);
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adm8668_write_config(NULL, 0, PCI_BASE_ADDRESS_0, 4, 0);
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adm8668_write_config(NULL, 0, PCI_BASE_ADDRESS_1, 4, 0);
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adm8668_write_config(NULL, 0, PCI_COMMAND, 4, PCI_CMM_DEF);
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return 0;
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}
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arch_initcall(adm8668_pci_init);
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@ -26,8 +26,8 @@
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#define ADM8668_SMEM0_BASE 0x1FC00000
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#define ADM8668_NAND_BASE 0x1FFFFF00
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#define PCICFG_BASE 0x12200000
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#define PCIDAT_BASE 0x12400000
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#define ADM8668_PCICFG_BASE 0x12200000
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#define ADM8668_PCIDAT_BASE 0x12400000
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/** onboard uart **/
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#define ADM8668_UARTCLK_FREQ 62500000
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200
target/linux/adm8668/files/arch/mips/pci/pci-adm8668.c
Normal file
200
target/linux/adm8668/files/arch/mips/pci/pci-adm8668.c
Normal file
@ -0,0 +1,200 @@
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/*
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* Copyright (C) 2010 Scott Nicholas <neutronscott@scottn.us>
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* Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Note that this controller is identical to the ADM5120 one
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <asm/byteorder.h>
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#include <asm/pci.h>
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#include <adm8668.h>
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static DEFINE_SPINLOCK(pci_lock);
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#define PCI_ENABLE 0x80000000
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#define ADMPCI_IO_BASE 0x12600000
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#define ADMPCI_IO_SIZE 0x1fffff
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#define ADMPCI_MEM_BASE 0x16000000
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#define ADMPCI_MEM_SIZE 0x7ffffff
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static inline void write_cfgaddr(u32 addr)
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{
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__raw_writel((addr | PCI_ENABLE),
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(void __iomem *)KSEG1ADDR(ADM8668_PCICFG_BASE));
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}
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static inline void write_cfgdata(u32 data)
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{
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__raw_writel(data, (void __iomem *)KSEG1ADDR(ADM8668_PCIDAT_BASE));
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}
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static inline u32 read_cfgdata(void)
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{
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return __raw_readl((void __iomem *)KSEG1ADDR(ADM8668_PCIDAT_BASE));
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}
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static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
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{
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return ((bus->number & 0xff) << 16) | ((devfn & 0xff) << 8) |
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(where & 0xfc);
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}
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static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus, devfn, where));
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data = read_cfgdata();
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xff;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xffff;
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break;
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}
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*val = data;
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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unsigned long flags;
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u32 data;
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int s;
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spin_lock_irqsave(&pci_lock, flags);
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write_cfgaddr(mkaddr(bus, devfn, where));
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data = read_cfgdata();
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switch (size) {
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case 1:
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s = ((where & 3) << 3);
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data &= ~(0xff << s);
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data |= ((val & 0xff) << s);
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break;
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case 2:
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s = ((where & 2) << 4);
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data &= ~(0xffff << s);
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data |= ((val & 0xffff) << s);
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break;
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case 4:
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data = val;
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break;
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}
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write_cfgdata(data);
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spin_unlock_irqrestore(&pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops adm8668_pci_ops = {
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.read = pci_read_config,
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.write = pci_write_config
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};
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struct resource pciioport_resource = {
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.name = "adm8668_pci",
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.start = ADMPCI_IO_BASE,
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.end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE,
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.flags = IORESOURCE_IO
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};
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struct resource pciiomem_resource = {
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.name = "adm8668_pci",
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.start = ADMPCI_MEM_BASE,
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.end = ADMPCI_MEM_BASE + ADMPCI_MEM_SIZE,
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.flags = IORESOURCE_MEM
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};
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struct pci_controller adm8668_pci_controller = {
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.pci_ops = &adm8668_pci_ops,
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.io_resource = &pciioport_resource,
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.mem_resource = &pciiomem_resource,
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};
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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switch (slot) {
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case 1:
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return 14;
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case 2:
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return 13;
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case 3:
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return 12;
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default:
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return dev->irq;
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}
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static void adm8668_pci_fixup(struct pci_dev *dev)
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{
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if (dev->devfn != 0)
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return;
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pr_info("PCI: fixing up ADM8668 controller\n");
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/* setup COMMAND register */
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pci_write_config_word(dev, PCI_COMMAND,
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(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* setup CACHE_LINE_SIZE register */
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
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/* setup BARS */
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
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}
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DECLARE_PCI_FIXUP_HEADER(0x1317, 0x8688, adm8668_pci_fixup);
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static int __init adm8668_pci_init(void)
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{
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void __iomem *io_map_base;
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ioport_resource.start = ADMPCI_IO_BASE;
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ioport_resource.end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE;
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io_map_base = ioremap(ADMPCI_IO_BASE, ADMPCI_IO_SIZE);
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if (!io_map_base)
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printk("io_map_base didn't work.\n");
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adm8668_pci_controller.io_map_base = (unsigned long)io_map_base;
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register_pci_controller(&adm8668_pci_controller);
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return 0;
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}
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arch_initcall(adm8668_pci_init);
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@ -36,7 +36,7 @@
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config BCM63XX
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bool "Broadcom BCM63XX based boards"
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select CEVT_R4K
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@@ -813,6 +833,7 @@ config NLM_XLP_BOARD
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@@ -813,6 +832,7 @@ config NLM_XLP_BOARD
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endchoice
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22
target/linux/adm8668/patches-3.3/002-adm8668_pci.patch
Normal file
22
target/linux/adm8668/patches-3.3/002-adm8668_pci.patch
Normal file
@ -0,0 +1,22 @@
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -57,6 +57,7 @@ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
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obj-$(CONFIG_CPU_XLR) += pci-xlr.o
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+obj-$(CONFIG_ADM8668) += pci-adm8668.o
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ifdef CONFIG_PCI_MSI
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
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--- a/include/linux/pci_ids.h
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+++ b/include/linux/pci_ids.h
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@@ -1803,6 +1803,9 @@
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#define PCI_VENDOR_ID_ESDGMBH 0x12fe
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#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
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+#define PCI_VENDOR_ADMTEK 0x1317
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+#define PCI_DEVICE_ID_ADM8668 0x8688
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+
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#define PCI_VENDOR_ID_SIIG 0x131f
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#define PCI_SUBVENDOR_ID_SIIG 0x131f
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#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
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