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add brcm47xx-2.6 fixes from #1496
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6639 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -235,6 +235,7 @@ static int ssb_attach_queued_buses(void)
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int i, err;
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list_for_each_entry_safe(bus, n, &attach_queue, list) {
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ssb_pcicore_init(&bus->pcicore);
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for (i = 0; i < bus->nr_devices; i++) {
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dev = &(bus->devices[i]);
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@ -350,7 +351,6 @@ static int ssb_bus_register(struct ssb_bus *bus,
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/* Initialize basic system devices (if available) */
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ssb_chipcommon_init(&bus->chipco);
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ssb_mipscore_init(&bus->mipscore);
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ssb_pcicore_init(&bus->pcicore);
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/* Queue it for attach */
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list_add_tail(&bus->list, &attach_queue);
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@ -266,6 +266,35 @@ void ssb_chipco_resume(struct ssb_chipcommon *cc)
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chipco_powercontrol_init(cc);
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}
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void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 chip_id, u32 *rate,
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u32 *plltype, u32 *n, u32 *m)
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{
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*rate = 0;
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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switch (*plltype) {
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case SSB_PLLTYPE_2:
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case SSB_PLLTYPE_4:
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case SSB_PLLTYPE_6:
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case SSB_PLLTYPE_7:
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
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break;
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case SSB_PLLTYPE_5:
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*rate = 200000000;
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break;
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case SSB_PLLTYPE_3:
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/* 5350 uses m2 to control mips */
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
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break;
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default:
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*m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
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break;
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}
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if (*rate == 0 && chip_id == 0x5365)
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*rate = 200000000;
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}
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void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m)
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{
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@ -215,15 +215,14 @@ u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
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if (bus->extif.dev) {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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} else if (bus->chipco.dev) {
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if (bus->chip_id == 0x5365)
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/* FIXME: is this override really necessary? */
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return 200000000;
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ssb_chipco_get_clockcontrol(&bus->chipco, &pll_type, &n, &m);
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ssb_chipco_get_clockcpu(&bus->chipco, bus->chip_id, &rate,
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&pll_type, &n, &m);
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} else
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return 0;
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rate = ssb_calc_clock_rate(pll_type, n, m);
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if (rate == 0)
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rate = ssb_calc_clock_rate(pll_type, n, m);
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if (pll_type == SSB_PLLTYPE_6)
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rate *= 2;
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@ -303,6 +303,8 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
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udelay(150);
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val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
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pcicore_write32(pc, SSB_PCICORE_CTL, val);
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val = SSB_PCICORE_ARBCTL_INTERN;
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pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
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udelay(1);
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//TODO cardbus mode
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@ -329,6 +331,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
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* The following needs change, if we want to port hostmode
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* to non-MIPS platform. */
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set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
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mdelay(300);
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register_pci_controller(&ssb_pcicore_controller);
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}
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@ -364,6 +364,8 @@ extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
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extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
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extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
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extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 chip_id,
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u32 *rate, u32 *plltype, u32 *n, u32 *m);
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extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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u32 *plltype, u32 *n, u32 *m);
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extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
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