qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-11-27 16:10:39 +02:00
Code

get rid of even more 2.6.28 stuff

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@18953 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
kaloz 2009-12-27 21:35:42 +00:00
parent b281497b69
commit be8ce37ea9
54 changed files with 1 additions and 76337 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/image.mk
View File

@ -23,7 +23,7 @@ JFFS2OPTS := --pad --big-endian --squash
SQUASHFS_OPTS := -be
endif
ifneq ($(CONFIG_LINUX_2_4)$(CONFIG_LINUX_2_6_21)$(CONFIG_LINUX_2_6_25)$(CONFIG_LINUX_2_6_28),)
ifneq ($(CONFIG_LINUX_2_4)$(CONFIG_LINUX_2_6_21)$(CONFIG_LINUX_2_6_25),)
USE_SQUASHFS3 := y
endif

3
include/kernel-version.mk
View File

@ -16,9 +16,6 @@ endif
ifeq ($(LINUX_VERSION),2.6.25.20)
LINUX_KERNEL_MD5SUM:=0da698edccf03e2235abc2830a495114
endif
ifeq ($(LINUX_VERSION),2.6.28.10)
LINUX_KERNEL_MD5SUM:=c4efb2c494d749cb5de274f8ae41c3fa
endif
ifeq ($(LINUX_VERSION),2.6.30.10)
LINUX_KERNEL_MD5SUM:=eb6be465f914275967a5602cb33662f5
endif

200
target/linux/adm5120/router_be/config-2.6.28
View File

@ -1,200 +0,0 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_ADM5120_ENET=y
# CONFIG_ADM5120_MACH_5GXI is not set
CONFIG_ADM5120_MACH_P_334WT=y
CONFIG_ADM5120_MACH_P_335=y
# CONFIG_ADM5120_OEM_CELLVISION is not set
# CONFIG_ADM5120_OEM_COMPEX is not set
# CONFIG_ADM5120_OEM_EDIMAX is not set
# CONFIG_ADM5120_OEM_INFINEON is not set
# CONFIG_ADM5120_OEM_MIKROTIK is not set
# CONFIG_ADM5120_OEM_MOTOROLA is not set
# CONFIG_ADM5120_OEM_OSBRIDGE is not set
CONFIG_ADM5120_OEM_ZYXEL=y
CONFIG_ADM5120_SOC_BGA=y
CONFIG_ADM5120_WDT=y
CONFIG_ADM5120=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_AMBA=y
# CONFIG_BCM47XX is not set
CONFIG_BINFMT_MISC=m
CONFIG_BITREVERSE=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CEVT_R4K=y
CONFIG_CLASSIC_RCU=y
CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,jffs2"
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CSRC_R4K=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_ELF_CORE=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_FS_POSIX_ACL=y
CONFIG_GENERIC_ACL=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HID_COMPAT=y
CONFIG_HID=m
CONFIG_HID_SUPPORT=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
# CONFIG_HZ_100 is not set
CONFIG_HZ=250
CONFIG_HZ_250=y
# CONFIG_IDE is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INOTIFY_USER=y
CONFIG_INOTIFY=y
# CONFIG_INPUT_GPIO_BUTTONS is not set
CONFIG_INPUT=m
# CONFIG_INPUT_YEALINK is not set
CONFIG_IRQ_CPU=y
# CONFIG_ISDN is not set
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LEGACY_PTYS=y
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_EMMA is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_MII=m
# CONFIG_MIKROTIK_RB532 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MIPS_FPU_EMU is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MIPS=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MTD_ADM5120=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_TRXSPLIT=y
# CONFIG_NET_PCI is not set
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PROBE_INITRD_HEADER is not set
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
CONFIG_SERIAL_AMBA_PL010=y
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_PCIPS2 is not set
# CONFIG_SERIO_RAW is not set
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SOFT_WATCHDOG=m
CONFIG_SWAP_IO_SPACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TRAD_SIGNALS=y
CONFIG_USB_ADM5120_HCD=m
CONFIG_USB_DEBUG=y
CONFIG_USB_EHCI_HCD=m
CONFIG_USB=m
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_VGASTATE is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_ZONE_DMA_FLAG=0

254
target/linux/adm5120/router_le/config-2.6.28
View File

@ -1,254 +0,0 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
# CONFIG_8139TOO is not set
CONFIG_ADM5120_ENET=y
CONFIG_ADM5120_MACH_5GXI=y
CONFIG_ADM5120_MACH_BR_6104KP=y
CONFIG_ADM5120_MACH_BR_6104K=y
CONFIG_ADM5120_MACH_BR_61X4WG=y
CONFIG_ADM5120_MACH_CAS_771=y
CONFIG_ADM5120_MACH_EASY5120P_ATA=y
CONFIG_ADM5120_MACH_EASY5120_RT=y
CONFIG_ADM5120_MACH_EASY5120_WVOIP=y
CONFIG_ADM5120_MACH_EASY83000=y
CONFIG_ADM5120_MACH_NFS_101=y
CONFIG_ADM5120_MACH_NP27G=y
CONFIG_ADM5120_MACH_NP28G=y
CONFIG_ADM5120_MACH_PMUGW=y
CONFIG_ADM5120_MACH_RB_11X=y
CONFIG_ADM5120_MACH_RB_133C=y
CONFIG_ADM5120_MACH_RB_133=y
CONFIG_ADM5120_MACH_RB_150=y
CONFIG_ADM5120_MACH_RB_153=y
CONFIG_ADM5120_MACH_RB_192=y
CONFIG_ADM5120_MACH_WP54=y
CONFIG_ADM5120_OEM_CELLVISION=y
CONFIG_ADM5120_OEM_COMPEX=y
CONFIG_ADM5120_OEM_EDIMAX=y
CONFIG_ADM5120_OEM_INFINEON=y
CONFIG_ADM5120_OEM_MIKROTIK=y
CONFIG_ADM5120_OEM_MOTOROLA=y
CONFIG_ADM5120_OEM_OSBRIDGE=y
# CONFIG_ADM5120_OEM_ZYXEL is not set
CONFIG_ADM5120_SOC_BGA=y
CONFIG_ADM5120_WDT=y
CONFIG_ADM5120=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_AMBA=y
CONFIG_ATA=m
# CONFIG_BCM47XX is not set
CONFIG_BITREVERSE=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CEVT_R4K=y
CONFIG_CLASSIC_RCU=y
CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2"
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CRYPTO_AEAD2=m
CONFIG_CRYPTO_ALGAPI2=m
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLKCIPHER2=m
CONFIG_CRYPTO_BLKCIPHER=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_HASH2=m
CONFIG_CRYPTO_MANAGER2=m
CONFIG_CRYPTO_MANAGER=m
CONFIG_CRYPTO_RNG2=m
CONFIG_CSRC_R4K=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_ELF_CORE=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_FS_POSIX_ACL=y
CONFIG_GENERIC_ACL=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HAMRADIO is not set
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HID_COMPAT=y
CONFIG_HID=m
CONFIG_HID_SUPPORT=y
# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP=m
CONFIG_HOSTAP_PCI=m
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
# CONFIG_HZ_100 is not set
CONFIG_HZ=250
CONFIG_HZ_250=y
# CONFIG_IDE is not set
CONFIG_IEEE80211_CRYPT_WEP=m
CONFIG_IEEE80211=m
CONFIG_IMAGE_CMDLINE_HACK=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INOTIFY_USER=y
CONFIG_INOTIFY=y
# CONFIG_INPUT_GPIO_BUTTONS is not set
CONFIG_INPUT=m
# CONFIG_INPUT_YEALINK is not set
CONFIG_IRQ_CPU=y
# CONFIG_ISDN is not set
CONFIG_KEXEC=y
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_TRIGGER_ADM5120_SWITCH=m
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LEGACY_PTYS=y
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_EMMA is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_MII=m
# CONFIG_MIKROTIK_RB532 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MIPS_FPU_EMU is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MIPS=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MTD_ADM5120=y
CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_MYLOADER_PARTS=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_TRXSPLIT=y
CONFIG_NO_HZ=y
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PATA_RB153_CF=m
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PROBE_INITRD_HEADER is not set
# CONFIG_R6040 is not set
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_SCSI=m
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2
CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS"
CONFIG_SERIAL_AMBA_PL010=y
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_LIBPS2 is not set
# CONFIG_SERIO_PCIPS2 is not set
# CONFIG_SERIO_RAW is not set
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SOFT_WATCHDOG=m
# CONFIG_SWAP is not set
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
# CONFIG_TC35815 is not set
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TRAD_SIGNALS=y
CONFIG_USB_ADM5120_HCD=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB=m
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIA_RHINE is not set
CONFIG_VLAN_8021Q=m
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_YAFFS_9BYTE_TAGS=y
# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
CONFIG_YAFFS_FS=y
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_YAFFS_YAFFS1=y
CONFIG_YAFFS_YAFFS2=y
CONFIG_ZONE_DMA_FLAG=0

0
target/linux/ifxmips/nfs/config-2.6.28 → target/linux/ifxmips/nfs/config-default
View File

11
target/linux/ixp4xx/patches-2.6.28/010-ixp43x_pci_fixup.patch
View File

@ -1,11 +0,0 @@
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -18,7 +18,7 @@
#define __ASM_ARCH_HARDWARE_H__
#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
+#define PCIBIOS_MIN_MEM 0x48000000
/*
* We override the standard dma-mask routines for bouncing.

420
target/linux/ixp4xx/patches-2.6.28/020-gateworks_i2c_pld.patch
View File

@ -1,420 +0,0 @@
--- /dev/null
+++ b/drivers/gpio/gw_i2c_pld.c
@@ -0,0 +1,370 @@
+/*
+ * Gateworks I2C PLD GPIO expander
+ *
+ * Copyright (C) 2009 Gateworks Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/i2c/gw_i2c_pld.h>
+#include <asm/gpio.h>
+
+static const struct i2c_device_id gw_i2c_pld_id[] = {
+ { "gw_i2c_pld", 8 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, gw_i2c_pld_id);
+
+/*
+ * The Gateworks I2C PLD chip only expose one read and one
+ * write register. Writing a "one" bit (to match the reset state) lets
+ * that pin be used as an input. It is an open-drain model.
+ */
+
+struct gw_i2c_pld {
+ struct gpio_chip chip;
+ struct i2c_client *client;
+ unsigned out; /* software latch */
+};
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * The Gateworks I2C PLD chip does not properly send the acknowledge bit
+ * thus we cannot use standard i2c_smbus functions. We have recreated
+ * our own here, but we still use the mutex_lock to lock the i2c_bus
+ * as the device still exists on the I2C bus.
+*/
+
+#define PLD_SCL_GPIO 6
+#define PLD_SDA_GPIO 7
+
+#define SCL_LO() gpio_line_set(PLD_SCL_GPIO, IXP4XX_GPIO_LOW)
+#define SCL_HI() gpio_line_set(PLD_SCL_GPIO, IXP4XX_GPIO_HIGH)
+#define SCL_EN() gpio_line_config(PLD_SCL_GPIO, IXP4XX_GPIO_OUT)
+#define SDA_LO() gpio_line_set(PLD_SDA_GPIO, IXP4XX_GPIO_LOW)
+#define SDA_HI() gpio_line_set(PLD_SDA_GPIO, IXP4XX_GPIO_HIGH)
+#define SDA_EN() gpio_line_config(PLD_SDA_GPIO, IXP4XX_GPIO_OUT)
+#define SDA_DIS() gpio_line_config(PLD_SDA_GPIO, IXP4XX_GPIO_IN)
+#define SDA_IN(x) gpio_line_get(PLD_SDA_GPIO, &x);
+
+static int i2c_pld_write_byte(int address, int byte)
+{
+ int i;
+
+ address = (address << 1) & ~0x1;
+
+ SDA_HI();
+ SDA_EN();
+ SCL_EN();
+ SCL_HI();
+ SDA_LO();
+ SCL_LO();
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (address & (1 << i))
+ SDA_HI();
+ else
+ SDA_LO();
+
+ SCL_HI();
+ SCL_LO();
+ }
+
+ SDA_DIS();
+ SCL_HI();
+ SDA_IN(i);
+ SCL_LO();
+ SDA_EN();
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (byte & (1 << i))
+ SDA_HI();
+ else
+ SDA_LO();
+ SCL_HI();
+ SCL_LO();
+ }
+
+ SDA_DIS();
+ SCL_HI();
+ SDA_IN(i);
+ SCL_LO();
+
+ SDA_HI();
+ SDA_EN();
+
+ SDA_LO();
+ SCL_HI();
+ SDA_HI();
+ SCL_LO();
+ SCL_HI();
+
+ return 0;
+}
+
+static unsigned int i2c_pld_read_byte(int address)
+{
+ int i = 0, byte = 0;
+ int bit;
+
+ address = (address << 1) | 0x1;
+
+ SDA_HI();
+ SDA_EN();
+ SCL_EN();
+ SCL_HI();
+ SDA_LO();
+ SCL_LO();
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (address & (1 << i))
+ SDA_HI();
+ else
+ SDA_LO();
+
+ SCL_HI();
+ SCL_LO();
+ }
+
+ SDA_DIS();
+ SCL_HI();
+ SDA_IN(i);
+ SCL_LO();
+ SDA_EN();
+
+ SDA_DIS();
+ for (i = 7; i >= 0; i--)
+ {
+ SCL_HI();
+ SDA_IN(bit);
+ byte |= bit << i;
+ SCL_LO();
+ }
+
+ SDA_LO();
+ SCL_HI();
+ SDA_HI();
+ SCL_LO();
+ SCL_HI();
+
+ return byte;
+}
+
+
+static int gw_i2c_pld_input8(struct gpio_chip *chip, unsigned offset)
+{
+ int ret;
+ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip);
+ struct i2c_adapter *adap = gpio->client->adapter;
+
+ if (in_atomic() || irqs_disabled()) {
+ ret = mutex_trylock(&adap->bus_lock);
+ if (!ret)
+ /* I2C activity is ongoing. */
+ return -EAGAIN;
+ } else {
+ mutex_lock_nested(&adap->bus_lock, adap->level);
+ }
+
+ gpio->out |= (1 << offset);
+
+ ret = i2c_pld_write_byte(gpio->client->addr, gpio->out);
+
+ mutex_unlock(&adap->bus_lock);
+
+ return ret;
+}
+
+static int gw_i2c_pld_get8(struct gpio_chip *chip, unsigned offset)
+{
+ int ret;
+ s32 value;
+ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip);
+ struct i2c_adapter *adap = gpio->client->adapter;
+
+ if (in_atomic() || irqs_disabled()) {
+ ret = mutex_trylock(&adap->bus_lock);
+ if (!ret)
+ /* I2C activity is ongoing. */
+ return -EAGAIN;
+ } else {
+ mutex_lock_nested(&adap->bus_lock, adap->level);
+ }
+
+ value = i2c_pld_read_byte(gpio->client->addr);
+
+ mutex_unlock(&adap->bus_lock);
+
+ return (value < 0) ? 0 : (value & (1 << offset));
+}
+
+static int gw_i2c_pld_output8(struct gpio_chip *chip, unsigned offset, int value)
+{
+ int ret;
+
+ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip);
+ struct i2c_adapter *adap = gpio->client->adapter;
+
+ unsigned bit = 1 << offset;
+
+ if (in_atomic() || irqs_disabled()) {
+ ret = mutex_trylock(&adap->bus_lock);
+ if (!ret)
+ /* I2C activity is ongoing. */
+ return -EAGAIN;
+ } else {
+ mutex_lock_nested(&adap->bus_lock, adap->level);
+ }
+
+
+ if (value)
+ gpio->out |= bit;
+ else
+ gpio->out &= ~bit;
+
+ ret = i2c_pld_write_byte(gpio->client->addr, gpio->out);
+
+ mutex_unlock(&adap->bus_lock);
+
+ return ret;
+}
+
+static void gw_i2c_pld_set8(struct gpio_chip *chip, unsigned offset, int value)
+{
+ gw_i2c_pld_output8(chip, offset, value);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int gw_i2c_pld_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct gw_i2c_pld_platform_data *pdata;
+ struct gw_i2c_pld *gpio;
+ int status;
+
+ pdata = client->dev.platform_data;
+ if (!pdata)
+ return -ENODEV;
+
+ /* Allocate, initialize, and register this gpio_chip. */
+ gpio = kzalloc(sizeof *gpio, GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+
+ gpio->chip.base = pdata->gpio_base;
+ gpio->chip.can_sleep = 1;
+ gpio->chip.dev = &client->dev;
+ gpio->chip.owner = THIS_MODULE;
+
+ gpio->chip.ngpio = pdata->nr_gpio;
+ gpio->chip.direction_input = gw_i2c_pld_input8;
+ gpio->chip.get = gw_i2c_pld_get8;
+ gpio->chip.direction_output = gw_i2c_pld_output8;
+ gpio->chip.set = gw_i2c_pld_set8;
+
+ gpio->chip.label = client->name;
+
+ gpio->client = client;
+ i2c_set_clientdata(client, gpio);
+
+ gpio->out = 0xFF;
+
+ status = gpiochip_add(&gpio->chip);
+ if (status < 0)
+ goto fail;
+
+ dev_info(&client->dev, "gpios %d..%d on a %s%s\n",
+ gpio->chip.base,
+ gpio->chip.base + gpio->chip.ngpio - 1,
+ client->name,
+ client->irq ? " (irq ignored)" : "");
+
+ /* Let platform code set up the GPIOs and their users.
+ * Now is the first time anyone could use them.
+ */
+ if (pdata->setup) {
+ status = pdata->setup(client,
+ gpio->chip.base, gpio->chip.ngpio,
+ pdata->context);
+ if (status < 0)
+ dev_warn(&client->dev, "setup --> %d\n", status);
+ }
+
+ return 0;
+
+fail:
+ dev_dbg(&client->dev, "probe error %d for '%s'\n",
+ status, client->name);
+ kfree(gpio);
+ return status;
+}
+
+static int gw_i2c_pld_remove(struct i2c_client *client)
+{
+ struct gw_i2c_pld_platform_data *pdata = client->dev.platform_data;
+ struct gw_i2c_pld *gpio = i2c_get_clientdata(client);
+ int status = 0;
+
+ if (pdata->teardown) {
+ status = pdata->teardown(client,
+ gpio->chip.base, gpio->chip.ngpio,
+ pdata->context);
+ if (status < 0) {
+ dev_err(&client->dev, "%s --> %d\n",
+ "teardown", status);
+ return status;
+ }
+ }
+
+ status = gpiochip_remove(&gpio->chip);
+ if (status == 0)
+ kfree(gpio);
+ else
+ dev_err(&client->dev, "%s --> %d\n", "remove", status);
+ return status;
+}
+
+static struct i2c_driver gw_i2c_pld_driver = {
+ .driver = {
+ .name = "gw_i2c_pld",
+ .owner = THIS_MODULE,
+ },
+ .probe = gw_i2c_pld_probe,
+ .remove = gw_i2c_pld_remove,
+ .id_table = gw_i2c_pld_id,
+};
+
+static int __init gw_i2c_pld_init(void)
+{
+ return i2c_add_driver(&gw_i2c_pld_driver);
+}
+module_init(gw_i2c_pld_init);
+
+static void __exit gw_i2c_pld_exit(void)
+{
+ i2c_del_driver(&gw_i2c_pld_driver);
+}
+module_exit(gw_i2c_pld_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Chris Lang");
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -160,6 +160,14 @@ config GPIO_BT8XX
If unsure, say N.
+config GPIO_GW_I2C_PLD
+ tristate "Gateworks I2C PLD GPIO Expander"
+ depends on I2C
+ help
+ Say yes here to provide access to the Gateworks I2C PLD GPIO
+ Expander. This is used at least on the GW2358-4.
+
+
comment "SPI GPIO expanders:"
config GPIO_MAX7301
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o
obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o
obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o
+obj-$(CONFIG_GPIO_GW_I2C_PLD) += gw_i2c_pld.o
--- /dev/null
+++ b/include/linux/i2c/gw_i2c_pld.h
@@ -0,0 +1,20 @@
+#ifndef __LINUX_GW_I2C_PLD_H
+#define __LINUX_GW_I2C_PLD_H
+
+/**
+ * The Gateworks I2C PLD Implements an additional 8 bits of GPIO through the PLD
+ */
+
+struct gw_i2c_pld_platform_data {
+ unsigned gpio_base;
+ unsigned nr_gpio;
+ int (*setup)(struct i2c_client *client,
+ int gpio, unsigned ngpio,
+ void *context);
+ int (*teardown)(struct i2c_client *client,
+ int gpio, unsigned ngpio,
+ void *context);
+ void *context;
+};
+
+#endif /* __LINUX_GW_I2C_PLD_H */

15
target/linux/ixp4xx/patches-2.6.28/090-increase_entropy_pools.patch
View File

@ -1,15 +0,0 @@
--- a/drivers/char/random.c
+++ b/drivers/char/random.c
@@ -259,9 +259,9 @@
/*
* Configuration information
*/
-#define INPUT_POOL_WORDS 128
-#define OUTPUT_POOL_WORDS 32
-#define SEC_XFER_SIZE 512
+#define INPUT_POOL_WORDS 256
+#define OUTPUT_POOL_WORDS 64
+#define SEC_XFER_SIZE 1024
/*
* The minimum number of bits of entropy before we wake up a read on

68
target/linux/ixp4xx/patches-2.6.28/100-wg302v2_gateway7001_mac_plat_info.patch
View File

@ -1,68 +0,0 @@
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -76,9 +76,35 @@ static struct platform_device gateway700
.resource = &gateway7001_uart_resource,
};
+static struct eth_plat_info gateway7001_plat_eth[] = {
+ {
+ .phy = 1,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 2,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device gateway7001_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = gateway7001_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = gateway7001_plat_eth + 1,
+ }
+};
+
static struct platform_device *gateway7001_devices[] __initdata = {
&gateway7001_flash,
- &gateway7001_uart
+ &gateway7001_uart,
+ &gateway7001_eth[0],
+ &gateway7001_eth[1],
};
static void __init gateway7001_init(void)
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -77,9 +77,26 @@ static struct platform_device wg302v2_ua
.resource = &wg302v2_uart_resource,
};
+static struct eth_plat_info wg302v2_plat_eth[] = {
+ {
+ .phy = 8,
+ .rxq = 3,
+ .txreadyq = 20,
+ }
+};
+
+static struct platform_device wg302v2_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = wg302v2_plat_eth,
+ }
+};
+
static struct platform_device *wg302v2_devices[] __initdata = {
&wg302v2_flash,
&wg302v2_uart,
+ &wg302v2_eth[0],
};
static void __init wg302v2_init(void)

257
target/linux/ixp4xx/patches-2.6.28/105-wg302v1_support.patch
View File

@ -1,257 +0,0 @@
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -155,6 +155,7 @@ CONFIG_MACH_AVILA=y
CONFIG_MACH_LOFT=y
CONFIG_ARCH_ADI_COYOTE=y
CONFIG_MACH_GATEWAY7001=y
+CONFIG_MACH_WG302V1=y
CONFIG_MACH_WG302V2=y
CONFIG_ARCH_IXDP425=y
CONFIG_MACH_IXDPG425=y
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -49,6 +49,14 @@ config MACH_GATEWAY7001
7001 Access Point. For more information on this platform,
see http://openwrt.org
+config MACH_WG302V1
+ bool "Netgear WG302 v1 / WAG302 v1"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support Netgear's
+ WG302 v1 or WAG302 v1 Access Points. For more information
+ on this platform, see http://openwrt.org
+
config MACH_WG302V2
bool "Netgear WG302 v2 / WAG302 v2"
select PCI
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -14,6 +14,7 @@ obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-p
obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o
obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
+obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o
obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
@@ -28,6 +29,7 @@ obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.
obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
+obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o
obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
obj-$(CONFIG_MACH_FSG) += fsg-setup.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/wg302v1-pci.c
@@ -0,0 +1,64 @@
+/*
+ * arch/arch/mach-ixp4xx/wg302v1-pci.c
+ *
+ * PCI setup routines for the Netgear WG302 v1 and WAG302 v1
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-pci.c:
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Software, Inc.
+ *
+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include <asm/mach/pci.h>
+
+void __init wg302v1_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init wg302v1_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 1)
+ return IRQ_IXP4XX_GPIO8;
+ else if (slot == 2)
+ return IRQ_IXP4XX_GPIO10;
+ else
+ return -1;
+}
+
+struct hw_pci wg302v1_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = wg302v1_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = wg302v1_map_irq,
+};
+
+int __init wg302v1_pci_init(void)
+{
+ if (machine_is_wg302v1())
+ pci_common_init(&wg302v1_pci);
+ return 0;
+}
+
+subsys_initcall(wg302v1_pci_init);
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c
@@ -0,0 +1,142 @@
+/*
+ * arch/arm/mach-ixp4xx/wg302v1-setup.c
+ *
+ * Board setup for the Netgear WG302 v1 and WAG302 v1
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <kaloz@openwrt.org>
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/memory.h>
+
+#include <asm/setup.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data wg302v1_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource wg302v1_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device wg302v1_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &wg302v1_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &wg302v1_flash_resource,
+};
+
+static struct resource wg302v1_uart_resources[] = {
+ {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct plat_serial8250_port wg302v1_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device wg302v1_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = wg302v1_uart_data,
+ },
+ .num_resources = 2,
+ .resource = wg302v1_uart_resources,
+};
+
+static struct eth_plat_info wg302v1_plat_eth[] = {
+ {
+ .phy = 30,
+ .rxq = 3,
+ .txreadyq = 20,
+ }
+};
+
+static struct platform_device wg302v1_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = wg302v1_plat_eth,
+ }
+};
+
+static struct platform_device *wg302v1_devices[] __initdata = {
+ &wg302v1_flash,
+ &wg302v1_uart,
+ &wg302v1_eth[0],
+};
+
+static void __init wg302v1_init(void)
+{
+ ixp4xx_sys_init();
+
+ wg302v1_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ wg302v1_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+ platform_add_devices(wg302v1_devices, ARRAY_SIZE(wg302v1_devices));
+}
+
+#ifdef CONFIG_MACH_WG302V1
+MACHINE_START(WG302V1, "Netgear WG302 v1 / WAG302 v1")
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = wg302v1_init,
+MACHINE_END
+#endif

387
target/linux/ixp4xx/patches-2.6.28/110-pronghorn_series_support.patch
View File

@ -1,387 +0,0 @@
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -157,6 +157,8 @@ CONFIG_ARCH_ADI_COYOTE=y
CONFIG_MACH_GATEWAY7001=y
CONFIG_MACH_WG302V1=y
CONFIG_MACH_WG302V2=y
+CONFIG_MACH_PRONGHORN=y
+CONFIG_MACH_PRONGHORNMETRO=y
CONFIG_ARCH_IXDP425=y
CONFIG_MACH_IXDPG425=y
CONFIG_MACH_IXDP465=y
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -65,6 +65,22 @@ config MACH_WG302V2
WG302 v2 or WAG302 v2 Access Points. For more information
on this platform, see http://openwrt.org
+config MACH_PRONGHORN
+ bool "ADI Pronghorn series"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support the ADI
+ Engineering Pronghorn series. For more
+ information on this platform, see http://www.adiengineering.com
+
+#
+# There're only minimal differences kernel-wise between the Pronghorn and
+# Pronghorn Metro boards - they use different chip selects to drive the
+# CF slot connected to the expansion bus, so we just enable them together.
+#
+config MACH_PRONGHORNMETRO
+ def_bool MACH_PRONGHORN
+
config ARCH_IXDP425
bool "IXDP425"
help
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -17,6 +17,7 @@ obj-pci-$(CONFIG_MACH_GATEWAY7001) += ga
obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o
obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
obj-y += common.o
@@ -32,6 +33,7 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gatewa
obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o
obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/pronghorn-pci.c
@@ -0,0 +1,70 @@
+/*
+ * arch/arch/mach-ixp4xx/pronghorn-pci.c
+ *
+ * PCI setup routines for ADI Engineering Pronghorn series
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-pci.c:
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include <asm/mach/pci.h>
+
+void __init pronghorn_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init pronghorn_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 13)
+ return IRQ_IXP4XX_GPIO4;
+ else if (slot == 14)
+ return IRQ_IXP4XX_GPIO6;
+ else if (slot == 15)
+ return IRQ_IXP4XX_GPIO11;
+ else if (slot == 16)
+ return IRQ_IXP4XX_GPIO1;
+ else
+ return -1;
+}
+
+struct hw_pci pronghorn_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = pronghorn_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = pronghorn_map_irq,
+};
+
+int __init pronghorn_pci_init(void)
+{
+ if (machine_is_pronghorn() || machine_is_pronghorn_metro())
+ pci_common_init(&pronghorn_pci);
+ return 0;
+}
+
+subsys_initcall(pronghorn_pci_init);
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c
@@ -0,0 +1,245 @@
+/*
+ * arch/arm/mach-ixp4xx/pronghorn-setup.c
+ *
+ * Board setup for the ADI Engineering Pronghorn series
+ *
+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <Kaloz@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/memory.h>
+#include <linux/i2c-gpio.h>
+#include <linux/leds.h>
+
+#include <asm/setup.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data pronghorn_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource pronghorn_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pronghorn_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &pronghorn_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &pronghorn_flash_resource,
+};
+
+static struct resource pronghorn_uart_resources [] = {
+ {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct plat_serial8250_port pronghorn_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device pronghorn_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = pronghorn_uart_data,
+ },
+ .num_resources = 2,
+ .resource = pronghorn_uart_resources,
+};
+
+static struct i2c_gpio_platform_data pronghorn_i2c_gpio_data = {
+ .sda_pin = 9,
+ .scl_pin = 10,
+};
+
+static struct platform_device pronghorn_i2c_gpio = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &pronghorn_i2c_gpio_data,
+ },
+};
+
+static struct gpio_led pronghorn_led_pin[] = {
+ {
+ .name = "pronghorn:green:status",
+ .gpio = 7,
+ }
+};
+
+static struct gpio_led_platform_data pronghorn_led_data = {
+ .num_leds = 1,
+ .leds = pronghorn_led_pin,
+};
+
+static struct platform_device pronghorn_led = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &pronghorn_led_data,
+};
+
+static struct resource pronghorn_pata_resources[] = {
+ {
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "intrq",
+ .start = IRQ_IXP4XX_GPIO0,
+ .end = IRQ_IXP4XX_GPIO0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct ixp4xx_pata_data pronghorn_pata_data = {
+ .cs0_bits = 0xbfff0043,
+ .cs1_bits = 0xbfff0043,
+};
+
+static struct platform_device pronghorn_pata = {
+ .name = "pata_ixp4xx_cf",
+ .id = 0,
+ .dev.platform_data = &pronghorn_pata_data,
+ .num_resources = ARRAY_SIZE(pronghorn_pata_resources),
+ .resource = pronghorn_pata_resources,
+};
+
+static struct eth_plat_info pronghorn_plat_eth[] = {
+ {
+ .phy = 0,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 1,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device pronghorn_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = pronghorn_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = pronghorn_plat_eth + 1,
+ }
+};
+
+static struct platform_device *pronghorn_devices[] __initdata = {
+ &pronghorn_flash,
+ &pronghorn_uart,
+ &pronghorn_led,
+ &pronghorn_eth[0],
+ &pronghorn_eth[1],
+};
+
+static void __init pronghorn_init(void)
+{
+ ixp4xx_sys_init();
+
+ pronghorn_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ pronghorn_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+ platform_add_devices(pronghorn_devices, ARRAY_SIZE(pronghorn_devices));
+
+ if (machine_is_pronghorn()) {
+ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(2);
+ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(2);
+
+ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(3);
+ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(3);
+
+ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS2;
+ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
+ } else {
+ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(3);
+ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(3);
+
+ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(4);
+ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(4);
+
+ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
+ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS4;
+
+ platform_device_register(&pronghorn_i2c_gpio);
+ }
+
+ platform_device_register(&pronghorn_pata);
+}
+
+MACHINE_START(PRONGHORN, "ADI Engineering Pronghorn")
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = pronghorn_init,
+MACHINE_END
+
+MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro")
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = pronghorn_init,
+MACHINE_END
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -41,7 +41,8 @@ static __inline__ void __arch_decomp_set
* Some boards are using UART2 as console
*/
if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
- machine_is_gateway7001() || machine_is_wg302v2())
+ machine_is_gateway7001() || machine_is_wg302v2() ||
+ machine_is_pronghorn() || machine_is_pronghorn_metro())
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;

44
target/linux/ixp4xx/patches-2.6.28/111-pronghorn_swap_uarts.patch
View File

@ -1,44 +0,0 @@
--- a/arch/arm/mach-ixp4xx/pronghorn-setup.c
+++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c
@@ -51,31 +51,31 @@ static struct platform_device pronghorn_
static struct resource pronghorn_uart_resources [] = {
{
- .start = IXP4XX_UART1_BASE_PHYS,
- .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM
},
{
- .start = IXP4XX_UART2_BASE_PHYS,
- .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM
}
};
static struct plat_serial8250_port pronghorn_uart_data[] = {
{
- .mapbase = IXP4XX_UART1_BASE_PHYS,
- .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
- .irq = IRQ_IXP4XX_UART1,
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
- .mapbase = IXP4XX_UART2_BASE_PHYS,
- .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
- .irq = IRQ_IXP4XX_UART2,
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,

282
target/linux/ixp4xx/patches-2.6.28/115-sidewinder_support.patch
View File

@ -1,282 +0,0 @@
From 60bdaaaf3446b4237566c6e04855186fc7bd766b Mon Sep 17 00:00:00 2001
From: Imre Kaloz <kaloz@openwrt.org>
Date: Sun, 13 Jul 2008 22:46:45 +0200
Subject: [PATCH] Add support for the ADI Sidewinder
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
---
arch/arm/mach-ixp4xx/Kconfig | 10 ++-
arch/arm/mach-ixp4xx/Makefile | 2 +
arch/arm/mach-ixp4xx/sidewinder-pci.c | 68 ++++++++++++++
arch/arm/mach-ixp4xx/sidewinder-setup.c | 151 +++++++++++++++++++++++++++++++
4 files changed, 230 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/sidewinder-pci.c
create mode 100644 arch/arm/mach-ixp4xx/sidewinder-setup.c
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -81,6 +81,14 @@ config MACH_PRONGHORN
config MACH_PRONGHORNMETRO
def_bool MACH_PRONGHORN
+config MACH_SIDEWINDER
+ bool "ADI Sidewinder"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support the ADI
+ Engineering Sidewinder board. For more information on this
+ platform, see http://www.adiengineering.com
+
config ARCH_IXDP425
bool "IXDP425"
help
@@ -163,7 +171,7 @@ config MACH_FSG
#
config CPU_IXP46X
bool
- depends on MACH_IXDP465
+ depends on MACH_IXDP465 || MACH_SIDEWINDER
default y
config CPU_IXP43X
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -18,6 +18,7 @@ obj-pci-$(CONFIG_MACH_WG302V1) += wg302
obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
+obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
obj-y += common.o
@@ -34,6 +35,7 @@ obj-$(CONFIG_MACH_WG302V1) += wg302v1-se
obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
obj-$(CONFIG_MACH_FSG) += fsg-setup.o
obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
+obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/sidewinder-pci.c
@@ -0,0 +1,68 @@
+/*
+ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c
+ *
+ * PCI setup routines for ADI Engineering Sidewinder
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-pci.c:
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/pci.h>
+
+void __init sidewinder_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init sidewinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 1)
+ return IRQ_IXP4XX_GPIO11;
+ else if (slot == 2)
+ return IRQ_IXP4XX_GPIO10;
+ else if (slot == 3)
+ return IRQ_IXP4XX_GPIO9;
+ else
+ return -1;
+}
+
+struct hw_pci sidewinder_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = sidewinder_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = sidewinder_map_irq,
+};
+
+int __init sidewinder_pci_init(void)
+{
+ if (machine_is_sidewinder())
+ pci_common_init(&sidewinder_pci);
+ return 0;
+}
+
+subsys_initcall(sidewinder_pci_init);
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/sidewinder-setup.c
@@ -0,0 +1,149 @@
+/*
+ * arch/arm/mach-ixp4xx/sidewinder-setup.c
+ *
+ * Board setup for the ADI Engineering Sidewinder
+ *
+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <Kaloz@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data sidewinder_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource sidewinder_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device sidewinder_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &sidewinder_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &sidewinder_flash_resource,
+};
+
+static struct resource sidewinder_uart_resources[] = {
+ {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct plat_serial8250_port sidewinder_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device sidewinder_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = sidewinder_uart_data,
+ },
+ .num_resources = ARRAY_SIZE(sidewinder_uart_resources),
+ .resource = sidewinder_uart_resources,
+};
+
+static struct eth_plat_info sidewinder_plat_eth[] = {
+ {
+ .phy = 5,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
+ .phy_mask = 0x1e,
+ .rxq = 4,
+ .txreadyq = 21,
+ }, {
+ .phy = 31,
+ .rxq = 2,
+ .txreadyq = 19,
+ }
+};
+
+static struct platform_device sidewinder_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = sidewinder_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = sidewinder_plat_eth + 1,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEA,
+ .dev.platform_data = sidewinder_plat_eth + 2,
+ }
+};
+
+static struct platform_device *sidewinder_devices[] __initdata = {
+ &sidewinder_flash,
+ &sidewinder_uart,
+ &sidewinder_eth[0],
+ &sidewinder_eth[1],
+ &sidewinder_eth[2],
+};
+
+static void __init sidewinder_init(void)
+{
+ ixp4xx_sys_init();
+
+ sidewinder_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ sidewinder_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_64M - 1;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+ platform_add_devices(sidewinder_devices, ARRAY_SIZE(sidewinder_devices));
+}
+
+MACHINE_START(SIDEWINDER, "ADI Engineering Sidewinder")
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = sidewinder_init,
+MACHINE_END

30
target/linux/ixp4xx/patches-2.6.28/116-sidewinder_fis_location.patch
View File

@ -1,30 +0,0 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -13,6 +13,8 @@
#define BOARD_CONFIG_PART "boardconfig"
+#include <asm/mach-types.h>
+
struct fis_image_desc {
unsigned char name[16]; // Null terminated name
uint32_t flash_base; // Address within FLASH of image
@@ -30,7 +32,8 @@ struct fis_list {
struct fis_list *next;
};
-static int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK;
+int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK;
+
module_param(directory, int, 0);
static inline int redboot_checksum(struct fis_image_desc *img)
@@ -59,6 +62,8 @@ static int parse_redboot_partitions(stru
#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
static char nullstring[] = "unallocated";
#endif
+ if (machine_is_sidewinder())
+ directory = -5;
if ( directory < 0 ) {
offset = master->size + directory * master->erasesize;

212
target/linux/ixp4xx/patches-2.6.28/120-compex_support.patch
View File

@ -1,212 +0,0 @@
From 24025a2dcf1248079dd3019fac6ed955252d277f Mon Sep 17 00:00:00 2001
From: Imre Kaloz <kaloz@openwrt.org>
Date: Mon, 14 Jul 2008 21:56:34 +0200
Subject: [PATCH] Add support for the Compex WP18 / NP18A boards
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
---
arch/arm/mach-ixp4xx/Kconfig | 8 ++
arch/arm/mach-ixp4xx/Makefile | 2 +
arch/arm/mach-ixp4xx/compex-setup.c | 136 +++++++++++++++++++++++++++++++++++
arch/arm/mach-ixp4xx/ixdp425-pci.c | 3 +-
arch/arm/tools/mach-types | 2 +-
5 files changed, 149 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/compex-setup.c
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -89,6 +89,14 @@ config MACH_SIDEWINDER
Engineering Sidewinder board. For more information on this
platform, see http://www.adiengineering.com
+config MACH_COMPEX
+ bool "Compex WP18 / NP18A"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support Compex'
+ WP18 or NP18A boards. For more information on this
+ platform, see http://www.compex.com.sg/home/OEM/product_ap.htm
+
config ARCH_IXDP425
bool "IXDP425"
help
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -19,6 +19,7 @@ obj-pci-$(CONFIG_MACH_WG302V2) += wg302
obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
+obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
obj-y += common.o
@@ -36,6 +37,7 @@ obj-$(CONFIG_MACH_WG302V2) += wg302v2-se
obj-$(CONFIG_MACH_FSG) += fsg-setup.o
obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
+obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/compex-setup.c
@@ -0,0 +1,136 @@
+/*
+ * arch/arm/mach-ixp4xx/compex-setup.c
+ *
+ * Compex WP18 / NP18A board-setup
+ *
+ * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <Kaloz@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data compex_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource compex_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device compex_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &compex_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &compex_flash_resource,
+};
+
+static struct resource compex_uart_resources[] = {
+ {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct plat_serial8250_port compex_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device compex_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev.platform_data = compex_uart_data,
+ .num_resources = 2,
+ .resource = compex_uart_resources,
+};
+
+static struct eth_plat_info compex_plat_eth[] = {
+ {
+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
+ .phy_mask = 0xf0000,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 3,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device compex_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = compex_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = compex_plat_eth + 1,
+ }
+};
+
+static struct platform_device *compex_devices[] __initdata = {
+ &compex_flash,
+ &compex_uart,
+ &compex_eth[0],
+ &compex_eth[1],
+};
+
+static void __init compex_init(void)
+{
+ ixp4xx_sys_init();
+
+ compex_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ compex_flash_resource.end =
+ IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+
+ platform_add_devices(compex_devices, ARRAY_SIZE(compex_devices));
+}
+
+MACHINE_START(COMPEX, "Compex WP18 / NP18A")
+ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = compex_init,
+MACHINE_END
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -66,7 +66,8 @@ struct hw_pci ixdp425_pci __initdata = {
int __init ixdp425_pci_init(void)
{
if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
- machine_is_ixdp465() || machine_is_kixrp435())
+ machine_is_ixdp465() || machine_is_kixrp435() ||
+ machine_is_compex())
pci_common_init(&ixdp425_pci);
return 0;
}
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1273,7 +1273,7 @@ oiab MACH_OIAB OIAB 1269
smdk6400 MACH_SMDK6400 SMDK6400 1270
nokia_n800 MACH_NOKIA_N800 NOKIA_N800 1271
greenphone MACH_GREENPHONE GREENPHONE 1272
-compex42x MACH_COMPEXWP18 COMPEXWP18 1273
+compex MACH_COMPEX COMPEX 1273
xmate MACH_XMATE XMATE 1274
energizer MACH_ENERGIZER ENERGIZER 1275
ime1 MACH_IME1 IME1 1276

225
target/linux/ixp4xx/patches-2.6.28/130-wrt300nv2_support.patch
View File

@ -1,225 +0,0 @@
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -97,6 +97,14 @@ config MACH_COMPEX
WP18 or NP18A boards. For more information on this
platform, see http://www.compex.com.sg/home/OEM/product_ap.htm
+config MACH_WRT300NV2
+ bool "Linksys WRT300N v2"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support Linksys'
+ WRT300N v2 router. For more information on this
+ platform, see http://openwrt.org
+
config ARCH_IXDP425
bool "IXDP425"
help
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -20,6 +20,7 @@ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o
obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
+obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
obj-y += common.o
@@ -38,6 +39,7 @@ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o
obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
+obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/wrt300nv2-pci.c
@@ -0,0 +1,65 @@
+/*
+ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c
+ *
+ * PCI setup routines for Linksys WRT300N v2
+ *
+ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-pci.c:
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/pci.h>
+
+extern void ixp4xx_pci_preinit(void);
+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+
+void __init wrt300nv2_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init wrt300nv2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 1)
+ return IRQ_IXP4XX_GPIO8;
+ else return -1;
+}
+
+struct hw_pci wrt300nv2_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = wrt300nv2_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = wrt300nv2_map_irq,
+};
+
+int __init wrt300nv2_pci_init(void)
+{
+ if (machine_is_wrt300nv2())
+ pci_common_init(&wrt300nv2_pci);
+ return 0;
+}
+
+subsys_initcall(wrt300nv2_pci_init);
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
@@ -0,0 +1,108 @@
+/*
+ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+ *
+ * Board setup for the Linksys WRT300N v2
+ *
+ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <Kaloz@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data wrt300nv2_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource wrt300nv2_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device wrt300nv2_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &wrt300nv2_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &wrt300nv2_flash_resource,
+};
+
+static struct resource wrt300nv2_uart_resource = {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct plat_serial8250_port wrt300nv2_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device wrt300nv2_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = wrt300nv2_uart_data,
+ },
+ .num_resources = 1,
+ .resource = &wrt300nv2_uart_resource,
+};
+
+static struct platform_device *wrt300nv2_devices[] __initdata = {
+ &wrt300nv2_flash,
+ &wrt300nv2_uart
+};
+
+static void __init wrt300nv2_init(void)
+{
+ ixp4xx_sys_init();
+
+ wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+ platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices));
+}
+
+#ifdef CONFIG_MACH_WRT300NV2
+MACHINE_START(WRT300NV2, "Linksys WRT300N v2")
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = wrt300nv2_init,
+MACHINE_END
+#endif
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -42,7 +42,7 @@ static __inline__ void __arch_decomp_set
*/
if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
machine_is_gateway7001() || machine_is_wg302v2() ||
- machine_is_pronghorn() || machine_is_pronghorn_metro())
+ machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2())
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;

40
target/linux/ixp4xx/patches-2.6.28/131-wrt300nv2_mac_plat_info.patch
View File

@ -1,40 +0,0 @@
--- a/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
@@ -76,9 +76,36 @@ static struct platform_device wrt300nv2_
.resource = &wrt300nv2_uart_resource,
};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info wrt300nv2_plat_eth[] = {
+ {
+ .phy = -1,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 1,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device wrt300nv2_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = wrt300nv2_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = wrt300nv2_plat_eth + 1,
+ }
+};
+
static struct platform_device *wrt300nv2_devices[] __initdata = {
&wrt300nv2_flash,
- &wrt300nv2_uart
+ &wrt300nv2_uart,
+ &wrt300nv2_eth[0],
+ &wrt300nv2_eth[1],
};
static void __init wrt300nv2_init(void)

200
target/linux/ixp4xx/patches-2.6.28/150-lanready_ap1000_support.patch
View File

@ -1,200 +0,0 @@
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/ap1000-setup.c
@@ -0,0 +1,151 @@
+/*
+ * arch/arm/mach-ixp4xx/ap1000-setup.c
+ *
+ * Lanready AP-1000
+ *
+ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
+ *
+ * based on ixdp425-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <Kaloz@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data ap1000_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource ap1000_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device ap1000_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &ap1000_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &ap1000_flash_resource,
+};
+
+static struct resource ap1000_uart_resources[] = {
+ {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct plat_serial8250_port ap1000_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device ap1000_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev.platform_data = ap1000_uart_data,
+ .num_resources = 2,
+ .resource = ap1000_uart_resources
+};
+
+static struct platform_device *ap1000_devices[] __initdata = {
+ &ap1000_flash,
+ &ap1000_uart
+};
+
+static char ap1000_mem_fixup[] __initdata = "mem=64M ";
+
+static void __init ap1000_fixup(struct machine_desc *desc,
+ struct tag *tags, char **cmdline, struct meminfo *mi)
+
+{
+ struct tag *t = tags;
+ char *p = *cmdline;
+
+ /* Find the end of the tags table, taking note of any cmdline tag. */
+ for (; t->hdr.size; t = tag_next(t)) {
+ if (t->hdr.tag == ATAG_CMDLINE) {
+ p = t->u.cmdline.cmdline;
+ }
+ }
+
+ /* Overwrite the end of the table with a new cmdline tag. */
+ t->hdr.tag = ATAG_CMDLINE;
+ t->hdr.size = (sizeof (struct tag_header) +
+ strlen(ap1000_mem_fixup) + strlen(p) + 1 + 4) >> 2;
+ strlcpy(t->u.cmdline.cmdline, ap1000_mem_fixup, COMMAND_LINE_SIZE);
+ strlcpy(t->u.cmdline.cmdline + strlen(ap1000_mem_fixup), p,
+ COMMAND_LINE_SIZE - strlen(ap1000_mem_fixup));
+
+ /* Terminate the table. */
+ t = tag_next(t);
+ t->hdr.tag = ATAG_NONE;
+ t->hdr.size = 0;
+}
+
+static void __init ap1000_init(void)
+{
+ ixp4xx_sys_init();
+
+ ap1000_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ ap1000_flash_resource.end =
+ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+
+ platform_add_devices(ap1000_devices, ARRAY_SIZE(ap1000_devices));
+}
+
+#ifdef CONFIG_MACH_AP1000
+MACHINE_START(AP1000, "Lanready AP-1000")
+ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .fixup = ap1000_fixup,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = ap1000_init,
+MACHINE_END
+#endif
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -67,7 +67,7 @@ int __init ixdp425_pci_init(void)
{
if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
machine_is_ixdp465() || machine_is_kixrp435() ||
- machine_is_compex())
+ machine_is_compex() || machine_is_ap1000())
pci_common_init(&ixdp425_pci);
return 0;
}
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -105,6 +105,14 @@ config MACH_WRT300NV2
WRT300N v2 router. For more information on this
platform, see http://openwrt.org
+config MACH_AP1000
+ bool "Lanready AP-1000"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support Lanready's
+ AP1000 board. For more information on this
+ platform, see http://openwrt.org
+
config ARCH_IXDP425
bool "IXDP425"
help
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -21,6 +21,7 @@ obj-pci-$(CONFIG_MACH_PRONGHORN) += pron
obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
+obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
obj-y += common.o
@@ -40,6 +41,7 @@ obj-$(CONFIG_MACH_PRONGHORN) += pronghor
obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
+obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o

41
target/linux/ixp4xx/patches-2.6.28/151-lanready_ap1000_mac_plat_info.patch
View File

@ -1,41 +0,0 @@
--- a/arch/arm/mach-ixp4xx/ap1000-setup.c
+++ b/arch/arm/mach-ixp4xx/ap1000-setup.c
@@ -90,9 +90,37 @@ static struct platform_device ap1000_uar
.resource = ap1000_uart_resources
};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ap1000_plat_eth[] = {
+ {
+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
+ .phy_mask = 0x1e,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 5,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device ap1000_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = ap1000_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = ap1000_plat_eth + 1,
+ }
+};
+
static struct platform_device *ap1000_devices[] __initdata = {
&ap1000_flash,
- &ap1000_uart
+ &ap1000_uart,
+ &ap1000_eth[0],
+ &ap1000_eth[1],
};
static char ap1000_mem_fixup[] __initdata = "mem=64M ";

47
target/linux/ixp4xx/patches-2.6.28/162-wg302v1_mem_fixup.patch
View File

@ -1,47 +0,0 @@
--- a/arch/arm/mach-ixp4xx/wg302v1-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c
@@ -115,6 +115,36 @@ static struct platform_device *wg302v1_d
&wg302v1_eth[0],
};
+static char wg302v1_mem_fixup[] __initdata = "mem=32M ";
+
+static void __init wg302v1_fixup(struct machine_desc *desc,
+ struct tag *tags, char **cmdline, struct meminfo *mi)
+
+{
+ struct tag *t = tags;
+ char *p = *cmdline;
+
+ /* Find the end of the tags table, taking note of any cmdline tag. */
+ for (; t->hdr.size; t = tag_next(t)) {
+ if (t->hdr.tag == ATAG_CMDLINE) {
+ p = t->u.cmdline.cmdline;
+ }
+ }
+
+ /* Overwrite the end of the table with a new cmdline tag. */
+ t->hdr.tag = ATAG_CMDLINE;
+ t->hdr.size = (sizeof (struct tag_header) +
+ strlen(wg302v1_mem_fixup) + strlen(p) + 1 + 4) >> 2;
+ strlcpy(t->u.cmdline.cmdline, wg302v1_mem_fixup, COMMAND_LINE_SIZE);
+ strlcpy(t->u.cmdline.cmdline + strlen(wg302v1_mem_fixup), p,
+ COMMAND_LINE_SIZE - strlen(wg302v1_mem_fixup));
+
+ /* Terminate the table. */
+ t = tag_next(t);
+ t->hdr.tag = ATAG_NONE;
+ t->hdr.size = 0;
+}
+
static void __init wg302v1_init(void)
{
ixp4xx_sys_init();
@@ -133,6 +163,7 @@ MACHINE_START(WG302V1, "Netgear WG302 v1
/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .fixup = wg302v1_fixup,
.map_io = ixp4xx_map_io,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,

41
target/linux/ixp4xx/patches-2.6.28/170-ixdpg425_mac_plat_info.patch
View File

@ -1,41 +0,0 @@
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -73,9 +73,37 @@ static struct platform_device coyote_uar
.resource = &coyote_uart_resource,
};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ixdpg425_plat_eth[] = {
+ {
+ .phy = 5,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 4,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device ixdpg425_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = ixdpg425_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = ixdpg425_plat_eth + 1,
+ }
+};
+
+
static struct platform_device *coyote_devices[] __initdata = {
&coyote_flash,
- &coyote_uart
+ &coyote_uart,
+ &ixdpg425_eth[0],
+ &ixdpg425_eth[1],
};
static void __init coyote_init(void)

284
target/linux/ixp4xx/patches-2.6.28/180-tw5334_support.patch
View File

@ -1,284 +0,0 @@
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -158,6 +158,14 @@ config ARCH_PRPMC1100
PrPCM1100 Processor Mezanine Module. For more information on
this platform, see <file:Documentation/arm/IXP4xx>.
+config MACH_TW5334
+ bool "Titan Wireless TW-533-4"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support the Titan
+ Wireless TW533-4. For more information on this platform,
+ see http://openwrt.org
+
config MACH_NAS100D
bool
prompt "NAS100D"
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -22,6 +22,7 @@ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sid
obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
+obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
obj-y += common.o
@@ -42,6 +43,7 @@ obj-$(CONFIG_MACH_SIDEWINDER) += sidewin
obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
+obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/tw5334-setup.c
@@ -0,0 +1,162 @@
+/*
+ * arch/arm/mach-ixp4xx/tw5334-setup.c
+ *
+ * Board setup for the Titan Wireless TW-533-4
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <Kaloz@openwrt.org>
+ */
+
+#include <linux/if_ether.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data tw5334_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource tw5334_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device tw5334_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &tw5334_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &tw5334_flash_resource,
+};
+
+static struct resource tw5334_uart_resource = {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct plat_serial8250_port tw5334_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device tw5334_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = tw5334_uart_data,
+ },
+ .num_resources = 1,
+ .resource = &tw5334_uart_resource,
+};
+
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info tw5334_plat_eth[] = {
+ {
+ .phy = 0,
+ .rxq = 3,
+ .txreadyq = 20,
+ }, {
+ .phy = 1,
+ .rxq = 4,
+ .txreadyq = 21,
+ }
+};
+
+static struct platform_device tw5334_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = tw5334_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = tw5334_plat_eth + 1,
+ }
+};
+
+static struct platform_device *tw5334_devices[] __initdata = {
+ &tw5334_flash,
+ &tw5334_uart,
+ &tw5334_eth[0],
+ &tw5334_eth[1],
+};
+
+static void __init tw5334_init(void)
+{
+ DECLARE_MAC_BUF(mac_buf);
+ uint8_t __iomem *f;
+ int i;
+
+ ixp4xx_sys_init();
+
+ tw5334_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ tw5334_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+ platform_add_devices(tw5334_devices, ARRAY_SIZE(tw5334_devices));
+
+ /*
+ * Map in a portion of the flash and read the MAC addresses.
+ * Since it is stored in BE in the flash itself, we need to
+ * byteswap it if we're in LE mode.
+ */
+ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000);
+ if (f) {
+ for (i = 0; i < 6; i++)
+#ifdef __ARMEB__
+ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + i);
+ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + i);
+#else
+ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + (i^3));
+ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + (i^3));
+#endif
+ iounmap(f);
+ }
+ printk(KERN_INFO "TW-533-4: Using MAC address %s for port 0\n",
+ print_mac(mac_buf, tw5334_plat_eth[0].hwaddr));
+ printk(KERN_INFO "TW-533-4: Using MAC address %s for port 1\n",
+ print_mac(mac_buf, tw5334_plat_eth[1].hwaddr));
+}
+
+#ifdef CONFIG_MACH_TW5334
+MACHINE_START(TW5334, "Titan Wireless TW-533-4")
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = tw5334_init,
+MACHINE_END
+#endif
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/tw5334-pci.c
@@ -0,0 +1,69 @@
+/*
+ * arch/arch/mach-ixp4xx/tw5334-pci.c
+ *
+ * PCI setup routines for the Titan Wireless TW-533-4
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-pci.c:
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include <asm/mach/pci.h>
+
+void __init tw5334_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO0, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init tw5334_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 12)
+ return IRQ_IXP4XX_GPIO6;
+ else if (slot == 13)
+ return IRQ_IXP4XX_GPIO2;
+ else if (slot == 14)
+ return IRQ_IXP4XX_GPIO1;
+ else if (slot == 15)
+ return IRQ_IXP4XX_GPIO0;
+ else return -1;
+}
+
+struct hw_pci tw5334_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = tw5334_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = tw5334_map_irq,
+};
+
+int __init tw5334_pci_init(void)
+{
+ if (machine_is_tw5334())
+ pci_common_init(&tw5334_pci);
+ return 0;
+}
+
+subsys_initcall(tw5334_pci_init);
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -42,7 +42,8 @@ static __inline__ void __arch_decomp_set
*/
if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
machine_is_gateway7001() || machine_is_wg302v2() ||
- machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2())
+ machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2() ||
+ machine_is_tw5334())
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;

465
target/linux/ixp4xx/patches-2.6.28/185-mi424wr_support.patch
View File

@ -1,465 +0,0 @@
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/mach-ixp4xx/mi424wr-pci.c
+ *
+ * Actiontec MI424WR board-level PCI initialization
+ *
+ * Copyright (C) 2008 Jose Vasconcellos
+ *
+ * Maintainer: Jose Vasconcellos <jvasco@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/pci.h>
+
+/* PCI controller GPIO to IRQ pin mappings
+ * This information was obtained from Actiontec's GPL release.
+ *
+ * INTA INTB
+ * SLOT 13 8 6
+ * SLOT 14 7 8
+ * SLOT 15 6 7
+ */
+
+void __init mi424wr_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init mi424wr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 13)
+ return IRQ_IXP4XX_GPIO8;
+ if (slot == 14)
+ return IRQ_IXP4XX_GPIO7;
+ if (slot == 15)
+ return IRQ_IXP4XX_GPIO6;
+
+ return -1;
+}
+
+struct hw_pci mi424wr_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = mi424wr_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = mi424wr_map_irq,
+};
+
+int __init mi424wr_pci_init(void)
+{
+ if (machine_is_mi424wr())
+ pci_common_init(&mi424wr_pci);
+ return 0;
+}
+
+subsys_initcall(mi424wr_pci_init);
+
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c
@@ -0,0 +1,344 @@
+/*
+ * arch/arm/mach-ixp4xx/mi424wr-setup.c
+ *
+ * Actiontec MI424-WR board setup
+ * Copyright (c) 2008 Jose Vasconcellos
+ *
+ * Based on Gemtek GTWX5715 by
+ * Copyright (C) 2004 George T. Joseph
+ * Derived from Coyote
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/types.h>
+#include <linux/memory.h>
+#include <linux/leds.h>
+#include <linux/spi/spi_gpio_old.h>
+
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+/*
+ * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch
+ * and operate as an SPI type interface. The details of the interface
+ * are available on Kendin/Micrel's web site.
+ */
+
+#define MI424WR_KSSPI_SELECT 9
+#define MI424WR_KSSPI_TXD 4
+#define MI424WR_KSSPI_CLOCK 2
+#define MI424WR_KSSPI_RXD 3
+
+/*
+ * The "reset" button is wired to GPIO 10.
+ * The GPIO is brought "low" when the button is pushed.
+ */
+
+#define MI424WR_BUTTON_GPIO 10
+#define MI424WR_BUTTON_IRQ IRQ_IXP4XX_GPIO10
+
+#define MI424WR_MOCA_WAN_LED 11
+
+/* Latch on CS1 - taken from Actiontec's 2.4 source code
+ *
+ * default latch value
+ * 0 - power alarm led (red) 0 (off)
+ * 1 - power led (green) 0 (off)
+ * 2 - wireless led (green) 1 (off)
+ * 3 - no internet led (red) 0 (off)
+ * 4 - internet ok led (green) 0 (off)
+ * 5 - moca LAN 0 (off)
+ * 6 - WAN alarm led (red) 0 (off)
+ * 7 - PCI reset 1 (not reset)
+ * 8 - IP phone 1 led (green) 1 (off)
+ * 9 - IP phone 2 led (green) 1 (off)
+ * 10 - VOIP ready led (green) 1 (off)
+ * 11 - PSTN relay 1 control 0 (PSTN)
+ * 12 - PSTN relay 1 control 0 (PSTN)
+ * 13 - N/A
+ * 14 - N/A
+ * 15 - N/A
+ */
+
+#define MI424WR_LATCH_MASK 0x04
+#define MI424WR_LATCH_DEFAULT 0x1f86
+
+#define MI424WR_LATCH_ALARM_LED 0x00
+#define MI424WR_LATCH_POWER_LED 0x01
+#define MI424WR_LATCH_WIRELESS_LED 0x02
+#define MI424WR_LATCH_INET_DOWN_LED 0x03
+#define MI424WR_LATCH_INET_OK_LED 0x04
+#define MI424WR_LATCH_MOCA_LAN_LED 0x05
+#define MI424WR_LATCH_WAN_ALARM_LED 0x06
+#define MI424WR_LATCH_PCI_RESET 0x07
+#define MI424WR_LATCH_PHONE1_LED 0x08
+#define MI424WR_LATCH_PHONE2_LED 0x09
+#define MI424WR_LATCH_VOIP_LED 0x10
+#define MI424WR_LATCH_PSTN_RELAY1 0x11
+#define MI424WR_LATCH_PSTN_RELAY2 0x12
+
+/* initialize CS1 to default timings, Intel style, 16-bit bus */
+#define MI424WR_CS1_CONFIG 0x80000002
+
+/* Define both UARTs but they are not easily accessible.
+ */
+
+static struct resource mi424wr_uart_resources[] = {
+ {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+
+static struct plat_serial8250_port mi424wr_uart_platform_data[] = {
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device mi424wr_uart_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev.platform_data = mi424wr_uart_platform_data,
+ .num_resources = ARRAY_SIZE(mi424wr_uart_resources),
+ .resource = mi424wr_uart_resources,
+};
+
+static struct flash_platform_data mi424wr_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource mi424wr_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device mi424wr_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev.platform_data = &mi424wr_flash_data,
+ .num_resources = 1,
+ .resource = &mi424wr_flash_resource,
+};
+
+static int mi424wr_spi_boardinfo_setup(struct spi_board_info *bi,
+ struct spi_master *master, void *data)
+{
+
+ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias));
+
+ bi->max_speed_hz = 5000000 /* Hz */;
+ bi->bus_num = master->bus_num;
+ bi->mode = SPI_MODE_0;
+
+ return 0;
+}
+
+static struct spi_gpio_platform_data mi424wr_spi_bus_data = {
+ .pin_cs = MI424WR_KSSPI_SELECT,
+ .pin_clk = MI424WR_KSSPI_CLOCK,
+ .pin_miso = MI424WR_KSSPI_RXD,
+ .pin_mosi = MI424WR_KSSPI_TXD,
+ .cs_activelow = 1,
+ .no_spi_delay = 1,
+ .boardinfo_setup = mi424wr_spi_boardinfo_setup,
+};
+
+static struct gpio_led mi424wr_gpio_led[] = {
+ {
+ .name = "moca-wan", /* green led */
+ .gpio = MI424WR_MOCA_WAN_LED,
+ .active_low = 0,
+ }
+};
+
+static struct gpio_led_platform_data mi424wr_gpio_leds_data = {
+ .num_leds = 1,
+ .leds = mi424wr_gpio_led,
+};
+
+static struct platform_device mi424wr_gpio_leds = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &mi424wr_gpio_leds_data,
+};
+
+static uint16_t latch_value = MI424WR_LATCH_DEFAULT;
+static uint16_t __iomem *iobase;
+
+static void mi424wr_latch_set_led(u8 bit, enum led_brightness value)
+{
+
+ if (((MI424WR_LATCH_MASK >> bit) & 1) ^ (value == LED_OFF))
+ latch_value &= ~(0x1 << bit);
+ else
+ latch_value |= (0x1 << bit);
+
+ __raw_writew(latch_value, iobase);
+
+}
+
+static struct latch_led mi424wr_latch_led[] = {
+ {
+ .name = "power-alarm",
+ .bit = MI424WR_LATCH_ALARM_LED,
+ },
+ {
+ .name = "power-ok",
+ .bit = MI424WR_LATCH_POWER_LED,
+ },
+ {
+ .name = "wireless", /* green led */
+ .bit = MI424WR_LATCH_WIRELESS_LED,
+ },
+ {
+ .name = "inet-down", /* red led */
+ .bit = MI424WR_LATCH_INET_DOWN_LED,
+ },
+ {
+ .name = "inet-up", /* green led */
+ .bit = MI424WR_LATCH_INET_OK_LED,
+ },
+ {
+ .name = "moca-lan", /* green led */
+ .bit = MI424WR_LATCH_MOCA_LAN_LED,
+ },
+ {
+ .name = "wan-alarm", /* red led */
+ .bit = MI424WR_LATCH_WAN_ALARM_LED,
+ }
+};
+
+static struct latch_led_platform_data mi424wr_latch_leds_data = {
+ .num_leds = ARRAY_SIZE(mi424wr_latch_led),
+ .mem = 0x51000000,
+ .leds = mi424wr_latch_led,
+ .set_led = mi424wr_latch_set_led,
+};
+
+static struct platform_device mi424wr_latch_leds = {
+ .name = "leds-latch",
+ .id = -1,
+ .dev.platform_data = &mi424wr_latch_leds_data,
+};
+
+static struct platform_device mi424wr_spi_bus = {
+ .name = "spi-gpio",
+ .id = 0,
+ .dev.platform_data = &mi424wr_spi_bus_data,
+};
+
+static struct eth_plat_info mi424wr_npeb_data = {
+ .phy = 17, /* KS8721 */
+ .rxq = 3,
+ .txreadyq = 20,
+};
+
+static struct eth_plat_info mi424wr_npec_data = {
+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
+ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
+ .rxq = 4,
+ .txreadyq = 21,
+};
+
+static struct platform_device mi424wr_npe_devices[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = &mi424wr_npec_data,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = &mi424wr_npeb_data,
+ }
+};
+
+static struct platform_device *mi424wr_devices[] __initdata = {
+ &mi424wr_uart_device,
+ &mi424wr_flash,
+ &mi424wr_gpio_leds,
+ &mi424wr_latch_leds,
+ &mi424wr_spi_bus,
+ &mi424wr_npe_devices[0],
+ &mi424wr_npe_devices[1],
+};
+
+static void __init mi424wr_init(void)
+{
+ ixp4xx_sys_init();
+
+ mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG;
+
+ /* configure button as input
+ */
+ gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN);
+
+ /* Initialize LEDs and enables PCI bus.
+ */
+ iobase = ioremap_nocache(IXP4XX_EXP_BUS_BASE(1), 0x1000);
+ __raw_writew(latch_value, iobase);
+
+ platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices));
+}
+
+
+MACHINE_START(MI424WR, "Actiontec MI424WR")
+ /* Maintainer: Jose Vasconcellos */
+ .phys_io = IXP4XX_UART2_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = mi424wr_init,
+MACHINE_END
+
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -23,6 +23,7 @@ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp42
obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
+obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o
obj-y += common.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_MACH_COMPEX) += compex-setu
obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
+obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -229,6 +229,13 @@ config MACH_GTWX5715
"High Speed" UART is n/c (as far as I can tell)
20 Pin ARM/Xscale JTAG interface on J2
+config MACH_MI424WR
+ bool "Actiontec MI424WR"
+ depends on ARCH_IXP4XX
+ select PCI
+ help
+ Add support for the Actiontec MI424-WR.
+
comment "IXP4xx Options"
config IXP4XX_INDIRECT_PCI
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -172,6 +172,7 @@ CONFIG_MACH_FSG=y
CONFIG_CPU_IXP46X=y
CONFIG_CPU_IXP43X=y
CONFIG_MACH_GTWX5715=y
+CONFIG_MACH_MI424WR=y
#
# IXP4xx Options

553
target/linux/ixp4xx/patches-2.6.28/190-cambria_support.patch
View File

@ -1,553 +0,0 @@
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/cambria-pci.c
@@ -0,0 +1,74 @@
+/*
+ * arch/arch/mach-ixp4xx/cambria-pci.c
+ *
+ * PCI setup routines for Gateworks Cambria series
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-pci.c:
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/pci.h>
+
+extern void ixp4xx_pci_preinit(void);
+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+
+void __init cambria_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init cambria_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 1)
+ return IRQ_IXP4XX_GPIO11;
+ else if (slot == 2)
+ return IRQ_IXP4XX_GPIO10;
+ else if (slot == 3)
+ return IRQ_IXP4XX_GPIO9;
+ else if (slot == 4)
+ return IRQ_IXP4XX_GPIO8;
+ else return -1;
+}
+
+struct hw_pci cambria_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = cambria_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = cambria_map_irq,
+};
+
+int __init cambria_pci_init(void)
+{
+ if (machine_is_cambria())
+ pci_common_init(&cambria_pci);
+ return 0;
+}
+
+subsys_initcall(cambria_pci_init);
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
@@ -0,0 +1,429 @@
+/*
+ * arch/arm/mach-ixp4xx/cambria-setup.c
+ *
+ * Board setup for the Gateworks Cambria series
+ *
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Imre Kaloz <kaloz@openwrt.org>
+ */
+
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/i2c/at24.h>
+#include <linux/if_ether.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/memory.h>
+#include <linux/netdevice.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+#include <linux/socket.h>
+#include <linux/types.h>
+#include <linux/tty.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/setup.h>
+
+struct cambria_board_info {
+ unsigned char *model;
+ void (*setup)(void);
+};
+
+static struct cambria_board_info *cambria_info __initdata;
+
+static struct flash_platform_data cambria_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource cambria_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device cambria_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &cambria_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &cambria_flash_resource,
+};
+
+static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
+ .sda_pin = 7,
+ .scl_pin = 6,
+};
+
+static struct platform_device cambria_i2c_gpio = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &cambria_i2c_gpio_data,
+ },
+};
+
+static struct eth_plat_info cambria_npec_data = {
+ .phy = 1,
+ .rxq = 4,
+ .txreadyq = 21,
+};
+
+static struct eth_plat_info cambria_npea_data = {
+ .phy = 2,
+ .rxq = 2,
+ .txreadyq = 19,
+};
+
+static struct platform_device cambria_npec_device = {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = &cambria_npec_data,
+};
+
+static struct platform_device cambria_npea_device = {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEA,
+ .dev.platform_data = &cambria_npea_data,
+};
+
+static struct resource cambria_uart_resource = {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct plat_serial8250_port cambria_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device cambria_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = cambria_uart_data,
+ },
+ .num_resources = 1,
+ .resource = &cambria_uart_resource,
+};
+
+static struct resource cambria_pata_resources[] = {
+ {
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "intrq",
+ .start = IRQ_IXP4XX_GPIO12,
+ .end = IRQ_IXP4XX_GPIO12,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct ixp4xx_pata_data cambria_pata_data = {
+ .cs0_bits = 0xbfff3c03,
+ .cs1_bits = 0xbfff3c03,
+};
+
+static struct platform_device cambria_pata = {
+ .name = "pata_ixp4xx_cf",
+ .id = 0,
+ .dev.platform_data = &cambria_pata_data,
+ .num_resources = ARRAY_SIZE(cambria_pata_resources),
+ .resource = cambria_pata_resources,
+};
+
+static struct gpio_led cambria_gpio_leds[] = {
+ {
+ .name = "user", /* green led */
+ .gpio = 5,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_led_platform_data cambria_gpio_leds_data = {
+ .num_leds = 1,
+ .leds = cambria_gpio_leds,
+};
+
+static struct platform_device cambria_gpio_leds_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &cambria_gpio_leds_data,
+};
+
+static struct latch_led cambria_latch_leds[] = {
+ {
+ .name = "ledA", /* green led */
+ .bit = 0,
+ },
+ {
+ .name = "ledB", /* green led */
+ .bit = 1,
+ },
+ {
+ .name = "ledC", /* green led */
+ .bit = 2,
+ },
+ {
+ .name = "ledD", /* green led */
+ .bit = 3,
+ },
+ {
+ .name = "ledE", /* green led */
+ .bit = 4,
+ },
+ {
+ .name = "ledF", /* green led */
+ .bit = 5,
+ },
+ {
+ .name = "ledG", /* green led */
+ .bit = 6,
+ },
+ {
+ .name = "ledH", /* green led */
+ .bit = 7,
+ }
+};
+
+static struct latch_led_platform_data cambria_latch_leds_data = {
+ .num_leds = 8,
+ .leds = cambria_latch_leds,
+ .mem = 0x53F40000,
+};
+
+static struct platform_device cambria_latch_leds_device = {
+ .name = "leds-latch",
+ .id = -1,
+ .dev.platform_data = &cambria_latch_leds_data,
+};
+
+static struct resource cambria_usb0_resources[] = {
+ {
+ .start = 0xCD000000,
+ .end = 0xCD000300,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 32,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource cambria_usb1_resources[] = {
+ {
+ .start = 0xCE000000,
+ .end = 0xCE000300,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 33,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 ehci_dma_mask = ~(u32)0;
+
+static struct platform_device cambria_usb0_device = {
+ .name = "ixp4xx-ehci",
+ .id = 0,
+ .resource = cambria_usb0_resources,
+ .num_resources = ARRAY_SIZE(cambria_usb0_resources),
+ .dev = {
+ .dma_mask = &ehci_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+static struct platform_device cambria_usb1_device = {
+ .name = "ixp4xx-ehci",
+ .id = 1,
+ .resource = cambria_usb1_resources,
+ .num_resources = ARRAY_SIZE(cambria_usb1_resources),
+ .dev = {
+ .dma_mask = &ehci_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+static struct platform_device *cambria_devices[] __initdata = {
+ &cambria_i2c_gpio,
+ &cambria_flash,
+ &cambria_uart,
+};
+
+static void __init cambria_gw23xx_setup(void)
+{
+ platform_device_register(&cambria_npec_device);
+ platform_device_register(&cambria_npea_device);
+}
+
+static void __init cambria_gw2350_setup(void)
+{
+ platform_device_register(&cambria_npec_device);
+ platform_device_register(&cambria_npea_device);
+
+ platform_device_register(&cambria_usb0_device);
+ platform_device_register(&cambria_usb1_device);
+
+ platform_device_register(&cambria_gpio_leds_device);
+}
+
+static void __init cambria_gw2358_setup(void)
+{
+ platform_device_register(&cambria_npec_device);
+ platform_device_register(&cambria_npea_device);
+
+ platform_device_register(&cambria_usb0_device);
+ platform_device_register(&cambria_usb1_device);
+
+ platform_device_register(&cambria_pata);
+
+ platform_device_register(&cambria_latch_leds_device);
+}
+
+static struct cambria_board_info cambria_boards[] __initdata = {
+ {
+ .model = "GW2350",
+ .setup = cambria_gw2350_setup,
+ }, {
+ .model = "GW2358",
+ .setup = cambria_gw2358_setup,
+ }
+};
+
+static struct cambria_board_info * __init cambria_find_board_info(char *model)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
+ struct cambria_board_info *info = &cambria_boards[i];
+ if (strcmp(info->model, model) == 0)
+ return info;
+ }
+
+ return NULL;
+}
+
+static struct at24_iface *at24_if;
+
+static int at24_setup(struct at24_iface *iface, void *context)
+{
+ char mac_addr[ETH_ALEN];
+ char model[6];
+
+ at24_if = iface;
+
+ /* Read MAC addresses */
+ if (at24_if->read(at24_if, mac_addr, 0x0, 6) == 6) {
+ memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN);
+ }
+ if (at24_if->read(at24_if, mac_addr, 0x6, 6) == 6) {
+ memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN);
+ }
+
+ /* Read the first 6 bytes of the model number */
+ if (at24_if->read(at24_if, model, 0x20, 6) == 6) {
+ cambria_info = cambria_find_board_info(model);
+ }
+
+ return 0;
+}
+
+static struct at24_platform_data cambria_eeprom_info = {
+ .byte_len = 1024,
+ .page_size = 16,
+ .flags = AT24_FLAG_READONLY,
+ .setup = at24_setup,
+};
+
+static struct i2c_board_info __initdata cambria_i2c_board_info[] = {
+ {
+ I2C_BOARD_INFO("ds1672", 0x68),
+ },
+ {
+ I2C_BOARD_INFO("ad7418", 0x28),
+ },
+ {
+ I2C_BOARD_INFO("24c08", 0x51),
+ .platform_data = &cambria_eeprom_info
+ },
+};
+
+static void __init cambria_init(void)
+{
+ ixp4xx_sys_init();
+
+ cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
+ platform_add_devices(cambria_devices, ARRAY_SIZE(cambria_devices));
+
+ cambria_pata_resources[0].start = 0x53e00000;
+ cambria_pata_resources[0].end = 0x53e3ffff;
+
+ cambria_pata_resources[1].start = 0x53e40000;
+ cambria_pata_resources[1].end = 0x53e7ffff;
+
+ cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
+ cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
+
+ i2c_register_board_info(0, cambria_i2c_board_info,
+ ARRAY_SIZE(cambria_i2c_board_info));
+}
+
+static int __init cambria_model_setup(void)
+{
+ if (!machine_is_cambria())
+ return 0;
+
+ if (cambria_info) {
+ printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
+ cambria_info->model);
+ cambria_info->setup();
+ } else {
+ printk(KERN_INFO "Unknown/missing Cambria model number"
+ " -- defaults will be used\n");
+ cambria_gw23xx_setup();
+ }
+
+ return 0;
+}
+late_initcall(cambria_model_setup);
+
+MACHINE_START(CAMBRIA, "Gateworks Cambria series")
+ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = cambria_init,
+MACHINE_END
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -25,6 +25,14 @@ config MACH_AVILA
Avila Network Platform. For more information on this platform,
see <file:Documentation/arm/IXP4xx>.
+config MACH_CAMBRIA
+ bool "Cambria"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support the Gateworks
+ Cambria series. For more information on this platform,
+ see <file:Documentation/arm/IXP4xx>.
+
config MACH_LOFT
bool "Loft"
depends on MACH_AVILA
@@ -208,7 +216,7 @@ config CPU_IXP46X
config CPU_IXP43X
bool
- depends on MACH_KIXRP435
+ depends on MACH_KIXRP435 || MACH_CAMBRIA
default y
config MACH_GTWX5715
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -7,6 +7,7 @@ obj-pci-n :=
obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
+obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
@@ -29,6 +30,7 @@ obj-y += common.o
obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
obj-$(CONFIG_MACH_AVILA) += avila-setup.o
+obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o

178
target/linux/ixp4xx/patches-2.6.28/191-cambria_optional_uart.patch
View File

@ -1,178 +0,0 @@
--- a/arch/arm/mach-ixp4xx/cambria-setup.c
+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
@@ -34,6 +34,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/setup.h>
+#include <linux/irq.h>
struct cambria_board_info {
unsigned char *model;
@@ -127,6 +128,45 @@ static struct platform_device cambria_ua
.resource = &cambria_uart_resource,
};
+static struct resource cambria_optional_uart_resources[] = {
+ {
+ .start = 0x52000000,
+ .end = 0x52000fff,
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .start = 0x53000000,
+ .end = 0x53000fff,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct plat_serial8250_port cambria_optional_uart_data[] = {
+ {
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM_DELAY,
+ .regshift = 0,
+ .uartclk = 1843200,
+ .rw_delay = 2,
+ },
+ {
+ .flags = UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM_DELAY,
+ .regshift = 0,
+ .uartclk = 1843200,
+ .rw_delay = 2,
+ },
+ { },
+};
+
+static struct platform_device cambria_optional_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM1,
+ .dev.platform_data = cambria_optional_uart_data,
+ .num_resources = 2,
+ .resource = cambria_optional_uart_resources,
+};
+
static struct resource cambria_pata_resources[] = {
{
.flags = IORESOURCE_MEM
@@ -283,6 +323,19 @@ static void __init cambria_gw23xx_setup(
static void __init cambria_gw2350_setup(void)
{
+ *IXP4XX_EXP_CS2 = 0xBFFF3C43;
+ set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
+ cambria_optional_uart_data[0].mapbase = 0x52FF0000;
+ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff);
+ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
+
+ *IXP4XX_EXP_CS3 = 0xBFFF3C43;
+ set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
+ cambria_optional_uart_data[1].mapbase = 0x53FF0000;
+ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
+ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
+
+ platform_device_register(&cambria_optional_uart);
platform_device_register(&cambria_npec_device);
platform_device_register(&cambria_npea_device);
@@ -294,6 +347,19 @@ static void __init cambria_gw2350_setup(
static void __init cambria_gw2358_setup(void)
{
+ *IXP4XX_EXP_CS3 = 0xBFFF3C43;
+ set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
+ cambria_optional_uart_data[0].mapbase = 0x53FC0000;
+ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff);
+ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
+
+ set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
+ cambria_optional_uart_data[1].mapbase = 0x53F80000;
+ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
+ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
+
+ platform_device_register(&cambria_optional_uart);
+
platform_device_register(&cambria_npec_device);
platform_device_register(&cambria_npea_device);
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -26,6 +26,7 @@ struct plat_serial8250_port {
void *private_data;
unsigned char regshift; /* register shift */
unsigned char iotype; /* UPIO_* */
+ unsigned int rw_delay; /* udelay for slower busses IXP4XX Expansion Bus */
unsigned char hub6;
upf_t flags; /* UPF_* flags */
};
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -262,6 +262,7 @@ struct uart_port {
#define UPIO_TSI (5) /* Tsi108/109 type IO */
#define UPIO_DWAPB (6) /* DesignWare APB UART */
#define UPIO_RM9000 (7) /* RM9000 type IO */
+#define UPIO_MEM_DELAY (8)
unsigned int read_status_mask; /* driver specific */
unsigned int ignore_status_mask; /* driver specific */
@@ -301,6 +302,7 @@ struct uart_port {
unsigned int mctrl; /* current modem ctrl settings */
unsigned int timeout; /* character-based timeout */
+ unsigned int rw_delay; /* udelay for slow busses, IXP4XX Expansion Bus */
unsigned int type; /* port type */
const struct uart_ops *ops;
unsigned int custom_divisor;
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -373,6 +373,8 @@ static unsigned int serial_in(struct uar
outb(up->port.hub6 - 1 + offset, up->port.iobase);
return inb(up->port.iobase + 1);
+ case UPIO_MEM_DELAY:
+ udelay(up->port.rw_delay);
case UPIO_MEM:
case UPIO_DWAPB:
return readb(up->port.membase + offset);
@@ -411,6 +413,8 @@ serial_out(struct uart_8250_port *up, in
outb(value, up->port.iobase + 1);
break;
+ case UPIO_MEM_DELAY:
+ udelay(up->port.rw_delay);
case UPIO_MEM:
writeb(value, up->port.membase + offset);
break;
@@ -2823,6 +2827,7 @@ static int __devinit serial8250_probe(st
port.hub6 = p->hub6;
port.private_data = p->private_data;
port.dev = &dev->dev;
+ port.rw_delay = p->rw_delay;
if (share_irqs)
port.flags |= UPF_SHARE_IRQ;
ret = serial8250_register_port(&port);
@@ -2972,6 +2977,7 @@ int serial8250_register_port(struct uart
uart->port.iotype = port->iotype;
uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
uart->port.mapbase = port->mapbase;
+ uart->port.rw_delay = port->rw_delay;
uart->port.private_data = port->private_data;
if (port->dev)
uart->port.dev = port->dev;
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -2161,6 +2161,7 @@ uart_report_port(struct uart_driver *drv
snprintf(address, sizeof(address),
"I/O 0x%lx offset 0x%x", port->iobase, port->hub6);
break;
+ case UPIO_MEM_DELAY:
case UPIO_MEM:
case UPIO_MEM32:
case UPIO_AU:
@@ -2577,6 +2578,7 @@ int uart_match_port(struct uart_port *po
case UPIO_HUB6:
return (port1->iobase == port2->iobase) &&
(port1->hub6 == port2->hub6);
+ case UPIO_MEM_DELAY:
case UPIO_MEM:
case UPIO_MEM32:
case UPIO_AU:

46
target/linux/ixp4xx/patches-2.6.28/192-cambria_gpio_device.patch
View File

@ -1,46 +0,0 @@
--- a/arch/arm/mach-ixp4xx/cambria-setup.c
+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
@@ -214,6 +214,20 @@ static struct platform_device cambria_gp
.dev.platform_data = &cambria_gpio_leds_data,
};
+static struct resource cambria_gpio_resources[] = {
+ {
+ .name = "gpio",
+ .flags = 0,
+ },
+};
+
+static struct platform_device cambria_gpio = {
+ .name = "GPIODEV",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(cambria_gpio_resources),
+ .resource = cambria_gpio_resources,
+};
+
static struct latch_led cambria_latch_leds[] = {
{
.name = "ledA", /* green led */
@@ -335,6 +349,11 @@ static void __init cambria_gw2350_setup(
cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
+ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
+ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
+ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
+
+ platform_device_register(&cambria_gpio);
platform_device_register(&cambria_optional_uart);
platform_device_register(&cambria_npec_device);
platform_device_register(&cambria_npea_device);
@@ -358,6 +377,10 @@ static void __init cambria_gw2358_setup(
cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
+ cambria_gpio_resources[0].start = (1 << 14);
+ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
+
+ platform_device_register(&cambria_gpio);
platform_device_register(&cambria_optional_uart);
platform_device_register(&cambria_npec_device);

107
target/linux/ixp4xx/patches-2.6.28/193-cambria_pld_gpio.patch
View File

@ -1,107 +0,0 @@
--- a/arch/arm/mach-ixp4xx/cambria-setup.c
+++ b/arch/arm/mach-ixp4xx/cambria-setup.c
@@ -12,11 +12,14 @@
*/
#include <linux/device.h>
+#include <linux/gpio_buttons.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/i2c/at24.h>
+#include <linux/i2c/gw_i2c_pld.h>
#include <linux/if_ether.h>
#include <linux/init.h>
+#include <linux/input.h>
#include <linux/kernel.h>
#include <linux/leds.h>
#include <linux/memory.h>
@@ -323,6 +326,39 @@ static struct platform_device cambria_us
},
};
+static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = {
+ .gpio_base = 16,
+ .nr_gpio = 8,
+};
+
+static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = {
+ .gpio_base = 24,
+ .nr_gpio = 2,
+};
+
+
+static struct gpio_button cambria_gpio_buttons[] = {
+ {
+ .desc = "user",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 2,
+ .gpio = 25,
+ }
+};
+
+static struct gpio_buttons_platform_data cambria_gpio_buttons_data = {
+ .poll_interval = 500,
+ .nbuttons = 1,
+ .buttons = cambria_gpio_buttons,
+};
+
+static struct platform_device cambria_gpio_buttons_device = {
+ .name = "gpio-buttons",
+ .id = -1,
+ .dev.platform_data = &cambria_gpio_buttons_data,
+};
+
static struct platform_device *cambria_devices[] __initdata = {
&cambria_i2c_gpio,
&cambria_flash,
@@ -331,6 +367,11 @@ static struct platform_device *cambria_d
static void __init cambria_gw23xx_setup(void)
{
+ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
+ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
+ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
+
+ platform_device_register(&cambria_gpio);
platform_device_register(&cambria_npec_device);
platform_device_register(&cambria_npea_device);
}
@@ -377,7 +418,8 @@ static void __init cambria_gw2358_setup(
cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
- cambria_gpio_resources[0].start = (1 << 14);
+ cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\
+ (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25);
cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
platform_device_register(&cambria_gpio);
@@ -391,7 +433,12 @@ static void __init cambria_gw2358_setup(
platform_device_register(&cambria_pata);
+ cambria_gpio_leds[0].gpio = 24;
+ platform_device_register(&cambria_gpio_leds_device);
+
platform_device_register(&cambria_latch_leds_device);
+
+ platform_device_register(&cambria_gpio_buttons_device);
}
static struct cambria_board_info cambria_boards[] __initdata = {
@@ -460,6 +507,14 @@ static struct i2c_board_info __initdata
I2C_BOARD_INFO("24c08", 0x51),
.platform_data = &cambria_eeprom_info
},
+ {
+ I2C_BOARD_INFO("gw_i2c_pld", 0x56),
+ .platform_data = &gw_i2c_pld_data0,
+ },
+ {
+ I2C_BOARD_INFO("gw_i2c_pld", 0x57),
+ .platform_data = &gw_i2c_pld_data1,
+ },
};
static void __init cambria_init(void)

11
target/linux/ixp4xx/patches-2.6.28/201-npe_driver_print_license_location.patch
View File

@ -1,11 +0,0 @@
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -592,6 +592,8 @@ int npe_load_firmware(struct npe *npe, c
npe_reset(npe);
#endif
+ print_npe(KERN_INFO, npe, "firmware's license can be found in /usr/share/doc/LICENSE.IPL\n");
+
print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
"revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
(image->id >> 8) & 0xFF, image->id & 0xFF);

246
target/linux/ixp4xx/patches-2.6.28/202-npe_driver_switch_support.patch
View File

@ -1,246 +0,0 @@
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -165,14 +165,15 @@ struct port {
struct net_device *netdev;
struct napi_struct napi;
struct net_device_stats stat;
- struct mii_if_info mii;
+ struct mii_if_info mii[IXP4XX_ETH_PHY_MAX_ADDR];
struct delayed_work mdio_thread;
struct eth_plat_info *plat;
buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
struct desc *desc_tab; /* coherent */
u32 desc_tab_phys;
int id; /* logical port ID */
- u16 mii_bmcr;
+ u16 mii_bmcr[IXP4XX_ETH_PHY_MAX_ADDR];
+ int phy_count;
};
/* NPE message structure */
@@ -316,12 +317,13 @@ static void mdio_write(struct net_device
spin_unlock_irqrestore(&mdio_lock, flags);
}
-static void phy_reset(struct net_device *dev, int phy_id)
+static void phy_reset(struct net_device *dev, int idx)
{
struct port *port = netdev_priv(dev);
+ int phy_id = port->mii[idx].phy_id;
int cycles = 0;
- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
+ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
while (cycles < MAX_MII_RESET_RETRIES) {
if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
@@ -335,12 +337,12 @@ static void phy_reset(struct net_device
cycles++;
}
- printk(KERN_ERR "%s: MII reset failed\n", dev->name);
+ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
}
-static void eth_set_duplex(struct port *port)
+static void eth_set_duplex(struct port *port, int full_duplex)
{
- if (port->mii.full_duplex)
+ if (full_duplex)
__raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
&port->regs->tx_control[0]);
else
@@ -348,7 +350,7 @@ static void eth_set_duplex(struct port *
&port->regs->tx_control[0]);
}
-
+#if 0
static void phy_check_media(struct port *port, int init)
{
if (mii_check_media(&port->mii, 1, init))
@@ -367,7 +369,63 @@ static void phy_check_media(struct port
}
}
}
+#else
+static void phy_update_link(struct net_device *dev, int link)
+{
+ int prev_link = netif_carrier_ok(dev);
+
+ if (!prev_link && link) {
+ printk(KERN_INFO "%s: link up\n", dev->name);
+ netif_carrier_on(dev);
+ } else if (prev_link && !link) {
+ printk(KERN_INFO "%s: link down\n", dev->name);
+ netif_carrier_off(dev);
+ }
+}
+
+static void phy_check_media(struct port *port, int init)
+{
+ struct net_device *dev = port->netdev;
+
+ if (port->phy_count == 1) {
+ struct mii_if_info *mii = &port->mii[0];
+
+ if (mii_check_media(mii, 1, init))
+ eth_set_duplex(port, mii->full_duplex);
+
+ if (mii->force_media) /* mii_check_media() doesn't work */
+ phy_update_link(dev, mii_link_ok(mii));
+ } else {
+ int cur_link = 0;
+ int i;
+
+ if (init)
+ eth_set_duplex(port, 1);
+
+ for (i = 0; i < port->phy_count; i++)
+ cur_link |= mii_link_ok(&port->mii[i]);
+
+ phy_update_link(dev, cur_link);
+ }
+}
+#endif
+
+static void phy_power_down(struct net_device *dev, int idx)
+{
+ struct port *port = netdev_priv(dev);
+ int phy_id = port->mii[idx].phy_id;
+
+ port->mii_bmcr[idx] = mdio_read(dev, phy_id, MII_BMCR) &
+ ~(BMCR_RESET | BMCR_PDOWN);
+ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_PDOWN);
+}
+
+static void phy_power_up(struct net_device *dev, int idx)
+{
+ struct port *port = netdev_priv(dev);
+ mdio_write(dev, port->mii[idx].phy_id, MII_BMCR, port->mii_bmcr[idx]);
+}
static void mdio_thread(struct work_struct *work)
{
@@ -791,9 +849,12 @@ static int eth_ioctl(struct net_device *
if (!netif_running(dev))
return -EINVAL;
- err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
+ if (port->phy_count != 1)
+ return -EOPNOTSUPP;
+
+ err = generic_mii_ioctl(&port->mii[0], if_mii(req), cmd, &duplex_chg);
if (duplex_chg)
- eth_set_duplex(port);
+ eth_set_duplex(port, port->mii[0].full_duplex);
return err;
}
@@ -946,7 +1007,8 @@ static int eth_open(struct net_device *d
}
}
- mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
+ for (i = 0; i < port->phy_count; i++)
+ phy_power_up(dev, i);
memset(&msg, 0, sizeof(msg));
msg.cmd = NPE_VLAN_SETRXQOSENTRY;
@@ -1106,10 +1168,8 @@ static int eth_close(struct net_device *
printk(KERN_CRIT "%s: unable to disable loopback\n",
dev->name);
- port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
- ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
- mdio_write(dev, port->plat->phy, MII_BMCR,
- port->mii_bmcr | BMCR_PDOWN);
+ for (i = 0; i < port->phy_count; i++)
+ phy_power_down(dev, i);
if (!ports_open)
qmgr_disable_irq(TXDONE_QUEUE);
@@ -1119,6 +1179,42 @@ static int eth_close(struct net_device *
return 0;
}
+static void eth_add_phy(struct net_device *dev, int phy_id)
+{
+ struct port *port = netdev_priv(dev);
+ int i;
+
+ i = port->phy_count++;
+
+ port->mii[i].dev = dev;
+ port->mii[i].mdio_read = mdio_read;
+ port->mii[i].mdio_write = mdio_write;
+ port->mii[i].phy_id = phy_id;
+ port->mii[i].phy_id_mask = 0x1F;
+ port->mii[i].reg_num_mask = 0x1F;
+
+ printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, phy_id,
+ npe_name(port->npe));
+
+ phy_reset(dev, i);
+ phy_power_down(dev, i);
+}
+
+static void eth_init_mii(struct net_device *dev)
+{
+ struct port *port = netdev_priv(dev);
+
+ if (port->plat->phy < IXP4XX_ETH_PHY_MAX_ADDR) {
+ eth_add_phy(dev, port->plat->phy);
+ } else {
+ int i;
+ for (i = 0; i < IXP4XX_ETH_PHY_MAX_ADDR; i++)
+ if (port->plat->phy_mask & (1U << i))
+ eth_add_phy(dev, i);
+ }
+
+}
+
static int __devinit eth_init_one(struct platform_device *pdev)
{
struct port *port;
@@ -1191,20 +1287,7 @@ static int __devinit eth_init_one(struct
__raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
udelay(50);
- port->mii.dev = dev;
- port->mii.mdio_read = mdio_read;
- port->mii.mdio_write = mdio_write;
- port->mii.phy_id = plat->phy;
- port->mii.phy_id_mask = 0x1F;
- port->mii.reg_num_mask = 0x1F;
-
- printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
- npe_name(port->npe));
-
- phy_reset(dev, plat->phy);
- port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
- ~(BMCR_RESET | BMCR_PDOWN);
- mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
+ eth_init_mii(dev);
INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
return 0;
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -95,12 +95,15 @@ struct sys_timer;
#define IXP4XX_ETH_NPEB 0x10
#define IXP4XX_ETH_NPEC 0x20
+#define IXP4XX_ETH_PHY_MAX_ADDR 32
+
/* Information about built-in Ethernet MAC interfaces */
struct eth_plat_info {
u8 phy; /* MII PHY ID, 0 - 31 */
u8 rxq; /* configurable, currently 0 - 31 only */
u8 txreadyq;
u8 hwaddr[6];
+ u32 phy_mask;
};
/* Information about built-in HSS (synchronous serial) interfaces */

42
target/linux/ixp4xx/patches-2.6.28/203-npe_driver_phy_reset_autoneg.patch
View File

@ -1,42 +0,0 @@
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -322,8 +322,12 @@ static void phy_reset(struct net_device
struct port *port = netdev_priv(dev);
int phy_id = port->mii[idx].phy_id;
int cycles = 0;
+ u16 bmcr;
- mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr[idx] | BMCR_RESET);
+ /* reset the PHY */
+ bmcr = mdio_read(dev, phy_id, MII_BMCR);
+ bmcr |= BMCR_ANENABLE;
+ mdio_write(dev, phy_id, MII_BMCR, bmcr | BMCR_RESET);
while (cycles < MAX_MII_RESET_RETRIES) {
if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
@@ -331,13 +335,23 @@ static void phy_reset(struct net_device
printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
dev->name, cycles);
#endif
- return;
+ break;
}
udelay(1);
cycles++;
}
- printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name, phy_id);
+ if (cycles == MAX_MII_RESET_RETRIES) {
+ printk(KERN_ERR "%s: MII reset failed on PHY%2d\n", dev->name,
+ phy_id);
+ return;
+ }
+
+ /* restart auto negotiation */
+ bmcr = mdio_read(dev, phy_id, MII_BMCR);
+ bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
+ mdio_write(dev, phy_id, MII_BMCR, bmcr);
+
}
static void eth_set_duplex(struct port *port, int full_duplex)

94
target/linux/ixp4xx/patches-2.6.28/204-npe_driver_ixp43x_support.patch
View File

@ -1,94 +0,0 @@
From cba5c286f3ea34ea4767fc00c705434a00fe2c37 Mon Sep 17 00:00:00 2001
From: Imre Kaloz <kaloz@openwrt.org>
Date: Thu, 26 Jun 2008 01:58:02 +0200
Subject: [PATCH] Add support for the ethernet ports on IXP43x
---
arch/arm/mach-ixp4xx/ixp4xx_npe.c | 6 +++---
drivers/net/arm/ixp4xx_eth.c | 13 +++++++++----
include/asm-arm/arch-ixp4xx/cpu.h | 2 ++
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 7 ++++---
4 files changed, 18 insertions(+), 10 deletions(-)
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -575,8 +575,8 @@ int npe_load_firmware(struct npe *npe, c
for (i = 0; i < image->size; i++)
image->data[i] = swab32(image->data[i]);
- if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
- print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
+ if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) {
+ print_npe(KERN_INFO, npe, "IXP46x/IXP43x firmware ignored on "
"IXP42x\n");
goto err;
}
@@ -598,7 +598,7 @@ int npe_load_firmware(struct npe *npe, c
"revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
(image->id >> 8) & 0xFF, image->id & 0xFF);
- if (!cpu_is_ixp46x()) {
+ if (cpu_is_ixp42x()) {
if (!npe->id)
instr_size = NPE_A_42X_INSTR_SIZE;
else
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -32,6 +32,7 @@
#include <linux/kernel.h>
#include <linux/mii.h>
#include <linux/platform_device.h>
+#include <mach/cpu.h>
#include <mach/npe.h>
#include <mach/qmgr.h>
@@ -1337,12 +1338,16 @@ static struct platform_driver drv = {
static int __init eth_init_module(void)
{
- if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
- return -ENOSYS;
- /* All MII PHY accesses use NPE-B Ethernet registers */
spin_lock_init(&mdio_lock);
- mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
+ if (!cpu_is_ixp43x())
+ /* All MII PHY accesses use NPE-B Ethernet registers */
+ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
+
+ else
+ /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
+ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
+
__raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
return platform_driver_register(&drv);
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -35,6 +35,8 @@ static inline u32 ixp4xx_read_feature_bi
val &= ~IXP4XX_FEATURE_RESERVED;
if (!cpu_is_ixp46x())
val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
+ if (cpu_is_ixp42x())
+ val &= ~IXP4XX_FEATURE_IXP43X_46X;
return val;
}
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -628,11 +628,12 @@
#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
-#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
+#define IXP4XX_FEATURE_IXP43X_46X (IXP4XX_FEATURE_ECC_TIMESYNC | \
IXP4XX_FEATURE_USB_HOST | \
IXP4XX_FEATURE_NPEA_ETH | \
- IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
- IXP4XX_FEATURE_RSA | \
IXP4XX_FEATURE_XSCALE_MAX_FREQ)
+#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
+ IXP4XX_FEATURE_RSA)
+
#endif

2917
target/linux/ixp4xx/patches-2.6.28/210-npe_hss.patch
View File

File diff suppressed because it is too large Load Diff

199
target/linux/ixp4xx/patches-2.6.28/295-latch_led_driver.patch
View File

@ -1,199 +0,0 @@
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -119,6 +119,12 @@ config LEDS_GPIO
outputs. To be useful the particular board must have LEDs
and they must be connected to the GPIO lines.
+config LEDS_LATCH
+ tristate "LED Support for Memory Latched LEDs"
+ depends on LEDS_CLASS
+ help
+ -- To Do --
+
config LEDS_HP_DISK
tristate "LED Support for disk protection LED on HP notebooks"
depends on LEDS_CLASS && ACPI
--- /dev/null
+++ b/drivers/leds/leds-latch.c
@@ -0,0 +1,149 @@
+/*
+ * LEDs driver for Memory Latched Devices
+ *
+ * Copyright (C) 2008 Gateworks Corp.
+ * Chris Lang <clang@gateworks.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/workqueue.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+
+static unsigned int mem_keep = 0xFF;
+static spinlock_t mem_lock;
+static unsigned char *iobase;
+
+struct latch_led_data {
+ struct led_classdev cdev;
+ struct work_struct work;
+ u8 new_level;
+ u8 bit;
+ void (*set_led)(u8 bit, enum led_brightness value);
+};
+
+static void latch_set_led(u8 bit, enum led_brightness value)
+{
+ if (value == LED_OFF)
+ mem_keep |= (0x1 << bit);
+ else
+ mem_keep &= ~(0x1 << bit);
+
+ writeb(mem_keep, iobase);
+}
+
+static void latch_led_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+ struct latch_led_data *led_dat =
+ container_of(led_cdev, struct latch_led_data, cdev);
+
+ spin_lock(mem_lock);
+
+ led_dat->set_led(led_dat->bit, value);
+
+ spin_unlock(mem_lock);
+}
+
+static int latch_led_probe(struct platform_device *pdev)
+{
+ struct latch_led_platform_data *pdata = pdev->dev.platform_data;
+ struct latch_led *cur_led;
+ struct latch_led_data *leds_data, *led_dat;
+ int i, ret = 0;
+
+ if (!pdata)
+ return -EBUSY;
+
+ leds_data = kzalloc(sizeof(struct latch_led_data) * pdata->num_leds,
+ GFP_KERNEL);
+ if (!leds_data)
+ return -ENOMEM;
+
+ for (i = 0; i < pdata->num_leds; i++) {
+ cur_led = &pdata->leds[i];
+ led_dat = &leds_data[i];
+
+ led_dat->cdev.name = cur_led->name;
+ led_dat->cdev.default_trigger = cur_led->default_trigger;
+ led_dat->cdev.brightness_set = latch_led_set;
+ led_dat->cdev.brightness = LED_OFF;
+ led_dat->bit = cur_led->bit;
+ led_dat->set_led = pdata->set_led ? pdata->set_led : latch_set_led;
+
+ ret = led_classdev_register(&pdev->dev, &led_dat->cdev);
+ if (ret < 0) {
+ goto err;
+ }
+ }
+
+ if (!pdata->set_led) {
+ iobase = ioremap_nocache(pdata->mem, 0x1000);
+ writeb(0xFF, iobase);
+ }
+ platform_set_drvdata(pdev, leds_data);
+
+ return 0;
+
+err:
+ if (i > 0) {
+ for (i = i - 1; i >= 0; i--) {
+ led_classdev_unregister(&leds_data[i].cdev);
+ }
+ }
+
+ kfree(leds_data);
+
+ return ret;
+}
+
+static int __devexit latch_led_remove(struct platform_device *pdev)
+{
+ int i;
+ struct latch_led_platform_data *pdata = pdev->dev.platform_data;
+ struct latch_led_data *leds_data;
+
+ leds_data = platform_get_drvdata(pdev);
+
+ for (i = 0; i < pdata->num_leds; i++) {
+ led_classdev_unregister(&leds_data[i].cdev);
+ cancel_work_sync(&leds_data[i].work);
+ }
+
+ kfree(leds_data);
+
+ return 0;
+}
+
+static struct platform_driver latch_led_driver = {
+ .probe = latch_led_probe,
+ .remove = __devexit_p(latch_led_remove),
+ .driver = {
+ .name = "leds-latch",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init latch_led_init(void)
+{
+ return platform_driver_register(&latch_led_driver);
+}
+
+static void __exit latch_led_exit(void)
+{
+ platform_driver_unregister(&latch_led_driver);
+}
+
+module_init(latch_led_init);
+module_exit(latch_led_exit);
+
+MODULE_AUTHOR("Chris Lang <clang@gateworks.com>");
+MODULE_DESCRIPTION("Latch LED driver");
+MODULE_LICENSE("GPL");
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-c
obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
obj-$(CONFIG_LEDS_PCA9532) += leds-pca9532.o
obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
+obj-$(CONFIG_LEDS_LATCH) += leds-latch.o
obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o
obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o
obj-$(CONFIG_LEDS_FSG) += leds-fsg.o
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -148,5 +148,19 @@ struct gpio_led_platform_data {
unsigned long *delay_off);
};
+/* For the leds-latch driver */
+struct latch_led {
+ const char *name;
+ char *default_trigger;
+ unsigned bit;
+};
+
+struct latch_led_platform_data {
+ int num_leds;
+ u32 mem;
+ struct latch_led *leds;
+ void (*set_led)(u8 bit, enum led_brightness value);
+};
+
#endif /* __LINUX_LEDS_H_INCLUDED */

244
target/linux/ixp4xx/patches-2.6.28/300-avila_fetch_mac.patch
View File

@ -1,244 +0,0 @@
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -14,10 +14,16 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
+#include <linux/if_ether.h>
+#include <linux/socket.h>
+#include <linux/netdevice.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+
#include <linux/i2c-gpio.h>
#include <asm/types.h>
@@ -29,6 +35,13 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
+struct avila_board_info {
+ unsigned char *model;
+ void (*setup)(void);
+};
+
+static struct avila_board_info *avila_info __initdata;
+
static struct flash_platform_data avila_flash_data = {
.map_name = "cfi_probe",
.width = 2,
@@ -132,16 +145,181 @@ static struct platform_device avila_pata
.resource = avila_pata_resources,
};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info avila_npeb_data = {
+ .phy = 0,
+ .rxq = 3,
+ .txreadyq = 20,
+};
+
+static struct eth_plat_info avila_npec_data = {
+ .phy = 1,
+ .rxq = 4,
+ .txreadyq = 21,
+};
+
+static struct platform_device avila_npeb_device = {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = &avila_npeb_data,
+};
+
+static struct platform_device avila_npec_device = {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = &avila_npec_data,
+};
+
static struct platform_device *avila_devices[] __initdata = {
&avila_i2c_gpio,
&avila_flash,
&avila_uart
};
+static void __init avila_gw23xx_setup(void)
+{
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
+}
+
+static void __init avila_gw2342_setup(void)
+{
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
+}
+
+static void __init avila_gw2345_setup(void)
+{
+ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
+ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
+ platform_device_register(&avila_npeb_device);
+
+ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
+ platform_device_register(&avila_npec_device);
+}
+
+static void __init avila_gw2347_setup(void)
+{
+ platform_device_register(&avila_npeb_device);
+}
+
+static void __init avila_gw2348_setup(void)
+{
+ platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_npec_device);
+}
+
+static void __init avila_gw2353_setup(void)
+{
+ platform_device_register(&avila_npeb_device);
+}
+
+static void __init avila_gw2355_setup(void)
+{
+ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
+ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */
+ platform_device_register(&avila_npeb_device);
+
+ avila_npec_data.phy = 16;
+ platform_device_register(&avila_npec_device);
+}
+
+static void __init avila_gw2357_setup(void)
+{
+ platform_device_register(&avila_npeb_device);
+}
+
+static struct avila_board_info avila_boards[] __initdata = {
+ {
+ .model = "GW2342",
+ .setup = avila_gw2342_setup,
+ }, {
+ .model = "GW2345",
+ .setup = avila_gw2345_setup,
+ }, {
+ .model = "GW2347",
+ .setup = avila_gw2347_setup,
+ }, {
+ .model = "GW2348",
+ .setup = avila_gw2348_setup,
+ }, {
+ .model = "GW2353",
+ .setup = avila_gw2353_setup,
+ }, {
+ .model = "GW2355",
+ .setup = avila_gw2355_setup,
+ }, {
+ .model = "GW2357",
+ .setup = avila_gw2357_setup,
+ }
+};
+
+static struct avila_board_info * __init avila_find_board_info(char *model)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(avila_boards); i++) {
+ struct avila_board_info *info = &avila_boards[i];
+ if (strcmp(info->model, model) == 0)
+ return info;
+ }
+
+ return NULL;
+}
+
+static struct at24_iface *at24_if;
+
+static int at24_setup(struct at24_iface *iface, void *context)
+{
+ char mac_addr[ETH_ALEN];
+ char model[6];
+
+ at24_if = iface;
+
+ /* Read MAC addresses */
+ if (at24_if->read(at24_if, mac_addr, 0x0, 6) == 6) {
+ memcpy(&avila_npeb_data.hwaddr, mac_addr, ETH_ALEN);
+ }
+ if (at24_if->read(at24_if, mac_addr, 0x6, 6) == 6) {
+ memcpy(&avila_npec_data.hwaddr, mac_addr, ETH_ALEN);
+ }
+
+ /* Read the first 6 bytes of the model number */
+ if (at24_if->read(at24_if, model, 0x20, 6) == 6) {
+ avila_info = avila_find_board_info(model);
+ }
+
+ return 0;
+}
+
+static struct at24_platform_data avila_eeprom_info = {
+ .byte_len = 1024,
+ .page_size = 16,
+ .flags = AT24_FLAG_READONLY,
+ .setup = at24_setup,
+};
+
+static struct i2c_board_info __initdata avila_i2c_board_info[] = {
+ {
+ I2C_BOARD_INFO("ds1672", 0x68),
+ },
+ {
+ I2C_BOARD_INFO("ad7418", 0x28),
+ },
+ {
+ I2C_BOARD_INFO("24c08", 0x51),
+ .platform_data = &avila_eeprom_info
+ },
+};
+
static void __init avila_init(void)
{
ixp4xx_sys_init();
+ /*
+ * These devices are present on all Avila models and don't need any
+ * model specific setup.
+ */
avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
avila_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
@@ -159,7 +337,28 @@ static void __init avila_init(void)
platform_device_register(&avila_pata);
+ i2c_register_board_info(0, avila_i2c_board_info,
+ ARRAY_SIZE(avila_i2c_board_info));
+}
+
+static int __init avila_model_setup(void)
+{
+ if (!machine_is_avila())
+ return 0;
+
+ if (avila_info) {
+ printk(KERN_DEBUG "Running on Gateworks Avila %s\n",
+ avila_info->model);
+ avila_info->setup();
+ } else {
+ printk(KERN_INFO "Unknown/missing Avila model number"
+ " -- defaults will be used\n");
+ avila_gw23xx_setup();
+ }
+
+ return 0;
}
+late_initcall(avila_model_setup);
MACHINE_START(AVILA, "Gateworks Avila Network Platform")
/* Maintainer: Deepak Saxena <dsaxena@plexity.net> */

171
target/linux/ixp4xx/patches-2.6.28/301-avila_led.patch
View File

@ -1,171 +0,0 @@
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -24,6 +24,7 @@
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
+#include <linux/leds.h>
#include <linux/i2c-gpio.h>
#include <asm/types.h>
@@ -170,6 +171,72 @@ static struct platform_device avila_npec
.dev.platform_data = &avila_npec_data,
};
+static struct gpio_led avila_gpio_leds[] = {
+ {
+ .name = "user", /* green led */
+ .gpio = AVILA_GW23XX_LED_USER_GPIO,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_led_platform_data avila_gpio_leds_data = {
+ .num_leds = 1,
+ .leds = avila_gpio_leds,
+};
+
+static struct platform_device avila_gpio_leds_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &avila_gpio_leds_data,
+};
+
+static struct latch_led avila_latch_leds[] = {
+ {
+ .name = "led0", /* green led */
+ .bit = 0,
+ },
+ {
+ .name = "led1", /* green led */
+ .bit = 1,
+ },
+ {
+ .name = "led2", /* green led */
+ .bit = 2,
+ },
+ {
+ .name = "led3", /* green led */
+ .bit = 3,
+ },
+ {
+ .name = "led4", /* green led */
+ .bit = 4,
+ },
+ {
+ .name = "led5", /* green led */
+ .bit = 5,
+ },
+ {
+ .name = "led6", /* green led */
+ .bit = 6,
+ },
+ {
+ .name = "led7", /* green led */
+ .bit = 7,
+ }
+};
+
+static struct latch_led_platform_data avila_latch_leds_data = {
+ .num_leds = 8,
+ .leds = avila_latch_leds,
+ .mem = 0x51000000,
+};
+
+static struct platform_device avila_latch_leds_device = {
+ .name = "leds-latch",
+ .id = -1,
+ .dev.platform_data = &avila_latch_leds_data,
+};
+
static struct platform_device *avila_devices[] __initdata = {
&avila_i2c_gpio,
&avila_flash,
@@ -180,12 +247,16 @@ static void __init avila_gw23xx_setup(vo
{
platform_device_register(&avila_npeb_device);
platform_device_register(&avila_npec_device);
+
+ platform_device_register(&avila_gpio_leds_device);
}
static void __init avila_gw2342_setup(void)
{
platform_device_register(&avila_npeb_device);
platform_device_register(&avila_npec_device);
+
+ platform_device_register(&avila_gpio_leds_device);
}
static void __init avila_gw2345_setup(void)
@@ -196,22 +267,30 @@ static void __init avila_gw2345_setup(vo
avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */
platform_device_register(&avila_npec_device);
+
+ platform_device_register(&avila_gpio_leds_device);
}
static void __init avila_gw2347_setup(void)
{
platform_device_register(&avila_npeb_device);
+
+ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
+ platform_device_register(&avila_gpio_leds_device);
}
static void __init avila_gw2348_setup(void)
{
platform_device_register(&avila_npeb_device);
platform_device_register(&avila_npec_device);
+
+ platform_device_register(&avila_gpio_leds_device);
}
static void __init avila_gw2353_setup(void)
{
platform_device_register(&avila_npeb_device);
+ platform_device_register(&avila_gpio_leds_device);
}
static void __init avila_gw2355_setup(void)
@@ -222,11 +301,29 @@ static void __init avila_gw2355_setup(vo
avila_npec_data.phy = 16;
platform_device_register(&avila_npec_device);
+
+ platform_device_register(&avila_gpio_leds_device);
+
+ *IXP4XX_EXP_CS4 |= 0xbfff3c03;
+ avila_latch_leds[0].name = "RXD";
+ avila_latch_leds[1].name = "TXD";
+ avila_latch_leds[2].name = "POL";
+ avila_latch_leds[3].name = "LNK";
+ avila_latch_leds[4].name = "ERR";
+ avila_latch_leds_data.num_leds = 5;
+ avila_latch_leds_data.mem = 0x54000000;
+ platform_device_register(&avila_latch_leds_device);
}
static void __init avila_gw2357_setup(void)
{
platform_device_register(&avila_npeb_device);
+
+ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
+ platform_device_register(&avila_gpio_leds_device);
+
+ *IXP4XX_EXP_CS1 |= 0xbfff3c03;
+ platform_device_register(&avila_latch_leds_device);
}
static struct avila_board_info avila_boards[] __initdata = {
--- a/arch/arm/mach-ixp4xx/include/mach/avila.h
+++ b/arch/arm/mach-ixp4xx/include/mach/avila.h
@@ -36,4 +36,6 @@
#define AVILA_PCI_INTC_PIN 9
#define AVILA_PCI_INTD_PIN 8
-
+/* User LEDs */
+#define AVILA_GW23XX_LED_USER_GPIO 3
+#define AVILA_GW23X7_LED_USER_GPIO 4

41
target/linux/ixp4xx/patches-2.6.28/302-avila_gpio_device.patch
View File

@ -1,41 +0,0 @@
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -237,10 +237,28 @@ static struct platform_device avila_latc
.dev.platform_data = &avila_latch_leds_data,
};
+static struct resource avila_gpio_resources[] = {
+ {
+ .name = "gpio",
+ /* FIXME: gpio mask should be model specific */
+ .start = AVILA_GPIO_MASK,
+ .end = AVILA_GPIO_MASK,
+ .flags = 0,
+ },
+};
+
+static struct platform_device avila_gpio = {
+ .name = "GPIODEV",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(avila_gpio_resources),
+ .resource = avila_gpio_resources,
+};
+
static struct platform_device *avila_devices[] __initdata = {
&avila_i2c_gpio,
&avila_flash,
- &avila_uart
+ &avila_uart,
+ &avila_gpio,
};
static void __init avila_gw23xx_setup(void)
--- a/arch/arm/mach-ixp4xx/include/mach/avila.h
+++ b/arch/arm/mach-ixp4xx/include/mach/avila.h
@@ -39,3 +39,6 @@
/* User LEDs */
#define AVILA_GW23XX_LED_USER_GPIO 3
#define AVILA_GW23X7_LED_USER_GPIO 4
+
+/* gpio mask used by platform device */
+#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9)

46
target/linux/ixp4xx/patches-2.6.28/303-avila_gw23x7_phy_quirk.patch
View File

@ -1,46 +0,0 @@
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -291,6 +291,7 @@ static void __init avila_gw2345_setup(vo
static void __init avila_gw2347_setup(void)
{
+ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
platform_device_register(&avila_npeb_device);
avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
@@ -335,6 +336,7 @@ static void __init avila_gw2355_setup(vo
static void __init avila_gw2357_setup(void)
{
+ avila_npeb_data.quirks |= IXP4XX_ETH_QUIRK_GW23X7;
platform_device_register(&avila_npeb_device);
avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO;
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -348,6 +348,14 @@ static void phy_reset(struct net_device
return;
}
+ if (port->plat->quirks & IXP4XX_ETH_QUIRK_GW23X7) {
+ mdio_write(dev, 1, 0x19,
+ (mdio_read(dev, 1, 0x19) & 0xfffe) | 0x8000);
+
+ printk(KERN_DEBUG "%s: phy_id of the DP83848 changed to 0\n",
+ dev->name);
+ }
+
/* restart auto negotiation */
bmcr = mdio_read(dev, phy_id, MII_BMCR);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -104,6 +104,8 @@ struct eth_plat_info {
u8 txreadyq;
u8 hwaddr[6];
u32 phy_mask;
+ u32 quirks;
+#define IXP4XX_ETH_QUIRK_GW23X7 0x00000001
};
/* Information about built-in HSS (synchronous serial) interfaces */

86
target/linux/ixp4xx/patches-2.6.28/304-ixp4xx_eth_jumboframe.patch
View File

@ -1,86 +0,0 @@
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -54,7 +54,7 @@
#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
#define REGS_SIZE 0x1000
-#define MAX_MRU 1536 /* 0x600 */
+#define MAX_MRU (14320 - ETH_HLEN - ETH_FCS_LEN)
#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
#define NAPI_WEIGHT 16
@@ -1011,6 +1011,32 @@ static void destroy_queues(struct port *
}
}
+static int eth_do_change_mtu(struct net_device *dev, int mtu)
+{
+ struct port *port;
+ struct msg msg;
+ /* adjust for ethernet headers */
+ int framesize = mtu + ETH_HLEN + ETH_FCS_LEN;
+
+ port = netdev_priv(dev);
+
+ memset(&msg, 0, sizeof(msg));
+ msg.cmd = NPE_SETMAXFRAMELENGTHS;
+ msg.eth_id = port->id;
+
+ /* max rx/tx 64 byte blocks */
+ msg.byte2 = ((framesize + 63) / 64) << 8;
+ msg.byte3 = ((framesize + 63) / 64) << 8;
+
+ msg.byte4 = msg.byte6 = framesize >> 8;
+ msg.byte5 = msg.byte7 = framesize & 0xff;
+
+ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))
+ return -EIO;
+
+ return 0;
+}
+
static int eth_open(struct net_device *dev)
{
struct port *port = netdev_priv(dev);
@@ -1061,6 +1087,8 @@ static int eth_open(struct net_device *d
if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
return -EIO;
+ eth_do_change_mtu(dev, dev->mtu);
+
if ((err = request_queues(port)) != 0)
return err;
@@ -1238,6 +1266,24 @@ static void eth_init_mii(struct net_devi
}
+static int eth_change_mtu(struct net_device *dev, int mtu)
+{
+ int ret;
+
+ if (mtu > MAX_MRU)
+ return -EINVAL;
+
+ if (dev->flags & IFF_UP) {
+ ret = eth_do_change_mtu(dev, mtu);
+ if (ret < 0)
+ return ret;
+ }
+
+ dev->mtu = mtu;
+
+ return 0;
+}
+
static int __devinit eth_init_one(struct platform_device *pdev)
{
struct port *port;
@@ -1272,6 +1318,7 @@ static int __devinit eth_init_one(struct
goto err_free;
}
+ dev->change_mtu = eth_change_mtu;
dev->open = eth_open;
dev->hard_start_xmit = eth_xmit;
dev->stop = eth_close;

53
target/linux/ixp4xx/patches-2.6.28/310-gtwx5717_spi_bus.patch
View File

@ -1,53 +0,0 @@
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -29,6 +29,8 @@
#include <linux/serial_8250.h>
#include <linux/slab.h>
+#include <linux/spi/spi_gpio_old.h>
+
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
@@ -121,9 +123,41 @@ static struct platform_device gtwx5715_f
.resource = &gtwx5715_flash_resource,
};
+static int gtwx5715_spi_boardinfo_setup(struct spi_board_info *bi,
+ struct spi_master *master, void *data)
+{
+
+ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias));
+
+ bi->max_speed_hz = 5000000 /* Hz */;
+ bi->bus_num = master->bus_num;
+ bi->mode = SPI_MODE_0;
+
+ return 0;
+}
+
+static struct spi_gpio_platform_data gtwx5715_spi_bus_data = {
+ .pin_cs = GTWX5715_KSSPI_SELECT,
+ .pin_clk = GTWX5715_KSSPI_CLOCK,
+ .pin_miso = GTWX5715_KSSPI_RXD,
+ .pin_mosi = GTWX5715_KSSPI_TXD,
+ .cs_activelow = 1,
+ .no_spi_delay = 1,
+ .boardinfo_setup = gtwx5715_spi_boardinfo_setup,
+};
+
+static struct platform_device gtwx5715_spi_bus = {
+ .name = "spi-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &gtwx5715_spi_bus_data,
+ },
+};
+
static struct platform_device *gtwx5715_devices[] __initdata = {
&gtwx5715_uart_device,
&gtwx5715_flash,
+ &gtwx5715_spi_bus,
};
static void __init gtwx5715_init(void)

40
target/linux/ixp4xx/patches-2.6.28/311-gtwx5717_mac_plat_info.patch
View File

@ -1,40 +0,0 @@
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -154,10 +154,37 @@ static struct platform_device gtwx5715_s
},
};
+static struct eth_plat_info gtwx5715_npeb_data = {
+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
+ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
+ .rxq = 3,
+ .txreadyq = 20,
+};
+
+static struct eth_plat_info gtwx5715_npec_data = {
+ .phy = 5, /* port 5 of the KS8995 switch */
+ .rxq = 4,
+ .txreadyq = 21,
+};
+
+static struct platform_device gtwx5715_npeb_device = {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = &gtwx5715_npeb_data,
+};
+
+static struct platform_device gtwx5715_npec_device = {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = &gtwx5715_npec_data,
+};
+
static struct platform_device *gtwx5715_devices[] __initdata = {
&gtwx5715_uart_device,
&gtwx5715_flash,
&gtwx5715_spi_bus,
+ &gtwx5715_npeb_device,
+ &gtwx5715_npec_device,
};
static void __init gtwx5715_init(void)

137
target/linux/ixp4xx/patches-2.6.28/312-ixp4xx_pata_optimization.patch
View File

@ -1,137 +0,0 @@
--- a/drivers/ata/pata_ixp4xx_cf.c
+++ b/drivers/ata/pata_ixp4xx_cf.c
@@ -24,17 +24,58 @@
#include <scsi/scsi_host.h>
#define DRV_NAME "pata_ixp4xx_cf"
-#define DRV_VERSION "0.2"
+#define DRV_VERSION "0.3"
static int ixp4xx_set_mode(struct ata_link *link, struct ata_device **error)
{
struct ata_device *dev;
+ struct ixp4xx_pata_data *data = link->ap->host->dev->platform_data;
+ unsigned int pio_mask;
ata_link_for_each_dev(dev, link) {
+ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){
+ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03;
+ if (pio_mask & (1 << 1)){
+ pio_mask = 4;
+ }else{
+ pio_mask = 3;
+ }
+ }else{
+ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8);
+ }
+ switch (pio_mask){
+ case 0:
+ ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n");
+ dev->pio_mode = XFER_PIO_0;
+ dev->xfer_mode = XFER_PIO_0;
+ *data->cs0_cfg = 0x8a473c03;
+ break;
+ case 1:
+ ata_dev_printk(dev, KERN_INFO, "configured for PIO1\n");
+ dev->pio_mode = XFER_PIO_1;
+ dev->xfer_mode = XFER_PIO_1;
+ *data->cs0_cfg = 0x86433c03;
+ break;
+ case 2:
+ ata_dev_printk(dev, KERN_INFO, "configured for PIO2\n");
+ dev->pio_mode = XFER_PIO_2;
+ dev->xfer_mode = XFER_PIO_2;
+ *data->cs0_cfg = 0x82413c03;
+ break;
+ case 3:
+ ata_dev_printk(dev, KERN_INFO, "configured for PIO3\n");
+ dev->pio_mode = XFER_PIO_3;
+ dev->xfer_mode = XFER_PIO_3;
+ *data->cs0_cfg = 0x80823c03;
+ break;
+ case 4:
+ ata_dev_printk(dev, KERN_INFO, "configured for PIO4\n");
+ dev->pio_mode = XFER_PIO_4;
+ dev->xfer_mode = XFER_PIO_4;
+ *data->cs0_cfg = 0x80403c03;
+ break;
+ }
if (ata_dev_enabled(dev)) {
- ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n");
- dev->pio_mode = XFER_PIO_0;
- dev->xfer_mode = XFER_PIO_0;
dev->xfer_shift = ATA_SHIFT_PIO;
dev->flags |= ATA_DFLAG_PIO;
}
@@ -48,6 +89,7 @@ static unsigned int ixp4xx_mmio_data_xfe
unsigned int i;
unsigned int words = buflen >> 1;
u16 *buf16 = (u16 *) buf;
+ unsigned int pio_mask;
struct ata_port *ap = dev->link->ap;
void __iomem *mmio = ap->ioaddr.data_addr;
struct ixp4xx_pata_data *data = ap->host->dev->platform_data;
@@ -55,8 +97,34 @@ static unsigned int ixp4xx_mmio_data_xfe
/* set the expansion bus in 16bit mode and restore
* 8 bit mode after the transaction.
*/
- *data->cs0_cfg &= ~(0x01);
- udelay(100);
+ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){
+ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03;
+ if (pio_mask & (1 << 1)){
+ pio_mask = 4;
+ }else{
+ pio_mask = 3;
+ }
+ }else{
+ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8);
+ }
+ switch (pio_mask){
+ case 0:
+ *data->cs0_cfg = 0xa9643c42;
+ break;
+ case 1:
+ *data->cs0_cfg = 0x85033c42;
+ break;
+ case 2:
+ *data->cs0_cfg = 0x80b23c42;
+ break;
+ case 3:
+ *data->cs0_cfg = 0x80823c42;
+ break;
+ case 4:
+ *data->cs0_cfg = 0x80403c42;
+ break;
+ }
+ udelay(5);
/* Transfer multiple of 2 bytes */
if (rw == READ)
@@ -81,8 +149,24 @@ static unsigned int ixp4xx_mmio_data_xfe
words++;
}
- udelay(100);
- *data->cs0_cfg |= 0x01;
+ udelay(5);
+ switch (pio_mask){
+ case 0:
+ *data->cs0_cfg = 0x8a473c03;
+ break;
+ case 1:
+ *data->cs0_cfg = 0x86433c03;
+ break;
+ case 2:
+ *data->cs0_cfg = 0x82413c03;
+ break;
+ case 3:
+ *data->cs0_cfg = 0x80823c03;
+ break;
+ case 4:
+ *data->cs0_cfg = 0x80403c03;
+ break;
+ }
return words << 1;
}

27
target/linux/ixp4xx/patches-2.6.28/400-dmabounce.patch
View File

@ -1,27 +0,0 @@
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -117,6 +117,10 @@ alloc_safe_buffer(struct dmabounce_devic
} else if (size <= device_info->large.size) {
pool = &device_info->large;
} else {
+#ifdef CONFIG_DMABOUNCE_DEBUG
+ printk(KERN_INFO "A dma bounce buffer outside the pool size was requested. Requested size was 0x%08X\nThe calling code was :\n", size);
+ dump_stack();
+#endif
pool = NULL;
}
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -246,6 +246,11 @@ config MACH_MI424WR
comment "IXP4xx Options"
+config DMABOUNCE_DEBUG
+ bool "Enable DMABounce debuging"
+ default n
+ depends on DMABOUNCE
+
config IXP4XX_INDIRECT_PCI
bool "Use indirect PCI memory access"
depends on PCI

11
target/linux/ixp4xx/patches-2.6.28/401-avila_pci_dev.patch
View File

@ -1,11 +0,0 @@
--- a/arch/arm/mach-ixp4xx/include/mach/avila.h
+++ b/arch/arm/mach-ixp4xx/include/mach/avila.h
@@ -25,7 +25,7 @@
/*
* AVILA PCI IRQs
*/
-#define AVILA_PCI_MAX_DEV 4
+#define AVILA_PCI_MAX_DEV 6
#define LOFT_PCI_MAX_DEV 6
#define AVILA_PCI_IRQ_LINES 4

125
target/linux/ixp4xx/patches-2.6.28/402-ixp4xx_gpiolib.patch
View File

@ -1,125 +0,0 @@
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -36,6 +36,7 @@
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/irq.h>
+#include <asm/gpio.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
@@ -374,12 +375,39 @@ static struct platform_device *ixp46x_de
unsigned long ixp4xx_exp_bus_size;
EXPORT_SYMBOL(ixp4xx_exp_bus_size);
+static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+ gpio_line_config(gpio, IXP4XX_GPIO_IN);
+ return 0;
+}
+EXPORT_SYMBOL(ixp4xx_gpio_direction_input);
+
+static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
+{
+ gpio_line_set(gpio, level);
+ gpio_line_config(gpio, IXP4XX_GPIO_OUT);
+ return 0;
+}
+EXPORT_SYMBOL(ixp4xx_gpio_direction_output);
+
+static struct gpio_chip ixp4xx_gpio_chip = {
+ .label = "IXP4XX_GPIO_CHIP",
+ .direction_input = ixp4xx_gpio_direction_input,
+ .direction_output = ixp4xx_gpio_direction_output,
+ .get = gpio_get_value,
+ .set = gpio_set_value,
+ .base = 0,
+ .ngpio = 16,
+};
+
void __init ixp4xx_sys_init(void)
{
ixp4xx_exp_bus_size = SZ_16M;
platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
+ gpiochip_add(&ixp4xx_gpio_chip);
+
if (cpu_is_ixp46x()) {
int region;
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -355,6 +355,7 @@ config ARCH_IXP4XX
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
+ select ARCH_REQUIRE_GPIOLIB
select DMABOUNCE if PCI
help
Support for Intel's IXP4XX (XScale) family of processors.
--- a/arch/arm/mach-ixp4xx/include/mach/gpio.h
+++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h
@@ -27,47 +27,31 @@
#include <linux/kernel.h>
#include <mach/hardware.h>
+#include <asm-generic/gpio.h> /* cansleep wrappers */
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
- might_sleep();
-
- return;
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
- gpio_line_config(gpio, IXP4XX_GPIO_IN);
- return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int level)
-{
- gpio_line_set(gpio, level);
- gpio_line_config(gpio, IXP4XX_GPIO_OUT);
- return 0;
-}
+#define NR_BUILTIN_GPIO 16
static inline int gpio_get_value(unsigned gpio)
{
- int value;
-
- gpio_line_get(gpio, &value);
-
- return value;
+ if (gpio < NR_BUILTIN_GPIO)
+ {
+ int value;
+ gpio_line_get(gpio, &value);
+ return value;
+ }
+ else
+ return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
- gpio_line_set(gpio, value);
+ if (gpio < NR_BUILTIN_GPIO)
+ gpio_line_set(gpio, value);
+ else
+ __gpio_set_value(gpio, value);
}
-#include <asm-generic/gpio.h> /* cansleep wrappers */
+#define gpio_cansleep __gpio_cansleep
extern int gpio_to_irq(int gpio);
extern int irq_to_gpio(int gpio);

342
target/linux/ixp4xx/patches-2.6.28/500-usr8200_support.patch
View File

@ -1,342 +0,0 @@
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -97,6 +97,14 @@ config MACH_SIDEWINDER
Engineering Sidewinder board. For more information on this
platform, see http://www.adiengineering.com
+config MACH_USR8200
+ bool "USRobotics USR8200"
+ select PCI
+ help
+ Say 'Y' here if you want your kernel to support the USRobotics
+ USR8200 router board. For more information on this platform, see
+ http://openwrt.org
+
config MACH_COMPEX
bool "Compex WP18 / NP18A"
select PCI
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt
obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o
+obj-pci-$(CONFIG_MACH_USR8200) += usr8200-pci.o
obj-y += common.o
@@ -48,6 +49,7 @@ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv
obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o
+obj-$(CONFIG_MACH_USR8200) += usr8200-setup.o
obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/usr8200-pci.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arch/mach-ixp4xx/usr8200-pci.c
+ *
+ * PCI setup routines for USRobotics USR8200
+ *
+ * Copyright (C) 2008 Peter Denison <openwrt@marshadder.org>
+ *
+ * based on pronghorn-pci.c
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * based on coyote-pci.c:
+ * Copyright (C) 2002 Jungo Software Technologies.
+ * Copyright (C) 2003 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Peter Denison <openwrt@marshadder.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include <asm/mach/pci.h>
+
+void __init usr8200_pci_preinit(void)
+{
+ set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
+ set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
+
+ ixp4xx_pci_preinit();
+}
+
+static int __init usr8200_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (slot == 14)
+ return IRQ_IXP4XX_GPIO7;
+ else if (slot == 15)
+ return IRQ_IXP4XX_GPIO8;
+ else if (slot == 16) {
+ if (pin == 1)
+ return IRQ_IXP4XX_GPIO11;
+ else if (pin == 2)
+ return IRQ_IXP4XX_GPIO10;
+ else if (pin == 3)
+ return IRQ_IXP4XX_GPIO9;
+ else
+ return -1;
+ } else
+ return -1;
+}
+
+struct hw_pci usr8200_pci __initdata = {
+ .nr_controllers = 1,
+ .preinit = usr8200_pci_preinit,
+ .swizzle = pci_std_swizzle,
+ .setup = ixp4xx_setup,
+ .scan = ixp4xx_scan_bus,
+ .map_irq = usr8200_map_irq,
+};
+
+int __init usr8200_pci_init(void)
+{
+ if (machine_is_usr8200())
+ pci_common_init(&usr8200_pci);
+ return 0;
+}
+
+subsys_initcall(usr8200_pci_init);
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/usr8200-setup.c
@@ -0,0 +1,212 @@
+/*
+ * arch/arm/mach-ixp4xx/usr8200-setup.c
+ *
+ * Board setup for the USRobotics USR8200
+ *
+ * Copyright (C) 2008 Peter Denison <openwrt@marshadder.org>
+ *
+ * based on pronghorn-setup.c:
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * based on coyote-setup.c:
+ * Copyright (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * Author: Peter Denison <openwrt@marshadder.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/memory.h>
+#include <linux/i2c-gpio.h>
+#include <linux/leds.h>
+
+#include <asm/setup.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct flash_platform_data usr8200_flash_data = {
+ .map_name = "cfi_probe",
+ .width = 2,
+};
+
+static struct resource usr8200_flash_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device usr8200_flash = {
+ .name = "IXP4XX-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &usr8200_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &usr8200_flash_resource,
+};
+
+static struct resource usr8200_uart_resources [] = {
+ {
+ .start = IXP4XX_UART2_BASE_PHYS,
+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .start = IXP4XX_UART1_BASE_PHYS,
+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct plat_serial8250_port usr8200_uart_data[] = {
+ {
+ .mapbase = IXP4XX_UART2_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART2,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ {
+ .mapbase = IXP4XX_UART1_BASE_PHYS,
+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+ .irq = IRQ_IXP4XX_UART1,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ .uartclk = IXP4XX_UART_XTAL,
+ },
+ { },
+};
+
+static struct platform_device usr8200_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = usr8200_uart_data,
+ },
+ .num_resources = 2,
+ .resource = usr8200_uart_resources,
+};
+
+static struct gpio_led usr8200_led_pin[] = {
+ {
+ .name = "usr8200:usb1",
+ .gpio = 0,
+ .active_low = 1,
+ },
+ {
+ .name = "usr8200:usb2",
+ .gpio = 1,
+ .active_low = 1,
+ },
+ {
+ .name = "usr8200:ieee1394",
+ .gpio = 2,
+ .active_low = 1,
+ },
+ {
+ .name = "usr8200:internal",
+ .gpio = 3,
+ .active_low = 1,
+ },
+ {
+ .name = "usr8200:power",
+ .gpio = 14,
+ }
+};
+
+static struct gpio_led_platform_data usr8200_led_data = {
+ .num_leds = ARRAY_SIZE(usr8200_led_pin),
+ .leds = usr8200_led_pin,
+};
+
+static struct platform_device usr8200_led = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &usr8200_led_data,
+};
+
+static struct eth_plat_info usr8200_plat_eth[] = {
+ { /* NPEC - LAN with Marvell 88E6060 switch */
+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
+ .phy_mask = 0x0F0000,
+ .rxq = 4,
+ .txreadyq = 21,
+ }, { /* NPEB - WAN */
+ .phy = 9,
+ .rxq = 3,
+ .txreadyq = 20,
+ }
+};
+
+static struct platform_device usr8200_eth[] = {
+ {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEC,
+ .dev.platform_data = usr8200_plat_eth,
+ }, {
+ .name = "ixp4xx_eth",
+ .id = IXP4XX_ETH_NPEB,
+ .dev.platform_data = usr8200_plat_eth + 1,
+ }
+};
+
+static struct resource usr8200_rtc_resources = {
+ .flags = IORESOURCE_MEM
+};
+
+static struct platform_device usr8200_rtc = {
+ .name = "rtc7301",
+ .id = 0,
+ .num_resources = 1,
+ .resource = &usr8200_rtc_resources,
+};
+
+static struct platform_device *usr8200_devices[] __initdata = {
+ &usr8200_flash,
+ &usr8200_uart,
+ &usr8200_led,
+ &usr8200_eth[0],
+ &usr8200_eth[1],
+ &usr8200_rtc,
+};
+
+static void __init usr8200_init(void)
+{
+ ixp4xx_sys_init();
+
+ usr8200_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+ usr8200_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1;
+
+ usr8200_rtc_resources.start = IXP4XX_EXP_BUS_BASE(2);
+ usr8200_rtc_resources.end = IXP4XX_EXP_BUS_BASE(2) + 0x01ff;
+
+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+ *IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
+ IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
+ *IXP4XX_GPIO_GPCLKR = 0x01100000;
+
+ /* configure button as input */
+ gpio_line_config(12, IXP4XX_GPIO_IN);
+
+ platform_add_devices(usr8200_devices, ARRAY_SIZE(usr8200_devices));
+}
+
+MACHINE_START(USR8200, "USRobotics USR8200")
+ /* Maintainer: Peter Denison <openwrt@marshadder.org> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+ .boot_params = 0x0100,
+ .init_machine = usr8200_init,
+MACHINE_END
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -43,7 +43,7 @@ static __inline__ void __arch_decomp_set
if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
machine_is_gateway7001() || machine_is_wg302v2() ||
machine_is_pronghorn() || machine_is_pronghorn_metro() || machine_is_wrt300nv2() ||
- machine_is_tw5334())
+ machine_is_tw5334() || machine_is_usr8200())
uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
else
uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;

63
target/linux/rdc/patches-2.6.28/001-rdc3210_flash_map.patch
View File

@ -1,63 +0,0 @@
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -112,6 +112,50 @@ config MTD_SUN_UFLASH
Sun Microsystems boardsets. This driver will require CFI support
in the kernel, so if you did not enable CFI previously, do that now.
+config MTD_RDC3210
+ tristate "CFI Flash device mapped on RDC3210"
+ depends on X86 && MTD_CFI && MTD_PARTITIONS
+ help
+ RDC-3210 is the flash device we find on Ralink reference board.
+
+config MTD_RDC3210_STATIC_MAP
+ bool "Partitions on RDC3210 mapped statically" if MTD_RDC3210
+ select MTD_RDC3210_FACTORY_PRESENT
+ help
+ The mapping driver will use the static partition map for the
+ RDC-3210 flash device.
+
+config MTD_RDC3210_FACTORY_PRESENT
+ bool "Reserve a partition on RDC3210 for factory presets"
+ depends on MTD_RDC3210
+ default y
+ help
+ The mapping driver will reserve a partition on the RDC-3210 flash
+ device for resetting flash contents to factory defaults.
+
+config MTD_RDC3210_ALLOW_JFFS2
+ bool "JFFS2 filesystem usable in a partition on RDC3210"
+ depends on MTD_RDC3210 && !MTD_RDC3210_STATIC_MAP
+ help
+ The mapping driver will align a partition on the RDC-3210 flash
+ device to an erase-block boundary so that a JFFS2 filesystem may
+ reside on it.
+
+config MTD_RDC3210_SIZE
+ hex "Amount of flash memory on RDC3210"
+ depends on MTD_RDC3210
+ default "0x400000"
+ help
+ Total size in bytes of the RDC-3210 flash device
+
+config MTD_RDC3210_BUSWIDTH
+ int "Width of CFI Flash device mapped on RDC3210"
+ depends on MTD_RDC3210
+ default "2"
+ help
+ Number of bytes addressed on the RDC-3210 flash device before
+ addressing the same chip again
+
config MTD_SC520CDP
tristate "CFI Flash device mapped on AMD SC520 CDP"
depends on X86 && MTD_CFI && MTD_CONCAT
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_MTD_PHYSMAP_OF) += physmap_
obj-$(CONFIG_MTD_PMC_MSP_EVM) += pmcmsp-flash.o
obj-$(CONFIG_MTD_PMC_MSP_RAMROOT)+= pmcmsp-ramroot.o
obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
+obj-$(CONFIG_MTD_RDC3210) += rdc3210.o
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o

334
target/linux/rdc/patches-2.6.28/002-platform_support.patch
View File

@ -1,334 +0,0 @@
Index: linux-2.6.28.10/arch/x86/mach-rdc321x/gpio.c
===================================================================
--- linux-2.6.28.10.orig/arch/x86/mach-rdc321x/gpio.c 2009-11-03 21:01:29.800401126 -0800
+++ linux-2.6.28.10/arch/x86/mach-rdc321x/gpio.c 2009-11-03 21:01:32.164401226 -0800
@@ -26,7 +26,7 @@
#include <linux/types.h>
#include <linux/module.h>
-#include <asm/gpio.h>
+#include <asm/mach-rdc321x/gpio.h>
#include <asm/mach-rdc321x/rdc321x_defs.h>
@@ -74,8 +74,8 @@
}
/* initially setup the 2 copies of the gpio data registers.
- This function must be called by the platform setup code. */
-void __init rdc321x_gpio_setup()
+ This function is called before the platform setup code. */
+static int __init rdc321x_gpio_setup(void)
{
/* this might not be, what others (BIOS, bootloader, etc.)
wrote to these registers before, but it's a good guess. Still
@@ -83,6 +83,8 @@
gpio_data_reg1 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG1);
gpio_data_reg2 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG2);
+
+ return 0;
}
/* determine, if gpio number is valid */
@@ -192,3 +194,5 @@
return 0;
}
EXPORT_SYMBOL(rdc_gpio_direction_output);
+
+arch_initcall(rdc321x_gpio_setup);
Index: linux-2.6.28.10/arch/x86/mach-rdc321x/platform.c
===================================================================
--- linux-2.6.28.10.orig/arch/x86/mach-rdc321x/platform.c 2009-11-03 21:01:29.836402559 -0800
+++ linux-2.6.28.10/arch/x86/mach-rdc321x/platform.c 2009-11-03 21:13:27.212398945 -0800
@@ -1,7 +1,9 @@
/*
* Generic RDC321x platform devices
*
+ * Copyright (C) 2007-2008 OpenWrt.org
* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2008 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -25,13 +27,59 @@
#include <linux/list.h>
#include <linux/device.h>
#include <linux/platform_device.h>
+#include <linux/version.h>
#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/root_dev.h>
-#include <asm/gpio.h>
+#include <asm/mach-rdc321x/gpio.h>
+
+/* Flash */
+#ifdef CONFIG_MTD_R8610
+#define CONFIG_MTD_RDC3210 1
+#elif defined CONFIG_MTD_RDC3210
+static struct resource rdc_flash_resource[] = {
+ [0] = {
+ .start = (u32)-CONFIG_MTD_RDC3210_SIZE,
+ .end = (u32)-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device rdc_flash_device = {
+ .name = "rdc321x-flash",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rdc_flash_resource),
+ .resource = rdc_flash_resource,
+};
+#else
+static struct mtd_partition rdc_flash_parts[15];
+
+static struct resource rdc_flash_resource = {
+ .end = (u32)-1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct physmap_flash_data rdc_flash_data = {
+ .parts = rdc_flash_parts,
+};
+
+static struct platform_device rdc_flash_device = {
+ .name = "physmap-flash",
+ .id = -1,
+ .resource = &rdc_flash_resource,
+ .num_resources = 1,
+ .dev.platform_data = &rdc_flash_data,
+};
+#endif
/* LEDS */
static struct gpio_led default_leds[] = {
- { .name = "rdc:dmz", .gpio = 1, },
+ { .name = "rdc321x:dmz", .gpio = 1, },
};
static struct gpio_led_platform_data rdc321x_led_data = {
@@ -54,16 +102,189 @@
.num_resources = 0,
};
+/* Button */
+static struct gpio_keys_button rdc321x_gpio_btn[] = {
+ {
+ .gpio = 0,
+ .code = BTN_0,
+ .desc = "Reset",
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_platform_data rdc321x_gpio_btn_data = {
+ .buttons = rdc321x_gpio_btn,
+ .nbuttons = ARRAY_SIZE(rdc321x_gpio_btn),
+};
+
+static struct platform_device rdc321x_button = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &rdc321x_gpio_btn_data,
+ }
+};
+
static struct platform_device *rdc321x_devs[] = {
+ &rdc_flash_device,
&rdc321x_leds,
- &rdc321x_wdt
+ &rdc321x_wdt,
+ &rdc321x_button,
};
+static int probe_flash_start(struct map_info *the_map)
+{
+ struct mtd_info *res;
+
+ the_map->virt = ioremap(the_map->phys, the_map->size);
+ if (the_map->virt == NULL)
+ return 1;
+ for (the_map->bankwidth = 32; the_map->bankwidth; the_map->bankwidth
+ >>= 1) {
+ res = do_map_probe("cfi_probe", the_map);
+ if (res == NULL)
+ res = do_map_probe("jedec_probe", the_map);
+ if (res != NULL)
+ break;
+ }
+ iounmap(the_map->virt);
+ if (res != NULL)
+ the_map->phys = (u32)-(s32)(the_map->size = res->size);
+ return res == NULL;
+}
+
static int __init rdc_board_setup(void)
{
- rdc321x_gpio_setup();
+#ifndef CONFIG_MTD_RDC3210
+ struct map_info rdc_map_info;
+ u32 the_header[8];
+ ROOT_DEV = 0;
+ rdc_map_info.name = rdc_flash_device.name;
+ rdc_map_info.phys = 0xff000000;
+ rdc_map_info.size = 0x1000000;
+ rdc_map_info.bankwidth = 2;
+ rdc_map_info.set_vpp = NULL;
+ simple_map_init(&rdc_map_info);
+ while (probe_flash_start(&rdc_map_info)) {
+ rdc_map_info.phys++;
+ if (--rdc_map_info.size)
+ panic("Could not find start of flash!");
+ }
+ rdc_flash_resource.start = rdc_map_info.phys;
+ rdc_flash_data.width = rdc_map_info.bankwidth;
+ rdc_map_info.virt = ioremap_nocache(rdc_map_info.phys, 0x10);
+ if (rdc_map_info.virt == NULL)
+ panic("Could not ioremap to read device magic!");
+ the_header[0] = ((u32 *)rdc_map_info.virt)[0];
+ the_header[1] = ((u32 *)rdc_map_info.virt)[1];
+ the_header[2] = ((u32 *)rdc_map_info.virt)[2];
+ the_header[3] = ((u32 *)rdc_map_info.virt)[3];
+ iounmap(rdc_map_info.virt);
+ rdc_map_info.virt = ioremap_nocache(rdc_map_info.phys + 0x8000, 0x10);
+ if (rdc_map_info.virt == NULL)
+ panic("Could not ioremap to read device magic!");
+ the_header[4] = ((u32 *)rdc_map_info.virt)[0];
+ the_header[5] = ((u32 *)rdc_map_info.virt)[1];
+ the_header[6] = ((u32 *)rdc_map_info.virt)[2];
+ the_header[7] = ((u32 *)rdc_map_info.virt)[3];
+ iounmap(rdc_map_info.virt);
+ if (!memcmp(the_header, "GMTK", 4)) { /* Gemtek */
+ /* TODO */
+ } else if (!memcmp(the_header + 4, "CSYS", 4)) { /* Sitecom */
+ rdc_flash_parts[0].name = "system";
+ rdc_flash_parts[0].offset = 0;
+ rdc_flash_parts[0].size = rdc_map_info.size - 0x10000;
+ rdc_flash_parts[1].name = "config";
+ rdc_flash_parts[1].offset = 0;
+ rdc_flash_parts[1].size = 0x8000;
+ rdc_flash_parts[2].name = "magic";
+ rdc_flash_parts[2].offset = 0x8000;
+ rdc_flash_parts[2].size = 0x14;
+ rdc_flash_parts[3].name = "kernel";
+ rdc_flash_parts[3].offset = 0x8014;
+ rdc_flash_parts[3].size = the_header[5];
+ rdc_flash_parts[4].name = "rootfs";
+ rdc_flash_parts[4].offset = 0x8014 + the_header[5];
+ rdc_flash_parts[4].size = rdc_flash_parts[0].size - rdc_flash_parts[4].offset;
+ rdc_flash_parts[5].name = "bootloader";
+ rdc_flash_parts[5].offset = rdc_flash_parts[0].size;
+ rdc_flash_parts[5].size = 0x10000;
+ rdc_flash_data.nr_parts = 6;
+ } else if (!memcmp(((u8 *)the_header) + 14, "Li", 2)) { /* AMIT */
+ rdc_flash_parts[0].name = "kernel_parthdr";
+ rdc_flash_parts[0].offset = 0;
+ rdc_flash_parts[0].size = 0x10;
+ rdc_flash_parts[1].name = "kernel";
+ rdc_flash_parts[1].offset = 0x10;
+ rdc_flash_parts[1].size = 0xffff0;
+ rdc_flash_parts[2].name = "rootfs_parthdr";
+ rdc_flash_parts[2].offset = 0x100000;
+ rdc_flash_parts[2].size = 0x10;
+ rdc_flash_parts[3].name = "rootfs";
+ rdc_flash_parts[3].offset = 0x100010;
+ rdc_flash_parts[3].size = rdc_map_info.size - 0x160010;
+ rdc_flash_parts[4].name = "config_parthdr";
+ rdc_flash_parts[4].offset = rdc_map_info.size - 0x60000;
+ rdc_flash_parts[4].size = 0x10;
+ rdc_flash_parts[5].name = "config";
+ rdc_flash_parts[5].offset = rdc_map_info.size - 0x5fff0;
+ rdc_flash_parts[5].size = 0xfff0;
+ rdc_flash_parts[6].name = "recoveryfs_parthdr";
+ rdc_flash_parts[6].offset = rdc_map_info.size - 0x50000;
+ rdc_flash_parts[6].size = 0x10;
+ rdc_flash_parts[7].name = "recoveryfs";
+ rdc_flash_parts[7].offset = rdc_map_info.size - 0x4fff0;
+ rdc_flash_parts[7].size = 0x3fff0;
+ rdc_flash_parts[8].name = "recovery_parthdr";
+ rdc_flash_parts[8].offset = rdc_map_info.size - 0x10000;
+ rdc_flash_parts[8].size = 0x10;
+ rdc_flash_parts[9].name = "recovery";
+ rdc_flash_parts[9].offset = rdc_map_info.size - 0xfff0;
+ rdc_flash_parts[9].size = 0x7ff0;
+ rdc_flash_parts[10].name = "productinfo_parthdr";
+ rdc_flash_parts[10].offset = rdc_map_info.size - 0x8000;
+ rdc_flash_parts[10].size = 0x10;
+ rdc_flash_parts[11].name = "productinfo";
+ rdc_flash_parts[11].offset = rdc_map_info.size - 0x7ff0;
+ rdc_flash_parts[11].size = 0x1ff0;
+ rdc_flash_parts[12].name = "bootloader_parthdr";
+ rdc_flash_parts[12].offset = rdc_map_info.size - 0x6000;
+ rdc_flash_parts[12].size = 0x10;
+ rdc_flash_parts[13].name = "bootloader";
+ rdc_flash_parts[13].offset = rdc_map_info.size - 0x5ff0;
+ rdc_flash_parts[13].size = 0x5ff0;
+ rdc_flash_parts[14].name = "everything";
+ rdc_flash_parts[14].offset = 0;
+ rdc_flash_parts[14].size = rdc_map_info.size;
+ rdc_flash_data.nr_parts = 15;
+ } else { /* ZyXEL */
+ rdc_flash_parts[0].name = "kernel";
+ rdc_flash_parts[0].offset = 0;
+ rdc_flash_parts[0].size = 0x100000;
+ rdc_flash_parts[1].name = "rootfs";
+ rdc_flash_parts[1].offset = 0x100000;
+ rdc_flash_parts[1].size = rdc_map_info.size - 0x140000;
+ rdc_flash_parts[2].name = "linux";
+ rdc_flash_parts[2].offset = 0;
+ rdc_flash_parts[2].size = rdc_map_info.size - 0x40000;
+ rdc_flash_parts[3].name = "config";
+ rdc_flash_parts[3].offset = rdc_map_info.size - 0x40000;
+ rdc_flash_parts[3].size = 0x10000;
+ rdc_flash_parts[4].name = "productinfo";
+ rdc_flash_parts[4].offset = rdc_map_info.size - 0x30000;
+ rdc_flash_parts[4].size = 0x10000;
+ rdc_flash_parts[5].name = "bootloader";
+ rdc_flash_parts[5].offset = rdc_map_info.size - 0x20000;
+ rdc_flash_parts[5].size = 0x20000;
+ rdc_flash_data.nr_parts = 6;
+ }
+#endif
return platform_add_devices(rdc321x_devs, ARRAY_SIZE(rdc321x_devs));
}
+#ifdef CONFIG_MTD_RDC3210
arch_initcall(rdc_board_setup);
+#else
+late_initcall(rdc_board_setup);
+#endif
Index: linux-2.6.28.10/arch/x86/Makefile
===================================================================
--- linux-2.6.28.10.orig/arch/x86/Makefile 2009-11-03 21:01:29.756400281 -0800
+++ linux-2.6.28.10/arch/x86/Makefile 2009-11-03 21:01:32.164401226 -0800
@@ -113,6 +113,10 @@
mflags-$(CONFIG_X86_VOYAGER) := -Iarch/x86/include/asm/mach-voyager
mcore-$(CONFIG_X86_VOYAGER) := arch/x86/mach-voyager/
+# RDC subarch support
+mflags-$(CONFIG_X86_RDC321X) := -Iarch/x86/include/asm/mach-rdc321x
+mcore-$(CONFIG_X86_RDC321X) += arch/x86/mach-rdc321x/
+
# generic subarchitecture
mflags-$(CONFIG_X86_GENERICARCH):= -Iarch/x86/include/asm/mach-generic
fcore-$(CONFIG_X86_GENERICARCH) += arch/x86/mach-generic/
Index: linux-2.6.28.10/arch/x86/include/asm/mach-rdc321x/gpio.h
===================================================================
--- linux-2.6.28.10.orig/arch/x86/include/asm/mach-rdc321x/gpio.h 2009-11-03 21:01:29.784401606 -0800
+++ linux-2.6.28.10/arch/x86/include/asm/mach-rdc321x/gpio.h 2009-11-03 21:01:32.164401226 -0800
@@ -9,7 +9,6 @@
extern int rdc_gpio_direction_output(unsigned gpio, int value);
extern int rdc_gpio_request(unsigned gpio, const char *label);
extern void rdc_gpio_free(unsigned gpio);
-extern void __init rdc321x_gpio_setup(void);
/* Wrappers for the arch-neutral GPIO API */

20
target/linux/rdc/patches-2.6.28/004-yenta_mystery.patch
View File

@ -1,20 +0,0 @@
--- a/drivers/pcmcia/yenta_socket.c
+++ b/drivers/pcmcia/yenta_socket.c
@@ -1174,6 +1174,17 @@ static int __devinit yenta_probe (struct
/* We must finish initialization here */
+#ifdef CONFIG_X86_RDC
+/* #define YO_TI1510_DATASHEET_GUY_EXPLAIN_THIS_JUNK 0x0044f044 */
+#define YO_TI1510_DATASHEET_GUY_EXPLAIN_THIS_JUNK 0x0844b060
+/* #define YO_TI1510_DATASHEET_GUY_EXPLAIN_THIS_JUNK 0x0044d044 */
+
+ config_writel(socket, 32*4, YO_TI1510_DATASHEET_GUY_EXPLAIN_THIS_JUNK);
+ config_writel(socket, 35*4, 0x00000022);
+ config_writel(socket, 36*4, 0x60200000);
+ config_writel(socket, 40*4, 0x7e020000);
+#endif
+
if (!socket->cb_irq || request_irq(socket->cb_irq, yenta_interrupt, IRQF_SHARED, "yenta", socket)) {
/* No IRQ or request_irq failed. Poll */
socket->cb_irq = 0; /* But zero is a valid IRQ number. */

40
target/linux/rdc/patches-2.6.28/005-fix_amit_breakage.patch
View File

@ -1,40 +0,0 @@
--- a/arch/x86/boot/boot.h
+++ b/arch/x86/boot/boot.h
@@ -62,7 +62,7 @@ static inline void outl(u32 v, u16 port)
{
asm volatile("outl %0,%1" : : "a" (v), "dN" (port));
}
-static inline u32 inl(u32 port)
+static inline u32 inl(u16 port)
{
u32 v;
asm volatile("inl %1,%0" : "=a" (v) : "dN" (port));
--- a/arch/x86/boot/pm.c
+++ b/arch/x86/boot/pm.c
@@ -14,6 +14,9 @@
#include "boot.h"
#include <asm/segment.h>
+#ifdef CONFIG_X86_RDC
+#include <asm/mach-rdc/rdc321x_defs.h>
+#endif
/*
* Invoke the realmode switch hook if present; otherwise
@@ -156,6 +159,16 @@ void go_to_protected_mode(void)
die();
}
+#ifdef CONFIG_X86_RDC
+ {
+ u32 bootctl;
+
+ outl(0x80003840, RDC3210_CFGREG_ADDR);
+ bootctl = inl(RDC3210_CFGREG_DATA) | 0x07ff0000;
+ outl(bootctl, RDC3210_CFGREG_DATA);
+ }
+#endif
+
/* Reset coprocessor (IGNNE#) */
reset_coprocessor();

2898
target/linux/rdc/patches-2.6.28/006-bzip2_lzma_x86.patch
View File

File diff suppressed because it is too large Load Diff

241
target/linux/rdc/patches-2.6.28/007-r6040_git_updates.patch
View File

@ -1,241 +0,0 @@
--- a/drivers/net/r6040.c
+++ b/drivers/net/r6040.c
@@ -49,12 +49,12 @@
#include <asm/processor.h>
#define DRV_NAME "r6040"
-#define DRV_VERSION "0.19"
-#define DRV_RELDATE "18Dec2008"
+#define DRV_VERSION "0.22"
+#define DRV_RELDATE "25Mar2009"
/* PHY CHIP Address */
#define PHY1_ADDR 1 /* For MAC1 */
-#define PHY2_ADDR 2 /* For MAC2 */
+#define PHY2_ADDR 3 /* For MAC2 */
#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
@@ -160,6 +160,7 @@ MODULE_AUTHOR("Sten Wang <sten.wang@rdc.
"Florian Fainelli <florian@openwrt.org>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
+MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
/* RX and TX interrupts that we handle */
#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
@@ -200,7 +201,7 @@ struct r6040_private {
static char version[] __devinitdata = KERN_INFO DRV_NAME
": RDC R6040 NAPI net driver,"
- "version "DRV_VERSION " (" DRV_RELDATE ")\n";
+ "version "DRV_VERSION " (" DRV_RELDATE ")";
static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
@@ -330,7 +331,7 @@ static int r6040_alloc_rxbufs(struct net
do {
skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
if (!skb) {
- printk(KERN_ERR "%s: failed to alloc skb for rx\n", dev->name);
+ printk(KERN_ERR DRV_NAME "%s: failed to alloc skb for rx\n", dev->name);
rc = -ENOMEM;
goto err_exit;
}
@@ -438,7 +439,6 @@ static void r6040_down(struct net_device
{
struct r6040_private *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
- struct pci_dev *pdev = lp->pdev;
int limit = 2048;
u16 *adrp;
u16 cmd;
@@ -457,22 +457,12 @@ static void r6040_down(struct net_device
iowrite16(adrp[0], ioaddr + MID_0L);
iowrite16(adrp[1], ioaddr + MID_0M);
iowrite16(adrp[2], ioaddr + MID_0H);
- free_irq(dev->irq, dev);
-
- /* Free RX buffer */
- r6040_free_rxbufs(dev);
-
- /* Free TX buffer */
- r6040_free_txbufs(dev);
-
- /* Free Descriptor memory */
- pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
- pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
}
static int r6040_close(struct net_device *dev)
{
struct r6040_private *lp = netdev_priv(dev);
+ struct pci_dev *pdev = lp->pdev;
/* deleted timer */
del_timer_sync(&lp->timer);
@@ -481,8 +471,28 @@ static int r6040_close(struct net_device
napi_disable(&lp->napi);
netif_stop_queue(dev);
r6040_down(dev);
+
+ free_irq(dev->irq, dev);
+
+ /* Free RX buffer */
+ r6040_free_rxbufs(dev);
+
+ /* Free TX buffer */
+ r6040_free_txbufs(dev);
+
spin_unlock_irq(&lp->lock);
+ /* Free Descriptor memory */
+ if (lp->rx_ring) {
+ pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
+ lp->rx_ring = NULL;
+ }
+
+ if (lp->tx_ring) {
+ pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
+ lp->tx_ring = NULL;
+ }
+
return 0;
}
@@ -598,7 +608,6 @@ static int r6040_rx(struct net_device *d
/* Send to upper layer */
netif_receive_skb(skb_ptr);
- dev->last_rx = jiffies;
dev->stats.rx_packets++;
dev->stats.rx_bytes += descptr->len - 4;
@@ -668,7 +677,7 @@ static int r6040_poll(struct napi_struct
work_done = r6040_rx(dev, budget);
if (work_done < budget) {
- netif_rx_complete(dev, napi);
+ napi_complete(napi);
/* Enable RX interrupt */
iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
}
@@ -705,7 +714,7 @@ static irqreturn_t r6040_interrupt(int i
/* Mask off RX interrupt */
misr &= ~RX_INTS;
- netif_rx_schedule(dev, &lp->napi);
+ napi_schedule(&lp->napi);
}
/* TX interrupt request */
@@ -1063,20 +1072,20 @@ static int __devinit r6040_init_one(stru
/* this should always be supported */
err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
if (err) {
- printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
+ printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
"not supported by the card\n");
goto err_out;
}
err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
if (err) {
- printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
+ printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
"not supported by the card\n");
goto err_out;
}
/* IO Size check */
if (pci_resource_len(pdev, 0) < io_size) {
- printk(KERN_ERR DRV_NAME "Insufficient PCI resources, aborting\n");
+ printk(KERN_ERR DRV_NAME ": Insufficient PCI resources, aborting\n");
err = -EIO;
goto err_out;
}
@@ -1086,7 +1095,7 @@ static int __devinit r6040_init_one(stru
dev = alloc_etherdev(sizeof(struct r6040_private));
if (!dev) {
- printk(KERN_ERR DRV_NAME "Failed to allocate etherdev\n");
+ printk(KERN_ERR DRV_NAME ": Failed to allocate etherdev\n");
err = -ENOMEM;
goto err_out;
}
@@ -1102,11 +1111,15 @@ static int __devinit r6040_init_one(stru
ioaddr = pci_iomap(pdev, bar, io_size);
if (!ioaddr) {
- printk(KERN_ERR "ioremap failed for device %s\n",
+ printk(KERN_ERR DRV_NAME ": ioremap failed for device %s\n",
pci_name(pdev));
err = -EIO;
goto err_out_free_res;
}
+ /* If PHY status change register is still set to zero it means the
+ * bootloader didn't initialize it */
+ if (ioread16(ioaddr + PHY_CC) == 0)
+ iowrite16(0x9f07, ioaddr + PHY_CC);
/* Init system & device */
lp->base = ioaddr;
@@ -1123,6 +1136,13 @@ static int __devinit r6040_init_one(stru
adrp[1] = ioread16(ioaddr + MID_0M);
adrp[2] = ioread16(ioaddr + MID_0H);
+ /* Some bootloader/BIOSes do not initialize
+ * MAC address, warn about that */
+ if (!(adrp[0] || adrp[1] || adrp[2])) {
+ printk(KERN_WARNING DRV_NAME ": MAC address not initialized, generating random\n");
+ random_ether_addr(dev->dev_addr);
+ }
+
/* Link new device into r6040_root_dev */
lp->pdev = pdev;
lp->dev = dev;
--- a/drivers/net/r6040.c
+++ b/drivers/net/r6040.c
@@ -742,6 +742,14 @@ static int r6040_up(struct net_device *d
struct r6040_private *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
int ret;
+ u16 val;
+
+ /* Check presence of a second PHY */
+ val = r6040_phy_read(ioaddr, lp->phy_addr, 2);
+ if (val == 0xFFFF) {
+ printk(KERN_ERR DRV_NAME " no second PHY attached\n");
+ return -EIO;
+ }
/* Initialise and alloc RX/TX buffers */
r6040_init_txbufs(dev);
--- a/drivers/net/r6040.c
+++ b/drivers/net/r6040.c
@@ -401,6 +401,9 @@ static void r6040_init_mac_regs(struct n
* we may got called by r6040_tx_timeout which has left
* some unsent tx buffers */
iowrite16(0x01, ioaddr + MTPR);
+
+ /* Check media */
+ mii_check_media(&lp->mii_if, 1, 1);
}
static void r6040_tx_timeout(struct net_device *dev)
@@ -528,6 +531,8 @@ static int r6040_phy_mode_chk(struct net
phy_dat = 0x0000;
}
+ mii_check_media(&lp->mii_if, 0, 1);
+
return phy_dat;
};
@@ -810,7 +815,6 @@ static void r6040_timer(unsigned long da
lp->phy_mode = phy_mode;
lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
iowrite16(lp->mcr0, ioaddr);
- printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
}
/* Timer active again */

25
target/linux/rdc/patches-2.6.28/008-r8610_flash_map.patch
View File

@ -1,25 +0,0 @@
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -156,6 +156,12 @@ config MTD_RDC3210_BUSWIDTH
Number of bytes addressed on the RDC-3210 flash device before
addressing the same chip again
+config MTD_R8610
+ tristate "CFI flash device mapped on R8610"
+ depends on X86 && MTD_CFI && MTD_PARTITIONS
+ help
+ Flash support for the RDC R8610 evaluation board.
+
config MTD_SC520CDP
tristate "CFI Flash device mapped on AMD SC520 CDP"
depends on X86 && MTD_CFI && MTD_CONCAT
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_MTD_PMC_MSP_EVM) += pmcms
obj-$(CONFIG_MTD_PMC_MSP_RAMROOT)+= pmcmsp-ramroot.o
obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
obj-$(CONFIG_MTD_RDC3210) += rdc3210.o
+obj-$(CONFIG_MTD_R8610) += r8610.o
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o

48750
target/linux/ubicom32/patches-2.6.28/100-ubicom32_support.patch
View File

File diff suppressed because it is too large Load Diff

14723
toolchain/kernel-headers/patches-2.6.28/100-ubicom_headers.patch
View File

File diff suppressed because it is too large Load Diff