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fixes ifxmips pci support and adds GENERIC_GPIO

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11396 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2008-06-07 16:04:31 +00:00
parent 6181dacb72
commit c164e9d4b7
21 changed files with 404 additions and 305 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
target/linux/ifxmips/files/arch/mips/ifxmips/board.c
View File

@@ -99,7 +99,7 @@ static struct platform_device ifxmips_mtd[] =
const char*
get_system_type (void)
{
chiprev = readl(IFXMIPS_MPS_CHIPID);
chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID);
switch(chiprev)
{
case BOARD_DANUBE_CHIPID:

130
target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
View File

@@ -97,9 +97,9 @@ enable_ch_irq (_dma_channel_info *pCh)
int flag;
local_irq_save(flag);
writel(chan_no, IFXMIPS_DMA_CS);
writel(0x4a, IFXMIPS_DMA_CIE);
writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
enable_ifxmips_irq(pCh->irq);
}
@@ -112,9 +112,9 @@ disable_ch_irq (_dma_channel_info *pCh)
local_irq_save(flag);
g_ifxmips_dma_int_status &= ~(1 << chan_no);
writel(chan_no, IFXMIPS_DMA_CS);
writel(0, IFXMIPS_DMA_CIE);
writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(0, IFXMIPS_DMA_CIE);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
mask_and_ack_ifxmips_irq(pCh->irq);
}
@@ -126,8 +126,8 @@ open_chan (_dma_channel_info *pCh)
int chan_no = (int)(pCh - dma_chan);
local_irq_save(flag);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
if(pCh->dir == IFXMIPS_DMA_RX)
enable_ch_irq(pCh);
local_irq_restore(flag);
@@ -140,8 +140,8 @@ close_chan(_dma_channel_info *pCh)
int chan_no = (int) (pCh - dma_chan);
local_irq_save(flag);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
disable_ch_irq(pCh);
local_irq_restore(flag);
}
@@ -151,8 +151,8 @@ reset_chan (_dma_channel_info *pCh)
{
int chan_no = (int) (pCh - dma_chan);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
}
void
@@ -176,10 +176,10 @@ rx_chan_intr_handler (int chan_no)
pCh->weight--;
} else {
local_irq_save(flag);
tmp = readl(IFXMIPS_DMA_CS);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
writel(tmp, IFXMIPS_DMA_CS);
tmp = ifxmips_r32(IFXMIPS_DMA_CS);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
ifxmips_w32(tmp, IFXMIPS_DMA_CS);
g_ifxmips_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
enable_ifxmips_irq(dma_chan[chan_no].irq);
@@ -195,10 +195,10 @@ tx_chan_intr_handler (int chan_no)
int flag;
local_irq_save(flag);
tmp = readl(IFXMIPS_DMA_CS);
writel(chan_no, IFXMIPS_DMA_CS);
writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
writel(tmp, IFXMIPS_DMA_CS);
tmp = ifxmips_r32(IFXMIPS_DMA_CS);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
ifxmips_w32(tmp, IFXMIPS_DMA_CS);
g_ifxmips_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
pDev->current_tx_chan = pCh->rel_chan_no;
@@ -272,10 +272,10 @@ dma_interrupt (int irq, void *dev_id)
if (chan_no < 0 || chan_no > 19)
BUG();
tmp = readl(IFXMIPS_DMA_IRNEN);
writel(0, IFXMIPS_DMA_IRNEN);
tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN);
ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
g_ifxmips_dma_int_status |= 1 << chan_no;
writel(tmp, IFXMIPS_DMA_IRNEN);
ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
mask_and_ack_ifxmips_irq(irq);
if (!g_ifxmips_dma_in_process)
@@ -337,16 +337,16 @@ dma_device_register(_dma_device_info *dev)
memset(tx_desc_p, 0, sizeof(struct tx_desc));
}
local_irq_save(flag);
writel(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
/*check if the descriptor length is changed */
if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 2){};
writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
writel(0x30100, IFXMIPS_DMA_CCTRL); /*reset and enable channel,enable channel later */
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){};
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /*reset and enable channel,enable channel later */
local_irq_restore(flag);
}
}
@@ -376,16 +376,16 @@ dma_device_register(_dma_device_info *dev)
}
local_irq_save(flag);
writel(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
/*check if the descriptor length is changed */
if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 2){};
writel(0x0a, IFXMIPS_DMA_CIE); /*fix me, should enable all the interrupts here? */
writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
writel(0x30000, IFXMIPS_DMA_CCTRL);
if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){};
ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /*fix me, should enable all the interrupts here? */
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
local_irq_restore(flag);
enable_ifxmips_irq(dma_chan[chan_no].irq);
}
@@ -409,14 +409,14 @@ dma_device_unregister (_dma_device_info *dev)
{
chan_no = (int)(dev->tx_chan[i] - dma_chan);
local_irq_save (flag);
writel(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
pCh->curr_desc = 0;
pCh->prev_desc = 0;
pCh->control = IFXMIPS_DMA_CH_OFF;
writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
ifxmips_w32(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
@@ -446,11 +446,11 @@ dma_device_unregister (_dma_device_info *dev)
pCh->prev_desc = 0;
pCh->control = IFXMIPS_DMA_CH_OFF;
writel(chan_no, IFXMIPS_DMA_CS);
writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
ifxmips_w32(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
@@ -577,8 +577,8 @@ dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *
dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
}
writel(chan_no, IFXMIPS_DMA_CS);
tmp = readl(IFXMIPS_DMA_CCTRL);
ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL);
if (!(tmp & 1))
pCh->open (pCh);
@@ -625,14 +625,14 @@ map_dma_chan(_dma_chan_map *map)
dma_devs[i].rx_burst_len = 4;
if (i == 0)
{
writel(0, IFXMIPS_DMA_PS);
writel(readl(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */
ifxmips_w32(0, IFXMIPS_DMA_PS);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */
}
if (i == 1)
{
writel(1, IFXMIPS_DMA_PS);
writel(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */
ifxmips_w32(1, IFXMIPS_DMA_PS);
ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */
}
for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
@@ -688,17 +688,17 @@ dma_chip_init(void)
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
// reset DMA
writel(readl(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
// diable all interrupts
writel(0, IFXMIPS_DMA_IRNEN);
ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
writel(i, IFXMIPS_DMA_CS);
writel(0x2, IFXMIPS_DMA_CCTRL);
writel(0x80000040, IFXMIPS_DMA_CPOLL);
writel(readl(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
ifxmips_w32(i, IFXMIPS_DMA_CS);
ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL);
ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL);
ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
}
}
@@ -728,9 +728,9 @@ ifxmips_dma_init (void)
dma_chan[i].curr_desc = 0;
dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
writel(i, IFXMIPS_DMA_CS);
writel((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
writel(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
ifxmips_w32(i, IFXMIPS_DMA_CS);
ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
}
return 0;

14
target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c
View File

@@ -48,7 +48,7 @@ disable_ifxmips_irq (unsigned int irq_nr)
for (i = 0; i <= 4; i++)
{
if (irq_nr < INT_NUM_IM_OFFSET){
writel(readl(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
return;
}
ifxmips_ier += IFXMIPS_ICU_OFFSET;
@@ -69,8 +69,8 @@ mask_and_ack_ifxmips_irq (unsigned int irq_nr)
{
if (irq_nr < INT_NUM_IM_OFFSET)
{
writel(readl(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
writel((1 << irq_nr ), ifxmips_isr);
ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
ifxmips_w32((1 << irq_nr ), ifxmips_isr);
return;
}
ifxmips_ier += IFXMIPS_ICU_OFFSET;
@@ -91,7 +91,7 @@ enable_ifxmips_irq (unsigned int irq_nr)
{
if (irq_nr < INT_NUM_IM_OFFSET)
{
writel(readl(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier);
ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier);
return;
}
ifxmips_ier += IFXMIPS_ICU_OFFSET;
@@ -145,7 +145,7 @@ ifxmips_hw_irqdispatch (int module)
{
u32 irq;
irq = readl(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
if (irq == 0)
return;
@@ -153,7 +153,7 @@ ifxmips_hw_irqdispatch (int module)
do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
if ((irq == 22) && (module == 0)){
writel(readl(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
}
}
@@ -195,7 +195,7 @@ arch_init_irq(void)
for (i = 0; i < 5; i++)
{
writel(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
}
mips_cpu_irq_init();

90
target/linux/ifxmips/files/arch/mips/ifxmips/pci.c
View File

@@ -21,7 +21,7 @@
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
//#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
@@ -80,12 +80,12 @@ ifxmips_pci_config_access(unsigned char access_type,
if (access_type == PCI_ACCESS_WRITE)
{
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
writel(swab32(*data), ((u32*)cfg_base));
ifxmips_w32(swab32(*data), ((u32*)cfg_base));
#else
writel(*data, ((u32*)cfg_base));
ifxmips_w32(*data, ((u32*)cfg_base));
#endif
} else {
*data = readl(((u32*)(cfg_base)));
*data = ifxmips_r32(((u32*)(cfg_base)));
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
*data = swab32(*data);
#endif
@@ -94,12 +94,12 @@ ifxmips_pci_config_access(unsigned char access_type,
/* clean possible Master abort */
cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
temp = readl(((u32*)(cfg_base)));
temp = ifxmips_r32(((u32*)(cfg_base)));
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
temp = swab32 (temp);
#endif
cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
writel(temp, ((u32*)cfg_base));
ifxmips_w32(temp, ((u32*)cfg_base));
local_irq_restore(flags);
@@ -164,8 +164,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
break;
case 1:
//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
break;
case 2:
case 3:
@@ -183,44 +183,44 @@ static void __init ifxmips_pci_startup (void){
/*initialize the first PCI device--ifxmips itself */
u32 temp_buffer;
/*TODO: trigger reset */
writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
/* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
0 =>clock input
PADsel of PCI_CR of CGU : 1 =>From CGU
: 0 =>From pad
*/
writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
/* prepare GPIO */
/* PCI_RST: P1.5 ALT 01 */
//pliu20060613: start
writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
//pliu20060613: end
/* PCI_REQ1: P1.13 ALT 01 */
/* PCI_GNT1: P1.14 ALT 01 */
writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
/* PCI_REQ2: P1.15 ALT 10 */
/* PCI_GNT2: P1.7 ALT 10 */
/* enable auto-switching between PCI and EBU */
writel(0xa, PCI_CR_CLK_CTRL);
ifxmips_w32(0xa, PCI_CR_CLK_CTRL);
/* busy, i.e. configuration is not done, PCI access has to be retried */
writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
wmb ();
/* BUS Master/IO/MEM access */
writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
temp_buffer = readl(PCI_CR_PC_ARB);
temp_buffer = ifxmips_r32(PCI_CR_PC_ARB);
/* enable external 2 PCI masters */
temp_buffer &= (~(0xf << 16));
/* enable internal arbiter */
@@ -233,51 +233,51 @@ static void __init ifxmips_pci_startup (void){
/* enable all external masters request */
temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
writel(temp_buffer, PCI_CR_PC_ARB);
ifxmips_w32(temp_buffer, PCI_CR_PC_ARB);
wmb ();
/* FPI ==> PCI MEM address mapping */
/* base: 0xb8000000 == > 0x18000000 */
/* size: 8x4M = 32M */
writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
/* FPI ==> PCI IO address mapping */
/* base: 0xbAE00000 == > 0xbAE00000 */
/* size: 2M */
writel(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
/* PCI ==> FPI address mapping */
/* base: 0x0 ==> 0x0 */
/* size: 32M */
/* BAR1 32M map to SDR address */
writel(0x0e000008, PCI_CR_BAR11MASK);
writel(0, PCI_CR_PCI_ADDR_MAP11);
writel(0, PCI_CS_BASE_ADDR1);
ifxmips_w32(0x0e000008, PCI_CR_BAR11MASK);
ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11);
ifxmips_w32(0, PCI_CS_BASE_ADDR1);
#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
/* both TX and RX endian swap are enabled */
writel(readl(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
wmb ();
#endif
/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
/*use 8 dw burse length */
writel(0x303, PCI_CR_FCI_BURST_LENGTH);
ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
wmb();
writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
wmb();
mdelay (1);
writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){

6
target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
View File

@@ -29,8 +29,8 @@ ifxmips_pmu_enable (unsigned int module)
{
int err = 1000000;
writel(readl(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
while (--err && (readl(IFXMIPS_PMU_PWDSR) & module)) {}
ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module)) {}
if (!err)
panic("activating PMU module failed!");
@@ -40,6 +40,6 @@ EXPORT_SYMBOL(ifxmips_pmu_enable);
void
ifxmips_pmu_disable (unsigned int module)
{
writel(readl(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
}
EXPORT_SYMBOL(ifxmips_pmu_disable);

6
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
View File

@@ -39,11 +39,11 @@ prom_free_prom_memory (void)
void
prom_putchar (char c)
{
while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
while ((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
if (c == '\n')
writel('\r', IFXMIPS_ASC1_TBUF);
writel(c, IFXMIPS_ASC1_TBUF);
ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
ifxmips_w32(c, IFXMIPS_ASC1_TBUF);
}
void

2
target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
View File

@@ -37,7 +37,7 @@ ifxmips_machine_restart (char *command)
printk (KERN_NOTICE "System restart\n");
local_irq_disable ();
writel(readl(IFXMIPS_RCU_REQ) | IFXMIPS_RST_ALL, IFXMIPS_RCU_REQ);
ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_REQ) | IFXMIPS_RST_ALL, IFXMIPS_RCU_REQ);
for (;;);
}

14
target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
View File

@@ -49,7 +49,7 @@ __init bus_error_init (void)
unsigned int
ifxmips_get_ddr_hz (void)
{
switch (readl(IFXMIPS_CGU_SYS) & 0x3)
switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
{
case 0:
return CLOCK_167M;
@@ -66,7 +66,7 @@ unsigned int
ifxmips_get_cpu_hz (void)
{
unsigned int ddr_clock = ifxmips_get_ddr_hz();
switch (readl(IFXMIPS_CGU_SYS) & 0xc)
switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
{
case 0:
return CLOCK_333M;
@@ -81,7 +81,7 @@ unsigned int
ifxmips_get_fpi_hz (void)
{
unsigned int ddr_clock = ifxmips_get_ddr_hz();
if (readl(IFXMIPS_CGU_SYS) & 0x40)
if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
{
return ddr_clock >> 1;
}
@@ -92,7 +92,7 @@ EXPORT_SYMBOL(ifxmips_get_fpi_hz);
unsigned int
ifxmips_get_cpu_ver (void)
{
return readl(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
return ifxmips_r32(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
}
EXPORT_SYMBOL(ifxmips_get_cpu_ver);
@@ -130,10 +130,10 @@ plat_time_init (void)
write_c0_compare(r4k_cur);
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
writel(0x100, IFXMIPS_GPTU_GPT_CLC);
ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC);
writel(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
writel(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
ifxmips_w32(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
ifxmips_w32(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
}
extern const char* get_system_type (void);