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fixes ifxmips pci support and adds GENERIC_GPIO

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11396 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2008-06-07 16:04:31 +00:00
parent 6181dacb72
commit c164e9d4b7
21 changed files with 404 additions and 305 deletions
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36
target/linux/ifxmips/files/drivers/char/ifxmips_gpio.c
View File

@@ -95,7 +95,7 @@ int
ifxmips_port_set_open_drain (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
return 0;
}
@@ -105,7 +105,7 @@ int
ifxmips_port_clear_open_drain (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
return 0;
}
@@ -115,7 +115,7 @@ int
ifxmips_port_set_pudsel (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
@@ -125,7 +125,7 @@ int
ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0;
}
@@ -135,7 +135,7 @@ int
ifxmips_port_set_puden (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
@@ -145,7 +145,7 @@ int
ifxmips_port_clear_puden (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0;
}
@@ -155,7 +155,7 @@ int
ifxmips_port_set_stoff (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
@@ -165,7 +165,7 @@ int
ifxmips_port_clear_stoff (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0;
}
@@ -175,7 +175,7 @@ int
ifxmips_port_set_dir_out (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
@@ -185,7 +185,7 @@ int
ifxmips_port_set_dir_in (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0;
}
@@ -195,7 +195,7 @@ int
ifxmips_port_set_output (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
@@ -205,7 +205,7 @@ int
ifxmips_port_clear_output (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0;
}
@@ -216,7 +216,7 @@ ifxmips_port_get_input (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
if (readl(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
return 0;
else
return 1;
@@ -227,7 +227,7 @@ int
ifxmips_port_set_altsel0 (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
@@ -237,7 +237,7 @@ int
ifxmips_port_clear_altsel0 (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0;
}
@@ -247,7 +247,7 @@ int
ifxmips_port_set_altsel1 (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
}
@@ -257,7 +257,7 @@ int
ifxmips_port_clear_altsel1 (unsigned int port, unsigned int pin)
{
IFXMIPS_GPIO_SANITY;
writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0;
}
@@ -347,7 +347,7 @@ long ifxmips_port_read_procmem_helper(char* tag, u32* in_reg, char *buf)
unsigned int len, t;
len = sprintf(buf, "\n%s: ", tag);
reg = readl(in_reg);
reg = ifxmips_r32(in_reg);
bit = 0x80000000;
for (t = 0; t < 32; t++) {
if ((reg & bit) > 0)

34
target/linux/ifxmips/files/drivers/char/ifxmips_led.c
View File

@@ -54,7 +54,7 @@ void
ifxmips_led_set (unsigned int led)
{
led &= 0xffffff;
writel(readl(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(ifxmips_led_set);
@@ -62,7 +62,7 @@ void
ifxmips_led_clear (unsigned int led)
{
led = ~(led & 0xffffff);
writel(readl(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(ifxmips_led_clear);
@@ -70,7 +70,7 @@ void
ifxmips_led_blink_set (unsigned int led)
{
led &= 0xffffff;
writel(readl(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(ifxmips_led_blink_set);
@@ -78,7 +78,7 @@ void
ifxmips_led_blink_clear (unsigned int led)
{
led = ~(led & 0xffffff);
writel(readl(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(ifxmips_led_blink_clear);
@@ -115,29 +115,29 @@ ifxmips_led_probe(struct platform_device *dev)
ifxmips_led_setup_gpio();
writel(0, IFXMIPS_LED_AR);
writel(0, IFXMIPS_LED_CPU0);
writel(0, IFXMIPS_LED_CPU1);
writel(LED_CON0_SWU, IFXMIPS_LED_CON0);
writel(0, IFXMIPS_LED_CON1);
ifxmips_w32(0, IFXMIPS_LED_AR);
ifxmips_w32(0, IFXMIPS_LED_CPU0);
ifxmips_w32(0, IFXMIPS_LED_CPU1);
ifxmips_w32(LED_CON0_SWU, IFXMIPS_LED_CON0);
ifxmips_w32(0, IFXMIPS_LED_CON1);
/* setup the clock edge that the shift register is triggered on */
writel(readl(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0);
writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0);
/* per default leds 15-0 are set */
writel(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
ifxmips_w32(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
/* leds are update periodically by the FPID */
writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1);
writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1);
/* set led update speed */
writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1);
writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1);
/* adsl 0 and 1 leds are updated by the arc */
writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0);
/* per default, the leds are turned on */
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED);

8
target/linux/ifxmips/files/drivers/char/ifxmips_mei_core.c
View File

@@ -260,7 +260,7 @@ unsigned char got_int = 0;
static void
meiLongwordWrite (u32* ul_address, u32 ul_data)
{
writel(ul_data, ul_address);
ifxmips_w32(ul_data, ul_address);
wmb();
return;
} // end of "meiLongwordWrite(..."
@@ -277,7 +277,7 @@ static void
meiLongwordRead (u32* ul_address, u32 * pul_data)
{
//*pul_data = *((volatile u32 *)ul_address);
*pul_data = readl(ul_address);
*pul_data = ifxmips_r32(ul_address);
wmb();
return;
} // end of "meiLongwordRead(..."
@@ -3561,9 +3561,9 @@ ifxmips_mei_init_module (void)
ifxmips_mei_ceoc_init ();
#endif
// power up mei
temp = readl(IFXMIPS_PMU_PWDCR);
temp = ifxmips_r32(IFXMIPS_PMU_PWDCR);
temp &= 0xffff7dbe;
writel(temp, IFXMIPS_PMU_PWDCR);
ifxmips_w32(temp, IFXMIPS_PMU_PWDCR);
#if defined (CONFIG_ATM_IFXMIPS)
IFX_ATM_LED_Callback_Register (adsl_led_flash);

124
target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c
View File

@@ -80,7 +80,7 @@ ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
{
unsigned int rmc;
rmc = (readl(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
rmc = (ifxmips_r32(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
if (rmc == 0)
{
printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
@@ -97,12 +97,12 @@ rx_int (struct ifx_ssc_port *info)
unsigned long *tmp_ptr;
unsigned int rx_valid_cnt;
/* number of words waiting in the RX FIFO */
fifo_fill_lev = (readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
fifo_fill_lev = (ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
// transfer with 32 bits per entry
while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
tmp_ptr = (unsigned long *) info->rxbuf_ptr;
*tmp_ptr = readl(IFXMIPS_SSC_RB);
*tmp_ptr = ifxmips_r32(IFXMIPS_SSC_RB);
info->rxbuf_ptr += 4;
info->stats.rxBytes += 4;
fifo_fill_lev--;
@@ -111,14 +111,14 @@ rx_int (struct ifx_ssc_port *info)
// now do the rest as mentioned in STATE.RXBV
while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
rx_valid_cnt = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
rx_valid_cnt = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
if (rx_valid_cnt == 0)
break;
if (rx_valid_cnt > bytes_in_buf)
rx_valid_cnt = bytes_in_buf;
tmp_val = readl(IFXMIPS_SSC_RB);
tmp_val = ifxmips_r32(IFXMIPS_SSC_RB);
for (i = 0; i < rx_valid_cnt; i++)
{
@@ -134,12 +134,12 @@ rx_int (struct ifx_ssc_port *info)
{
disable_irq(IFXMIPS_SSC_RIR);
wake_up_interruptible (&info->rwait);
} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (readl(IFXMIPS_SSC_RXCNT) == 0))
} else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0))
{
if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
ifxmips_w32((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
else
writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
}
}
@@ -148,8 +148,8 @@ tx_int (struct ifx_ssc_port *info)
{
int fifo_space, fill, i;
fifo_space = ((readl(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
- ((readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
fifo_space = ((ifxmips_r32(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
- ((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
if (fifo_space == 0)
return;
@@ -162,7 +162,7 @@ tx_int (struct ifx_ssc_port *info)
for (i = 0; i < fill / 4; i++)
{
// at first 32 bit access
writel(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
ifxmips_w32(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
info->txbuf_ptr += 4;
}
@@ -224,7 +224,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
unsigned long flags;
local_irq_save (flags);
state = readl(IFXMIPS_SSC_STATE);
state = ifxmips_r32(IFXMIPS_SSC_STATE);
if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
info->stats.rxUnErr++;
@@ -252,7 +252,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
}
if (write_back)
writel(write_back, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(write_back, IFXMIPS_SSC_WHBSTATE);
local_irq_restore (flags);
@@ -278,12 +278,12 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
// complete word. The disable cuts the transmission immediatly and
// releases the chip selects. This could result in unpredictable
// behavior of connected external devices!
enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
// flush fifos
writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
// free txbuf
if (info->txbuf != NULL)
@@ -302,10 +302,10 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
// clear error flags
writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
if (enabled)
writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
}
@@ -343,22 +343,22 @@ ifx_ssc_open (struct inode *inode, struct file *filp)
disable_irq(IFXMIPS_SSC_EIR);
/* Flush and enable TX/RX FIFO */
writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
/* logically flush the software FIFOs */
info->rxbuf_ptr = 0;
info->txbuf_ptr = 0;
/* clear all error bits */
writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
// clear pending interrupts
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_RIR);
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_TIR);
mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
return 0;
}
@@ -382,7 +382,7 @@ ifx_ssc_close (struct inode *inode, struct file *filp)
if (!info)
return -ENXIO;
writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
ifx_ssc_abort(info);
@@ -451,13 +451,13 @@ ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_
enable_irq(IFXMIPS_SSC_RIR);
} else {
local_irq_restore(flags);
if (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
if (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
return -EBUSY;
enable_irq(IFXMIPS_SSC_RIR);
if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
writel(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
ifxmips_w32(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
else
writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
}
__add_wait_queue (&info->rwait, &wait);
@@ -643,12 +643,12 @@ ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
{
unsigned long tmp;
tmp = readl(IFXMIPS_SSC_SFSTAT);
tmp = ifxmips_r32(IFXMIPS_SSC_SFSTAT);
info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
tmp = readl(IFXMIPS_SSC_SFCON);
tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
@@ -661,7 +661,7 @@ ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
{
unsigned long tmp;
tmp = readl(IFXMIPS_SSC_SFCON);
tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
@@ -686,7 +686,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
return -EINVAL;
// read interrupt bits (they're not changed here)
tmp = readl(IFXMIPS_SSC_SFCON) &
tmp = ifxmips_r32(IFXMIPS_SSC_SFCON) &
(IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
// set all values with respect to it's bit position (for data and pause
@@ -698,7 +698,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
writel(tmp, IFXMIPS_SSC_SFCON);
ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
return 0;
}
@@ -711,12 +711,12 @@ ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
return -EINVAL;
if ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
|| (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
if ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
|| (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
return -EBUSY;
tmp = (readl(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
writel(tmp, IFXMIPS_SSC_SFCON);
tmp = (ifxmips_r32(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
info->opts.modeRxTx = val;
return 0;
@@ -766,20 +766,20 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info)
local_irq_save (flags);
writel(bits, IFXMIPS_SSC_CON);
writel((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
ifxmips_w32(bits, IFXMIPS_SSC_CON);
ifxmips_w32((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
(info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
writel(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
ifxmips_w32(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
//master mode
if (opts->masterSelect)
writel(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
else
writel(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
// init serial framing
writel(0, IFXMIPS_SSC_SFCON);
ifxmips_w32(0, IFXMIPS_SSC_SFCON);
/* set up the port pins */
//check for general requirements to switch (external) pad/pin characteristics
/* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
@@ -823,23 +823,23 @@ ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
local_irq_save (flags);
enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
wmb();
if (br > 0xffff || ((br == 0) &&
((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
local_irq_restore (flags);
printk ("%s: invalid baudrate %u\n", __func__, baud);
return -EINVAL;
}
writel(br, IFXMIPS_SSC_BR);
ifxmips_w32(br, IFXMIPS_SSC_BR);
if (enabled)
writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
local_irq_restore(flags);
@@ -853,8 +853,8 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
unsigned long flags;
bool enabled;
enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
if (ifx_ssc_sethwopts (info) < 0)
{
@@ -871,14 +871,14 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
local_irq_save (flags);
/* TX FIFO */
writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
/* RX FIFO */
writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
local_irq_restore (flags);
if (enabled)
writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
return 0;
}
@@ -926,7 +926,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
/* if the buffers are not empty then the port is */
/* busy and we shouldn't change things on-the-fly! */
if (!info->txbuf || !info->rxbuf ||
(readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
(ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
ret_val = -EBUSY;
break;
}
@@ -967,7 +967,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
break;
case IFX_SSC_RXTX_MODE_GET:
tmp = readl(IFXMIPS_SSC_CON) &
tmp = ifxmips_r32(IFXMIPS_SSC_CON) &
(~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
if (from_kernel)
*((unsigned int *) data) = tmp;
@@ -991,7 +991,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
if (tmp > IFX_SSC_MAX_GPO_OUT)
ret_val = -EINVAL;
else
writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
IFXMIPS_SSC_WHBGPOSTAT);
break;
case IFX_SSC_GPO_OUT_CLR:
@@ -1004,12 +1004,12 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
if (tmp > IFX_SSC_MAX_GPO_OUT)
ret_val = -EINVAL;
else {
writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
IFXMIPS_SSC_WHBGPOSTAT);
}
break;
case IFX_SSC_GPO_OUT_GET:
tmp = readl(IFXMIPS_SSC_GPOSTAT);
tmp = ifxmips_r32(IFXMIPS_SSC_GPOSTAT);
if (from_kernel)
*((unsigned int *) data) = tmp;
else if (copy_to_user ((void *) data,
@@ -1053,7 +1053,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
/* if the buffers are not empty then the port is */
/* busy and we shouldn't change things on-the-fly! */
if (!info->txbuf || !info->rxbuf ||
(readl(IFXMIPS_SSC_STATE)
(ifxmips_r32(IFXMIPS_SSC_STATE)
& IFX_SSC_STATE_BUSY)) {
ret_val = -EBUSY;
break;
@@ -1165,14 +1165,14 @@ ifx_ssc_init (void)
info->mapbase = IFXMIPS_SSC_BASE_ADDR;
}
writel(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
ifxmips_w32(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
init_waitqueue_head (&info->rwait);
local_irq_save (flags);
// init serial framing register
writel(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
ifxmips_w32(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info);
if (ret_val)
@@ -1197,7 +1197,7 @@ ifx_ssc_init (void)
local_irq_restore (flags);
goto irqerr;
}
writel(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
ifxmips_w32(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
//enable_irq(IFXMIPS_SSC_TIR);
//enable_irq(IFXMIPS_SSC_RIR);
@@ -1233,7 +1233,7 @@ ifx_ssc_cleanup_module (void)
int i;
for (i = 0; i < PORT_CNT; i++) {
writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
free_irq(IFXMIPS_SSC_TIR, &isp[i]);
free_irq(IFXMIPS_SSC_RIR, &isp[i]);
free_irq(IFXMIPS_SSC_EIR, &isp[i]);

2
target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
View File

@@ -135,7 +135,7 @@ ifxmips_mtd_probe (void)
struct mtd_partition *parts = NULL;
unsigned long uimage_size;
writel(0x1d7ff, IFXMIPS_EBU_BUSCON0);
ifxmips_w32(0x1d7ff, IFXMIPS_EBU_BUSCON0);
ifxmips_map.read = ifxmips_read16;
ifxmips_map.write = ifxmips_write16;

18
target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
View File

@@ -60,8 +60,8 @@ ifxmips_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
phy_data;
while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
writel(val, IFXMIPS_PPE32_MDIO_ACC);
while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
}
unsigned short
@@ -71,9 +71,9 @@ ifxmips_read_mdio (u32 phy_addr, u32 phy_reg)
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
writel(val, IFXMIPS_PPE32_MDIO_ACC);
while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val;
}
@@ -374,13 +374,13 @@ ifxmips_sw_chip_init (int mode)
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
if(mode == REV_MII_MODE)
writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
else if(mode == MII_MODE)
writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
wmb();
}

74
target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
View File

@@ -88,7 +88,7 @@ static void
ifxmipsasc_stop_rx (struct uart_port *port)
{
/* clear the RX enable bit */
writel(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
ifxmips_w32(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
}
static void
@@ -104,12 +104,12 @@ ifxmipsasc_rx_chars (struct uart_port *port)
struct tty_struct *tty = port->info->tty;
unsigned int ch = 0, rsr = 0, fifocnt;
fifocnt = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
fifocnt = ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
while (fifocnt--)
{
u8 flag = TTY_NORMAL;
ch = readl(IFXMIPS_ASC1_RBUF);
rsr = (readl(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
ch = ifxmips_r32(IFXMIPS_ASC1_RBUF);
rsr = (ifxmips_r32(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tty);
port->icount.rx++;
@@ -120,14 +120,14 @@ ifxmipsasc_rx_chars (struct uart_port *port)
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
}
rsr &= port->read_status_mask;
@@ -166,11 +166,11 @@ ifxmipsasc_tx_chars (struct uart_port *port)
return;
}
while(((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
while(((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
{
if (port->x_char) {
writel(port->x_char, IFXMIPS_ASC1_TBUF);
ifxmips_w32(port->x_char, IFXMIPS_ASC1_TBUF);
port->icount.tx++;
port->x_char = 0;
continue;
@@ -179,7 +179,7 @@ ifxmipsasc_tx_chars (struct uart_port *port)
if (uart_circ_empty(xmit))
break;
writel(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
@@ -191,7 +191,7 @@ ifxmipsasc_tx_chars (struct uart_port *port)
static irqreturn_t
ifxmipsasc_tx_int (int irq, void *port)
{
writel(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
ifxmips_w32(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
ifxmipsasc_start_tx(port);
mask_and_ack_ifxmips_irq(irq);
@@ -202,7 +202,7 @@ static irqreturn_t
ifxmipsasc_er_int (int irq, void *port)
{
/* clear any pending interrupts */
writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
return IRQ_HANDLED;
@@ -211,7 +211,7 @@ ifxmipsasc_er_int (int irq, void *port)
static irqreturn_t
ifxmipsasc_rx_int (int irq, void *port)
{
writel(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
ifxmips_w32(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
ifxmipsasc_rx_chars((struct uart_port *) port);
mask_and_ack_ifxmips_irq(irq);
@@ -223,7 +223,7 @@ ifxmipsasc_tx_empty (struct uart_port *port)
{
int status;
status = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
status = ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
@@ -251,17 +251,17 @@ ifxmipsasc1_hw_init (void)
{
/* this setup was probably already done in ROM/u-boot but we do it again*/
/* TODO: GPIO pins are multifunction */
writel(readl(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
writel((readl(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
writel(0, IFXMIPS_ASC1_PISEL);
writel(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
ifxmips_w32((ifxmips_r32(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
ifxmips_w32(0, IFXMIPS_ASC1_PISEL);
ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
writel(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
wmb ();
/*framing, overrun, enable */
writel(readl(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
IFXMIPS_ASC1_CON);
}
@@ -299,7 +299,7 @@ ifxmipsasc_startup (struct uart_port *port)
goto err2;
}
writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
IFXMIPS_ASC1_IRNREN);
local_irq_restore(flags);
@@ -325,13 +325,13 @@ ifxmipsasc_shutdown (struct uart_port *port)
/*
* disable the baudrate generator to disable the ASC
*/
writel(0, IFXMIPS_ASC1_CON);
ifxmips_w32(0, IFXMIPS_ASC1_CON);
/* flush and then disable the fifos */
writel(readl(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
writel(readl(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
writel(readl(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
writel(readl(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
}
static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
@@ -395,7 +395,7 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
local_irq_save(flags);
/* set up CON */
writel(readl(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
@@ -403,22 +403,22 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
quot = quot / 2 - 1;
/* disable the baudrate generator */
writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
/* make sure the fractional divider is off */
writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
/* set up to use divisor of 2 */
writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
/* now we can write the new baudrate into the register */
writel(quot, IFXMIPS_ASC1_BG);
ifxmips_w32(quot, IFXMIPS_ASC1_BG);
/* turn the baudrate generator back on */
writel(readl(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
/* enable rx */
writel(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
ifxmips_w32(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
local_irq_restore(flags);
}
@@ -507,7 +507,7 @@ ifxmipsasc_console_write (struct console *co, const char *s, u_int count)
/* wait until the FIFO is not full */
do
{
fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
fifocnt = (ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
@@ -518,14 +518,14 @@ ifxmipsasc_console_write (struct console *co, const char *s, u_int count)
if (s[i] == '\n')
{
writel('\r', IFXMIPS_ASC1_TBUF);
ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
do
{
fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
fifocnt = (ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
} while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
}
writel(s[i], IFXMIPS_ASC1_TBUF);
ifxmips_w32(s[i], IFXMIPS_ASC1_TBUF);
}
local_irq_restore(flags);

42
target/linux/ifxmips/files/drivers/watchdog/ifxmips_wdt.c
View File

@@ -46,8 +46,8 @@ ifxmips_wdt_enable (unsigned int timeout)
int retval = 0;
/* clock divider & prewarning limit */
wdt_clkdiv = 1 << (7 * IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR)));
wdt_pwl = 0x8000 >> IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR));
wdt_clkdiv = 1 << (7 * IFXMIPS_BIU_WDT_CR_CLKDIV_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR)));
wdt_pwl = 0x8000 >> IFXMIPS_BIU_WDT_CR_PWL_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR));
//TODO
printk("WARNING FUNCTION CALL MISSING!!!");
@@ -68,21 +68,21 @@ ifxmips_wdt_enable (unsigned int timeout)
}
/* Write first part of password access */
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
wdt_cr &= (!IFXMIPS_BIU_WDT_CR_PW_SET(0xff) &
!IFXMIPS_BIU_WDT_CR_PWL_SET(0x3) &
!IFXMIPS_BIU_WDT_CR_CLKDIV_SET(0x3) &
!IFXMIPS_BIU_WDT_CR_RELOAD_SET(0xffff));
wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) |
IFXMIPS_BIU_WDT_CR_PWL_SET(IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR))) |
IFXMIPS_BIU_WDT_CR_CLKDIV_SET(IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR))) |
IFXMIPS_BIU_WDT_CR_PWL_SET(IFXMIPS_BIU_WDT_CR_PWL_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR))) |
IFXMIPS_BIU_WDT_CR_CLKDIV_SET(IFXMIPS_BIU_WDT_CR_CLKDIV_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR))) |
IFXMIPS_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
IFXMIPS_BIU_WDT_CR_GEN);
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
printk("watchdog enabled\n");
@@ -93,8 +93,8 @@ out:
void
ifxmips_wdt_disable (void)
{
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2), IFXMIPS_BIU_WDT_CR);
ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2), IFXMIPS_BIU_WDT_CR);
printk("watchdog disabled\n");
}
@@ -105,9 +105,9 @@ ifxmips_wdt_enable_feature (int en, int type)
{
unsigned int wdt_cr = 0;
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
if (en)
{
@@ -118,7 +118,7 @@ ifxmips_wdt_enable_feature (int en, int type)
wdt_cr |= IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2);
}
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@@ -126,14 +126,14 @@ ifxmips_wdt_prewarning_limit (int pwl)
{
unsigned int wdt_cr = 0;
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xf300ffff;
wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_PWL_SET(pwl));
/* Set reload value in second password access */
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@@ -141,14 +141,14 @@ ifxmips_wdt_set_clkdiv (int clkdiv)
{
unsigned int wdt_cr = 0;
wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xfc00ffff;
wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_CLKDIV_SET(clkdiv));
/* Set reload value in second password access */
writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
static int
@@ -189,7 +189,7 @@ ifxmips_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
break;
case IFXMIPS_WDT_IOC_GET_STATUS:
user_arg = readl(IFXMIPS_BIU_WDT_SR);
user_arg = ifxmips_r32(IFXMIPS_BIU_WDT_SR);
copy_to_user((int*)arg, (int*)&user_arg, sizeof(int));
break;
@@ -244,9 +244,9 @@ ifxmips_wdt_register_proc_read (char *buf, char **start, off_t offset, int count
len += sprintf (buf + len, "IFXMIPS_BIU_WDT_PROC_READ\n");
len += sprintf (buf + len, "IFXMIPS_BIU_WDT_CR(0x%08x) : 0x%08x\n",
(unsigned int)IFXMIPS_BIU_WDT_CR, readl(IFXMIPS_BIU_WDT_CR));
(unsigned int)IFXMIPS_BIU_WDT_CR, ifxmips_r32(IFXMIPS_BIU_WDT_CR));
len += sprintf (buf + len, "IFXMIPS_BIU_WDT_SR(0x%08x) : 0x%08x\n",
(unsigned int)IFXMIPS_BIU_WDT_SR, readl(IFXMIPS_BIU_WDT_SR));
(unsigned int)IFXMIPS_BIU_WDT_SR, ifxmips_r32(IFXMIPS_BIU_WDT_SR));
*eof = 1;