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mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00

[ppc40x] merge 2.6.28 patches

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16929 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2009-07-20 08:11:07 +00:00
parent 23651be81b
commit c2fd5acd2e
8 changed files with 80 additions and 134 deletions

View File

@@ -49,7 +49,7 @@
static int __init ppc40x_probe(void)
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-openrb-light.c
@@ -0,0 +1,41 @@
@@ -0,0 +1,69 @@
+/*
+ * Old U-boot compatibility for OpenRB Light board
+ *
@@ -74,8 +74,36 @@
+
+static bd_t bd;
+
+static void fixup_cf_card(void)
+{
+#define DCRN_CPC0_PCI_BASE 0xf9
+#define CF_CS0_BASE 0xff100000
+#define CF_CS1_BASE 0xff200000
+
+ /* Turn on PerWE instead of PCIsomething */
+ mtdcr(DCRN_CPC0_PCI_BASE,
+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
+
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+#undef DCRN_CPC0_PCI_BASE
+#undef CF_CS0_BASE
+#undef CF_CS1_BASE
+}
+
+static void openrb_light_fixups(void)
+{
+ fixup_cf_card();
+ ibm405ep_fixup_clocks(33333000);
+ ibm4xx_sdram_fixup_memsize();
+ dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
@@ -93,7 +121,7 @@
+
--- /dev/null
+++ b/arch/powerpc/boot/dts/openrb-light.dts
@@ -0,0 +1,244 @@
@@ -0,0 +1,252 @@
+/*
+ * Device Tree Source for OpenRB Light board
+ *
@@ -273,6 +301,14 @@
+ */
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ cf_card@ff100000 {
+ compatible = "magicbox-cf";
+ reg = <0x00000000 0xff100000 0x00001000
+ 0x00000000 0xff200000 0x00001000>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
+ };
+
+ nor_flash@ff800000 {
+ compatible = "cfi-flash";
+ bank-width = <2>;