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ar71xx: use a dummy irq chip for WMAC and PCIe irq hadling
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29107 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -114,6 +114,8 @@ static void ar934x_wmac_init(void)
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ar9xxx_wmac_device.name = "ar934x_wmac";
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ar9xxx_wmac_device.name = "ar934x_wmac";
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ar9xxx_wmac_resources[0].start = AR934X_WMAC_BASE;
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ar9xxx_wmac_resources[0].start = AR934X_WMAC_BASE;
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ar9xxx_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
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ar9xxx_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
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ar9xxx_wmac_resources[1].start = AR934X_IP2_IRQ_WMAC;
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ar9xxx_wmac_resources[1].start = AR934X_IP2_IRQ_WMAC;
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if (ar71xx_ref_freq == MHZ_25)
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if (ar71xx_ref_freq == MHZ_25)
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ar9xxx_wmac_data.is_clk_25mhz = true;
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ar9xxx_wmac_data.is_clk_25mhz = true;
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}
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}
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@ -231,6 +231,39 @@ static void __init ar71xx_misc_irq_init(void)
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setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
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setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
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}
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}
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static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ar71xx_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
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if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL)
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generic_handle_irq(AR934X_IP2_IRQ_PCIE);
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else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL)
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generic_handle_irq(AR934X_IP2_IRQ_WMAC);
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else
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spurious_interrupt();
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enable_irq(irq);
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}
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static void ar934x_ip2_irq_init(void)
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{
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int i;
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for (i = AR934X_IP2_IRQ_BASE;
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i < AR934X_IP2_IRQ_BASE + AR934X_IP2_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
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}
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/*
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/*
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* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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* these devices typically allocate coherent DMA memory, however the
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* these devices typically allocate coherent DMA memory, however the
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@ -372,6 +405,11 @@ void __init arch_init_irq(void)
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ar71xx_misc_irq_init();
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ar71xx_misc_irq_init();
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if (ar71xx_soc == AR71XX_SOC_AR9341 ||
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ar71xx_soc == AR71XX_SOC_AR9342 ||
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ar71xx_soc == AR71XX_SOC_AR9344)
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ar934x_ip2_irq_init();
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cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
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cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
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ar71xx_gpio_irq_init();
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ar71xx_gpio_irq_init();
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@ -81,9 +81,12 @@ int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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case AR71XX_SOC_AR7242:
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ret = ar724x_pcibios_init(AR71XX_CPU_IRQ_IP2);
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break;
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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case AR71XX_SOC_AR9344:
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ret = ar724x_pcibios_init(AR71XX_CPU_IRQ_IP2);
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ret = ar724x_pcibios_init(AR934X_IP2_IRQ_PCIE);
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break;
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break;
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default:
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default:
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@ -89,7 +89,9 @@
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#define AR71XX_GPIO_IRQ_BASE 40
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#define AR71XX_GPIO_IRQ_BASE 40
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#define AR71XX_GPIO_IRQ_COUNT 32
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#define AR71XX_GPIO_IRQ_COUNT 32
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#define AR71XX_PCI_IRQ_BASE 72
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#define AR71XX_PCI_IRQ_BASE 72
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#define AR71XX_PCI_IRQ_COUNT 8
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#define AR71XX_PCI_IRQ_COUNT 6
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#define AR934X_IP2_IRQ_BASE 78
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#define AR934X_IP2_IRQ_COUNT 2
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#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
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#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
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#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
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#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
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@ -119,6 +121,9 @@
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#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
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#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
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#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
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#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
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#define AR934X_IP2_IRQ_WMAC (AR934X_IP2_IRQ_BASE + 0)
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#define AR934X_IP2_IRQ_PCIE (AR934X_IP2_IRQ_BASE + 1)
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extern u32 ar71xx_ahb_freq;
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extern u32 ar71xx_ahb_freq;
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extern u32 ar71xx_cpu_freq;
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extern u32 ar71xx_cpu_freq;
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extern u32 ar71xx_ddr_freq;
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extern u32 ar71xx_ddr_freq;
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