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git://projects.qi-hardware.com/openwrt-xburst.git
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amazon: update amazon target to kernel 3.3
This is just compile tested, my device is currently not working. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31706 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@@ -34,10 +34,11 @@
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#include <asm/irq.h>
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#include <asm/time.h>
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static void amazon_disable_irq(unsigned int irq_nr)
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static void amazon_disable_irq(struct irq_data *d)
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{
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int i;
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u32 amazon_ier = AMAZON_ICU_IM0_IER;
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unsigned int irq_nr = d->irq;
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if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
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amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
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@@ -53,11 +54,12 @@ static void amazon_disable_irq(unsigned int irq_nr)
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}
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}
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static void amazon_mask_and_ack_irq(unsigned int irq_nr)
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static void amazon_mask_and_ack_irq(struct irq_data *d)
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{
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int i;
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u32 amazon_ier = AMAZON_ICU_IM0_IER;
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u32 amazon_isr = AMAZON_ICU_IM0_ISR;
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unsigned int irq_nr = d->irq;
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if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0){
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amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
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@@ -77,10 +79,11 @@ static void amazon_mask_and_ack_irq(unsigned int irq_nr)
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}
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}
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static void amazon_enable_irq(unsigned int irq_nr)
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static void amazon_enable_irq(struct irq_data *d)
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{
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int i;
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u32 amazon_ier = AMAZON_ICU_IM0_IER;
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unsigned int irq_nr = d->irq;
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if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
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amazon_writel(amazon_readl(amazon_ier) | AMAZON_DMA_H_MASK, amazon_ier);
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@@ -96,29 +99,21 @@ static void amazon_enable_irq(unsigned int irq_nr)
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}
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}
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static unsigned int amazon_startup_irq(unsigned int irq)
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static unsigned int amazon_startup_irq(struct irq_data *d)
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{
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amazon_enable_irq(irq);
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amazon_enable_irq(d);
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return 0;
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}
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static void amazon_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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amazon_enable_irq(irq);
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}
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}
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static struct irq_chip amazon_irq_type = {
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.name = "AMAZON",
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.startup = amazon_startup_irq,
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.enable = amazon_enable_irq,
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.disable = amazon_disable_irq,
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.unmask = amazon_enable_irq,
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.ack = amazon_mask_and_ack_irq,
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.mask = amazon_disable_irq,
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.mask_ack = amazon_mask_and_ack_irq,
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.end = amazon_end_irq
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.irq_startup = amazon_startup_irq,
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.irq_enable = amazon_enable_irq,
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.irq_disable = amazon_disable_irq,
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.irq_unmask = amazon_enable_irq,
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.irq_ack = amazon_mask_and_ack_irq,
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.irq_mask = amazon_disable_irq,
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.irq_mask_ack = amazon_mask_and_ack_irq,
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};
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/* Cascaded interrupts from IM0-4 */
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@@ -178,7 +173,7 @@ void __init arch_init_irq(void)
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}
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for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++)
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set_irq_chip_and_handler(i, &amazon_irq_type,
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irq_set_chip_and_handler(i, &amazon_irq_type,
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handle_level_irq);
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set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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