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Upgrade to Linux 2.6.19
- Includes large parts of the patch from #1021 by dpalffy - Includes RB532 NAND driver changes by n0-1 git-svn-id: svn://svn.openwrt.org/openwrt/trunk@5789 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
@@ -1,6 +1,6 @@
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diff -ur linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
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--- linux.old/arch/mips/kernel/genex.S 2006-10-16 19:09:36.000000000 +0200
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+++ linux.dev/arch/mips/kernel/genex.S 2006-10-16 19:06:50.000000000 +0200
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diff -urN linux-2.6.19.ref/arch/mips/kernel/genex.S linux-2.6.19/arch/mips/kernel/genex.S
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--- linux-2.6.19.ref/arch/mips/kernel/genex.S 2006-11-29 22:57:37.000000000 +0100
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+++ linux-2.6.19/arch/mips/kernel/genex.S 2006-12-04 21:34:09.000000000 +0100
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@@ -73,6 +73,10 @@
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.set push
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.set mips3
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@@ -12,10 +12,10 @@ diff -ur linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S
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mfc0 k1, CP0_CAUSE
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li k0, 31<<2
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andi k1, k1, 0x7c
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diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2006-10-16 19:09:36.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2006-10-16 19:08:46.000000000 +0200
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@@ -14,6 +14,15 @@
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diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
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--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c 2006-12-04 21:34:04.000000000 +0100
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+++ linux-2.6.19/arch/mips/mm/c-r4k.c 2006-12-04 21:34:09.000000000 +0100
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@@ -13,6 +13,15 @@
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#include <linux/mm.h>
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#include <linux/bitops.h>
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@@ -31,7 +31,7 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cache.h>
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@@ -30,6 +39,9 @@
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@@ -29,6 +38,9 @@
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#include <asm/cacheflush.h> /* for run_uncached() */
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@@ -41,40 +41,37 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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/*
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* Special Variant of smp_call_function for use by cache functions:
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*
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@@ -94,7 +106,9 @@
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@@ -93,6 +105,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache_page = blast_dcache_page;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page = blast_dcache16_page;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
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@@ -106,7 +120,9 @@
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_page = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -107,6 +122,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
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@@ -118,7 +134,9 @@
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_page_indexed = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -121,6 +139,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache = blast_dcache;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache = blast_dcache16;
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else if (dc_lsize == 32)
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r4k_blast_dcache = blast_dcache32;
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@@ -527,6 +545,9 @@
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -538,6 +559,9 @@
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r4k_blast_icache();
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else
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protected_blast_icache_range(start, end);
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@@ -84,17 +81,17 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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}
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static void r4k_flush_icache_range(unsigned long start, unsigned long end)
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@@ -683,6 +704,8 @@
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@@ -618,6 +642,8 @@
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unsigned long addr = (unsigned long) arg;
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (dc_lsize)
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store && scache_size)
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protected_writeback_scache_line(addr & ~(sc_lsize - 1));
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@@ -1189,6 +1212,16 @@
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static inline void coherency_setup(void)
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@@ -1135,6 +1161,16 @@
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static void __init coherency_setup(void)
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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+#ifdef CONFIG_BCM947XX
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@@ -110,7 +107,7 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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@@ -1227,6 +1260,15 @@
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@@ -1173,6 +1209,15 @@
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/* Default cache error handler for R4000 and R5000 family */
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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@@ -126,21 +123,21 @@ diff -ur linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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probe_pcache();
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setup_scache();
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diff -ur linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
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--- linux.old/arch/mips/mm/tlbex.c 2006-10-16 19:09:36.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex.c 2006-10-16 19:06:50.000000000 +0200
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@@ -38,6 +38,10 @@
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/* #define DEBUG_TLB */
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diff -urN linux-2.6.19.ref/arch/mips/mm/tlbex.c linux-2.6.19/arch/mips/mm/tlbex.c
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--- linux-2.6.19.ref/arch/mips/mm/tlbex.c 2006-12-04 21:33:48.000000000 +0100
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+++ linux-2.6.19/arch/mips/mm/tlbex.c 2006-12-04 21:34:09.000000000 +0100
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@@ -1174,6 +1174,10 @@
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#endif
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}
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+#ifdef CONFIG_BCM947XX
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+extern int bcm4710;
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+#endif
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+
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static __init int __attribute__((unused)) r45k_bvahwbug(void)
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static void __init build_r4000_tlb_refill_handler(void)
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{
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/* XXX: We should probe for the presence of this bug, but we don't. */
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@@ -1184,6 +1188,12 @@
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u32 *p = tlb_handler;
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@@ -1188,6 +1192,12 @@
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memset(relocs, 0, sizeof(relocs));
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memset(final_handler, 0, sizeof(final_handler));
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@@ -153,9 +150,9 @@ diff -ur linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
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/*
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* create the plain linear handler
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*/
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diff -ur linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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--- linux.old/include/asm-mips/r4kcache.h 2006-10-16 19:09:36.000000000 +0200
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+++ linux.dev/include/asm-mips/r4kcache.h 2006-10-16 19:09:11.000000000 +0200
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diff -urN linux-2.6.19.ref/include/asm-mips/r4kcache.h linux-2.6.19/include/asm-mips/r4kcache.h
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--- linux-2.6.19.ref/include/asm-mips/r4kcache.h 2006-11-29 22:57:37.000000000 +0100
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+++ linux-2.6.19/include/asm-mips/r4kcache.h 2006-12-04 21:34:09.000000000 +0100
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@@ -17,6 +17,18 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsmtregs.h>
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@@ -356,10 +353,10 @@ diff -ur linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcac
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+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
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#endif /* _ASM_R4KCACHE_H */
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diff -ur linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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--- linux.old/include/asm-mips/stackframe.h 2006-10-16 19:09:36.000000000 +0200
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+++ linux.dev/include/asm-mips/stackframe.h 2006-10-16 19:06:50.000000000 +0200
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@@ -361,6 +361,10 @@
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diff -urN linux-2.6.19.ref/include/asm-mips/stackframe.h linux-2.6.19/include/asm-mips/stackframe.h
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--- linux-2.6.19.ref/include/asm-mips/stackframe.h 2006-11-29 22:57:37.000000000 +0100
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+++ linux-2.6.19/include/asm-mips/stackframe.h 2006-12-04 21:34:09.000000000 +0100
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@@ -334,6 +334,10 @@
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.macro RESTORE_SP_AND_RET
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LONG_L sp, PT_R29(sp)
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.set mips3
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