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mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-11-27 17:15:00 +02:00

[backfire] remove unused kernel config, files & patches in 10.03

git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@20666 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nico 2010-04-03 01:57:27 +00:00
parent 3256895004
commit cb341b7ccb
549 changed files with 0 additions and 265423 deletions

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@ -1,291 +0,0 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_AG71XX=y
CONFIG_AG71XX_AR8216_SUPPORT=y
# CONFIG_AG71XX_DEBUG is not set
# CONFIG_AG71XX_DEBUG_FS is not set
# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
# CONFIG_AR7 is not set
CONFIG_AR71XX_DEV_AP91_ETH=y
CONFIG_AR71XX_DEV_AP91_PCI=y
CONFIG_AR71XX_DEV_AP94_PCI=y
CONFIG_AR71XX_DEV_AR913X_WMAC=y
CONFIG_AR71XX_DEV_DSA=y
CONFIG_AR71XX_DEV_GPIO_BUTTONS=y
CONFIG_AR71XX_DEV_LEDS_GPIO=y
CONFIG_AR71XX_DEV_M25P80=y
CONFIG_AR71XX_DEV_PB42_PCI=y
CONFIG_AR71XX_DEV_PB9X_PCI=y
CONFIG_AR71XX_DEV_USB=y
CONFIG_AR71XX_MACH_AP81=y
CONFIG_AR71XX_MACH_AP83=y
CONFIG_AR71XX_MACH_AW_NR580=y
CONFIG_AR71XX_MACH_DIR_600_A1=y
CONFIG_AR71XX_MACH_DIR_615_C1=y
CONFIG_AR71XX_MACH_DIR_825_B1=y
CONFIG_AR71XX_MACH_MZK_W04NU=y
CONFIG_AR71XX_MACH_MZK_W300NH=y
CONFIG_AR71XX_MACH_PB42=y
CONFIG_AR71XX_MACH_PB44=y
CONFIG_AR71XX_MACH_PB92=y
CONFIG_AR71XX_MACH_RB4XX=y
CONFIG_AR71XX_MACH_RB750=y
CONFIG_AR71XX_MACH_TEW_632BRP=y
CONFIG_AR71XX_MACH_TL_WR1043ND=y
CONFIG_AR71XX_MACH_TL_WR741ND=y
CONFIG_AR71XX_MACH_TL_WR841N_V1=y
CONFIG_AR71XX_MACH_TL_WR941ND=y
CONFIG_AR71XX_MACH_UBNT=y
CONFIG_AR71XX_MACH_WNDR3700=y
CONFIG_AR71XX_MACH_WNR2000=y
CONFIG_AR71XX_MACH_WP543=y
CONFIG_AR71XX_MACH_WRT160NL=y
CONFIG_AR71XX_MACH_WRT400N=y
CONFIG_AR71XX_MACH_WZR_HP_G300NH=y
CONFIG_AR71XX_NVRAM=y
CONFIG_AR71XX_WDT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ATHEROS_AR71XX=y
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
CONFIG_BITREVERSE=y
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CEVT_R4K=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_CAVIUM_OCTEON is not set
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2E is not set
# CONFIG_CPU_LOONGSON2F is not set
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR2=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CSRC_R4K=y
CONFIG_CSRC_R4K_LIB=y
CONFIG_DECOMPRESS_LZMA=y
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
# CONFIG_FSNOTIFY is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_NXP_74HC153=y
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_SYSFS=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HW_HAS_PCI=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_GPIO=y
CONFIG_ICPLUS_PHY=y
CONFIG_IMAGE_CMDLINE_HACK=y
# CONFIG_INITRAMFS_COMPRESSION_LZO is not set
CONFIG_INITRAMFS_ROOT_GID=0
CONFIG_INITRAMFS_ROOT_UID=0
CONFIG_INITRAMFS_SOURCE="../../root"
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
CONFIG_IRQ_CPU=y
# CONFIG_LEDS_GPIO is not set
# CONFIG_LEDS_RB750 is not set
# CONFIG_LEDS_WNDR3700_USB is not set
CONFIG_LOONGSON_UART_BASE=y
# CONFIG_M25PXX_USE_FAST_READ is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_LOONGSON is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_MICREL_PHY=y
# CONFIG_MIKROTIK_RB532 is not set
CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MTD_AR91XX_FLASH=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_MYLOADER_PARTS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_RB4XX=y
CONFIG_MTD_NAND_RB750=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_WRT160NL_PARTS=y
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
CONFIG_MYLOADER=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_AR7240=y
CONFIG_NET_DSA_MV88E6060=y
CONFIG_NET_DSA_MV88E6063=y
# CONFIG_NET_DSA_MV88E6123_61_65 is not set
# CONFIG_NET_DSA_MV88E6131 is not set
# CONFIG_NET_DSA_MV88E6XXX is not set
# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
# CONFIG_NET_DSA_TAG_DSA is not set
# CONFIG_NET_DSA_TAG_EDSA is not set
CONFIG_NET_DSA_TAG_QINQ=y
CONFIG_NET_DSA_TAG_TRAILER=y
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PHYLIB=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_POWERTV is not set
CONFIG_RTL8306_PHY=y
CONFIG_RTL8366RB_PHY=y
CONFIG_RTL8366S_PHY=y
CONFIG_RTL8366_SMI=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_EXTENDED is not set
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SPI=y
CONFIG_SPI_AP83=y
CONFIG_SPI_AR71XX=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_PB44=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_VSC7385 is not set
CONFIG_SWCONFIG=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
# CONFIG_TC35815 is not set
# CONFIG_TINY_RCU is not set
CONFIG_TRAD_SIGNALS=y
# CONFIG_TREE_PREEMPT_RCU is not set
CONFIG_TREE_RCU=y
CONFIG_USB_SUPPORT=y
CONFIG_YAFFS_9BYTE_TAGS=y
CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
CONFIG_YAFFS_FS=y
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_YAFFS_YAFFS1=y
CONFIG_YAFFS_YAFFS2=y
CONFIG_ZONE_DMA_FLAG=0

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@ -1,316 +0,0 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_AG71XX=y
CONFIG_AG71XX_AR8216_SUPPORT=y
# CONFIG_AG71XX_DEBUG is not set
# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
# CONFIG_AR7 is not set
CONFIG_AR71XX_DEV_AP91_ETH=y
CONFIG_AR71XX_DEV_AP91_PCI=y
CONFIG_AR71XX_DEV_AP94_PCI=y
CONFIG_AR71XX_DEV_AR913X_WMAC=y
CONFIG_AR71XX_DEV_DSA=y
CONFIG_AR71XX_DEV_GPIO_BUTTONS=y
CONFIG_AR71XX_DEV_LEDS_GPIO=y
CONFIG_AR71XX_DEV_M25P80=y
CONFIG_AR71XX_DEV_PB42_PCI=y
CONFIG_AR71XX_DEV_PB9X_PCI=y
CONFIG_AR71XX_DEV_USB=y
CONFIG_AR71XX_MACH_AP81=y
CONFIG_AR71XX_MACH_AP83=y
CONFIG_AR71XX_MACH_AW_NR580=y
CONFIG_AR71XX_MACH_DIR_600_A1=y
CONFIG_AR71XX_MACH_DIR_615_C1=y
CONFIG_AR71XX_MACH_DIR_825_B1=y
CONFIG_AR71XX_MACH_MZK_W04NU=y
CONFIG_AR71XX_MACH_MZK_W300NH=y
CONFIG_AR71XX_MACH_PB42=y
CONFIG_AR71XX_MACH_PB44=y
CONFIG_AR71XX_MACH_PB92=y
CONFIG_AR71XX_MACH_RB4XX=y
CONFIG_AR71XX_MACH_RB750=y
CONFIG_AR71XX_MACH_TEW_632BRP=y
CONFIG_AR71XX_MACH_TL_WR1043ND=y
CONFIG_AR71XX_MACH_TL_WR741ND=y
CONFIG_AR71XX_MACH_TL_WR841N_V1=y
CONFIG_AR71XX_MACH_TL_WR941ND=y
CONFIG_AR71XX_MACH_UBNT=y
CONFIG_AR71XX_MACH_WNDR3700=y
CONFIG_AR71XX_MACH_WNR2000=y
CONFIG_AR71XX_MACH_WP543=y
CONFIG_AR71XX_MACH_WRT160NL=y
CONFIG_AR71XX_MACH_WRT400N=y
CONFIG_AR71XX_MACH_WZR_HP_G300NH=y
CONFIG_AR71XX_NVRAM=y
CONFIG_AR71XX_WDT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ATHEROS_AR71XX=y
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
CONFIG_BITREVERSE=y
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CEVT_R4K=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd console=ttyS0,115200"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_CAVIUM_OCTEON is not set
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2E is not set
# CONFIG_CPU_LOONGSON2F is not set
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR2=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CRYSTALHD is not set
CONFIG_CSRC_R4K=y
CONFIG_CSRC_R4K_LIB=y
# CONFIG_DEBUG_FS is not set
CONFIG_DECOMPRESS_LZMA=y
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_DT3155 is not set
CONFIG_EARLY_PRINTK=y
# CONFIG_FSNOTIFY is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GPIOLIB=y
# CONFIG_GPIO_IT8761E is not set
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_NXP_74HC153=y
CONFIG_GPIO_PCF857X=y
# CONFIG_GPIO_SCH is not set
CONFIG_GPIO_SYSFS=y
# CONFIG_HAMRADIO is not set
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HTC_I2CPLD is not set
CONFIG_HW_HAS_PCI=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_GPIO=y
# CONFIG_I2C_SMBUS is not set
# CONFIG_I2C_XILINX is not set
CONFIG_ICPLUS_PHY=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_IMAGE_CMDLINE_HACK=y
# CONFIG_INITRAMFS_COMPRESSION_LZO is not set
CONFIG_INITRAMFS_ROOT_GID=0
CONFIG_INITRAMFS_ROOT_UID=0
CONFIG_INITRAMFS_SOURCE="../../root"
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
CONFIG_IRQ_CPU=y
# CONFIG_KSZ884X_PCI is not set
# CONFIG_LEDS_GPIO is not set
# CONFIG_LEDS_RB750 is not set
# CONFIG_LEDS_WNDR3700_USB is not set
CONFIG_LLC=m
# CONFIG_LOGFS is not set
CONFIG_LOONGSON_UART_BASE=y
# CONFIG_LPC_SCH is not set
# CONFIG_M25PXX_USE_FAST_READ is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_LOONGSON is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_TIMBERDALE is not set
# CONFIG_MFD_WM8994 is not set
CONFIG_MICREL_PHY=y
# CONFIG_MIKROTIK_RB532 is not set
CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_MACHINE=y
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MTD_AR91XX_FLASH=y
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_MYLOADER_PARTS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_RB4XX=y
CONFIG_MTD_NAND_RB750=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_WRT160NL_PARTS=y
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
CONFIG_MYLOADER=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_AR7240=y
CONFIG_NET_DSA_MV88E6060=y
CONFIG_NET_DSA_MV88E6063=y
# CONFIG_NET_DSA_MV88E6123_61_65 is not set
# CONFIG_NET_DSA_MV88E6131 is not set
# CONFIG_NET_DSA_MV88E6XXX is not set
# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
# CONFIG_NET_DSA_TAG_DSA is not set
# CONFIG_NET_DSA_TAG_EDSA is not set
CONFIG_NET_DSA_TAG_QINQ=y
CONFIG_NET_DSA_TAG_TRAILER=y
CONFIG_NO_HZ=y
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PHYLIB=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_POWERTV is not set
CONFIG_RTL8306_PHY=y
CONFIG_RTL8366RB_PHY=y
CONFIG_RTL8366S_PHY=y
CONFIG_RTL8366_SMI=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_EXTENDED is not set
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SPI=y
CONFIG_SPI_AP83=y
CONFIG_SPI_AR71XX=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_PB44=y
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_VSC7385 is not set
CONFIG_STP=m
# CONFIG_SWAP is not set
CONFIG_SWCONFIG=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
# CONFIG_TC35815 is not set
CONFIG_TRAD_SIGNALS=y
# CONFIG_TREE_PREEMPT_RCU is not set
CONFIG_USB_SUPPORT=y
CONFIG_VLAN_8021Q=m
CONFIG_YAFFS_9BYTE_TAGS=y
CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
CONFIG_YAFFS_AUTO_YAFFS2=y
# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
CONFIG_YAFFS_FS=y
CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
CONFIG_YAFFS_YAFFS1=y
CONFIG_YAFFS_YAFFS2=y
CONFIG_ZONE_DMA_FLAG=0

View File

@ -1,50 +0,0 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -166,6 +166,13 @@ ifeq (,$(findstring march=octeon, $(cfla
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
endif
+#
+# Atheros AR71xx
+#
+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/
+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx
+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000
+
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -48,6 +48,23 @@ config AR7
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
+config ATHEROS_AR71XX
+ bool "Atheros AR71xx based boards"
+ select CEVT_R4K
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select IRQ_CPU
+ select ARCH_REQUIRE_GPIOLIB
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_EARLY_PRINTK
+ select MIPS_MACHINE
+ help
+ Support for Atheros AR71xx based boards.
+
config BCM47XX
bool "BCM47XX based boards"
select CEVT_R4K
@@ -682,6 +699,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
endchoice
source "arch/mips/alchemy/Kconfig"
+source "arch/mips/ar71xx/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"

View File

@ -1,10 +0,0 @@
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
ops-bcm63xx.o
+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o
#
# These are still pretty much in the old state, watch, go blind.

View File

@ -1,58 +0,0 @@
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -109,6 +109,13 @@ config XPS_USB_HCD_XILINX
support both high speed and full speed devices, or high speed
devices only.
+config USB_EHCI_AR71XX
+ bool "USB EHCI support for AR71xx"
+ depends on USB_EHCI_HCD && ATHEROS_AR71XX
+ default y
+ help
+ Support for Atheros AR71xx built-in EHCI controller
+
config USB_EHCI_FSL
bool "Support for Freescale on-chip EHCI USB controller"
depends on USB_EHCI_HCD && FSL_SOC
@@ -207,6 +214,13 @@ config USB_OHCI_HCD
To compile this driver as a module, choose M here: the
module will be called ohci-hcd.
+config USB_OHCI_AR71XX
+ bool "USB OHCI support for Atheros AR71xx"
+ depends on USB_OHCI_HCD && ATHEROS_AR71XX
+ default y
+ help
+ Support for Atheros AR71xx built-in OHCI controller
+
config USB_OHCI_HCD_PPC_SOC
bool "OHCI support for on-chip PPC USB controller"
depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx)
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1158,6 +1158,11 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ehci_atmel_driver
#endif
+#ifdef CONFIG_USB_EHCI_AR71XX
+#include "ehci-ar71xx.c"
+#define PLATFORM_DRIVER ehci_ar71xx_driver
+#endif
+
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
#error "missing bus glue for ehci-hcd"
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1085,6 +1085,11 @@ MODULE_LICENSE ("GPL");
#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
#endif
+#ifdef CONFIG_USB_OHCI_AR71XX
+#include "ohci-ar71xx.c"
+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver
+#endif
+
#if !defined(PCI_DRIVER) && \
!defined(PLATFORM_DRIVER) && \
!defined(OF_PLATFORM_DRIVER) && \

View File

@ -1,26 +0,0 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -53,6 +53,13 @@ if SPI_MASTER
comment "SPI Master Controller Drivers"
+config SPI_AR71XX
+ tristate "Atheros AR71xx SPI Controller"
+ depends on SPI_MASTER && ATHEROS_AR71XX
+ select SPI_BITBANG
+ help
+ This is the SPI contoller driver for Atheros AR71xx.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on (ARCH_AT91 || AVR32)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ endif
obj-$(CONFIG_SPI_MASTER) += spi.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o
obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o

View File

@ -1,21 +0,0 @@
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2128,6 +2128,8 @@ config ACENIC_OMIT_TIGON_I
The safe and default value for this is N.
+source drivers/net/ag71xx/Kconfig
+
config DL2K
tristate "DL2000/TC902x-based Gigabit Ethernet support"
depends on PCI
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac/
# end link order section
#
+obj-$(CONFIG_AG71XX) += ag71xx/
obj-$(CONFIG_SUNDANCE) += sundance.o
obj-$(CONFIG_HAMACHI) += hamachi.o
obj-$(CONFIG_NET) += Space.o loopback.o

View File

@ -1,26 +0,0 @@
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -840,6 +840,13 @@ config TXX9_WDT
help
Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
+config AR71XX_WDT
+ tristate "Atheros AR71xx Watchdog Timer"
+ depends on ATHEROS_AR71XX
+ help
+ Hardware driver for the built-in watchdog timer on the Atheros
+ AR71xx SoCs.
+
# PARISC Architecture
# POWERPC Architecture
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o
# PARISC Architecture

View File

@ -1,26 +0,0 @@
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -257,6 +257,13 @@ config MTD_ALCHEMY
help
Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
+config MTD_AR91XX_FLASH
+ tristate "Atheros AR91xx parallel flash support"
+ depends on ATHEROS_AR71XX
+ select MTD_COMPLEX_MAPPINGS
+ help
+ Parallel flash driver for the Atheros AR91xx based boards.
+
config MTD_DILNETPC
tristate "CFI Flash device mapped on DIL/Net PC"
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.
obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
obj-$(CONFIG_MTD_PCI) += pci.o
obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o
obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
obj-$(CONFIG_MTD_EDB7312) += edb7312.o
obj-$(CONFIG_MTD_IMPA7) += impa7.o

View File

@ -1,24 +0,0 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -114,6 +114,11 @@ config RTL8306_PHY
tristate "Driver for Realtek RTL8306S switches"
select SWCONFIG
+config MICREL_PHY
+ tristate "Drivers for Micrel/Kendin PHYs"
+ ---help---
+ Currently has a driver for the KSZ8041
+
config FIXED_PHY
bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
depends on PHYLIB=y
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi
obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o
obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o
obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
+obj-$(CONFIG_MICREL) += micrel.o
obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o

View File

@ -1,19 +0,0 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -922,6 +922,16 @@ static int __devinit m25p_probe(struct s
part_probes, &parts, 0);
}
+#ifdef CONFIG_MTD_MYLOADER_PARTS
+ if (nr_parts <= 0) {
+ static const char *part_probes[]
+ = { "MyLoader", NULL, };
+
+ nr_parts = parse_mtd_partitions(&flash->mtd,
+ part_probes, &parts, 0);
+ }
+#endif
+
if (nr_parts <= 0 && data && data->parts) {
parts = data->parts;
nr_parts = data->nr_parts;

View File

@ -1,18 +0,0 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -932,6 +932,15 @@ static int __devinit m25p_probe(struct s
}
#endif
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+ if (nr_parts <= 0) {
+ static const char *part_probes[]
+ = { "RedBoot", NULL, };
+
+ nr_parts = parse_mtd_partitions(&flash->mtd,
+ part_probes, &parts, 0);
+ }
+#endif
if (nr_parts <= 0 && data && data->parts) {
parts = data->parts;
nr_parts = data->nr_parts;

View File

@ -1,29 +0,0 @@
--- a/drivers/mtd/chips/jedec_probe.c
+++ b/drivers/mtd/chips/jedec_probe.c
@@ -166,6 +166,7 @@
#define SST39LF160 0x2782
#define SST39VF1601 0x234b
#define SST39VF3201 0x235b
+#define SST39VF6401B 0x236d
#define SST39LF512 0x00D4
#define SST39LF010 0x00D5
#define SST39LF020 0x00D6
@@ -1556,6 +1557,18 @@ static const struct amd_flash_info jedec
ERASEINFO(0x10000,64),
}
}, {
+ .mfr_id = MANUFACTURER_SST,
+ .dev_id = SST39VF6401B,
+ .name = "SST 39VF6401B",
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_0xAAAA_0x5555,
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
+ .regions = {
+ ERASEINFO(0x10000,128)
+ }
+ }, {
.mfr_id = MANUFACTURER_ST,
.dev_id = M29F800AB,
.name = "ST M29F800AB",

View File

@ -1,69 +0,0 @@
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -1130,8 +1130,8 @@ static int __xipram do_write_oneword(str
break;
}
- if (chip_ready(map, adr))
- break;
+ if (chip_good(map, adr, datum))
+ goto enable_xip;
/* Latency issues. Drop the lock, wait a while and retry */
UDELAY(map, chip, adr, 1);
@@ -1147,6 +1147,8 @@ static int __xipram do_write_oneword(str
ret = -EIO;
}
+
+ enable_xip:
xip_enable(map, chip, adr);
op_done:
chip->state = FL_READY;
@@ -1493,7 +1495,6 @@ static int cfi_amdstd_write_buffers(stru
return 0;
}
-
/*
* Handle devices with one erase region, that only implement
* the chip erase command.
@@ -1557,8 +1558,8 @@ static int __xipram do_erase_chip(struct
chip->erase_suspended = 0;
}
- if (chip_ready(map, adr))
- break;
+ if (chip_good(map, adr, map_word_ff(map)))
+ goto op_done;
if (time_after(jiffies, timeo)) {
printk(KERN_WARNING "MTD %s(): software timeout\n",
@@ -1578,6 +1579,7 @@ static int __xipram do_erase_chip(struct
ret = -EIO;
}
+ op_done:
chip->state = FL_READY;
xip_enable(map, chip, adr);
put_chip(map, chip, adr);
@@ -1645,9 +1647,9 @@ static int __xipram do_erase_oneblock(st
chip->erase_suspended = 0;
}
- if (chip_ready(map, adr)) {
+ if (chip_good(map, adr, map_word_ff(map))) {
xip_enable(map, chip, adr);
- break;
+ goto op_done;
}
if (time_after(jiffies, timeo)) {
@@ -1669,6 +1671,7 @@ static int __xipram do_erase_oneblock(st
ret = -EIO;
}
+ op_done:
chip->state = FL_READY;
put_chip(map, chip, adr);
spin_unlock(chip->mutex);

View File

@ -1,44 +0,0 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -941,6 +941,16 @@ static int __devinit m25p_probe(struct s
part_probes, &parts, 0);
}
#endif
+
+#ifdef CONFIG_MTD_WRT160NL_PARTS
+ if (nr_parts <= 0) {
+ static const char *part_probes[]
+ = { "wrt160nl", NULL, };
+
+ nr_parts = parse_mtd_partitions(&flash->mtd,
+ part_probes, &parts, 0);
+ }
+#endif
if (nr_parts <= 0 && data && data->parts) {
parts = data->parts;
nr_parts = data->nr_parts;
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -181,6 +181,12 @@ config MTD_AR7_PARTS
---help---
TI AR7 partitioning support
+config MTD_WRT160NL_PARTS
+ tristate "Linksys WRT160NL partitioning support"
+ depends on MTD_PARTITIONS && AR71XX_MACH_WRT160NL
+ ---help---
+ Linksys WRT160NL partitioning support
+
config MTD_MYLOADER_PARTS
tristate "MyLoader partition parsing"
depends on MTD_PARTITIONS && (ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX)
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redbo
obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
+obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o

View File

@ -1,22 +0,0 @@
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -1194,6 +1194,9 @@ static void end_unlink_async (struct ehc
ehci->reclaim = NULL;
start_unlink_async (ehci, next);
}
+
+ if (ehci->has_synopsys_hc_bug)
+ writel((u32)ehci->async->qh_dma, &ehci->regs->async_next);
}
/* makes sure the async qh will become idle */
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -129,6 +129,7 @@ struct ehci_hcd { /* one per controlle
unsigned has_amcc_usb23:1;
unsigned need_io_watchdog:1;
unsigned broken_periodic:1;
+ unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
/* required for usb32 quirk */
#define OHCI_CTRL_HCFS (3 << 6)

View File

@ -1,61 +0,0 @@
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -39,7 +39,7 @@
#include <linux/mtd/xip.h>
#define AMD_BOOTLOC_BUG
-#define FORCE_WORD_WRITE 0
+#define FORCE_WORD_WRITE 1
#define MAX_WORD_RETRIES 3
@@ -55,7 +55,9 @@
static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+#if !FORCE_WORD_WRITE
static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+#endif
static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
static void cfi_amdstd_sync (struct mtd_info *);
@@ -190,6 +192,7 @@ static void fixup_amd_bootblock(struct m
}
#endif
+#if !FORCE_WORD_WRITE
static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
{
struct map_info *map = mtd->priv;
@@ -199,6 +202,7 @@ static void fixup_use_write_buffers(stru
mtd->write = cfi_amdstd_write_buffers;
}
}
+#endif /* !FORCE_WORD_WRITE */
/* Atmel chips don't use the same PRI format as AMD chips */
static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
@@ -1304,6 +1308,7 @@ static int cfi_amdstd_write_words(struct
/*
* FIXME: interleaved mode not tested, and probably not supported!
*/
+#if !FORCE_WORD_WRITE
static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
unsigned long adr, const u_char *buf,
int len)
@@ -1415,7 +1420,6 @@ static int __xipram do_write_buffer(stru
return ret;
}
-
static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
@@ -1494,6 +1498,7 @@ static int cfi_amdstd_write_buffers(stru
return 0;
}
+#endif /* !FORCE_WORD_WRITE */
/*
* Handle devices with one erase region, that only implement

View File

@ -1,11 +0,0 @@
--- a/net/dsa/tag_trailer.c
+++ b/net/dsa/tag_trailer.c
@@ -86,7 +86,7 @@ static int trailer_rcv(struct sk_buff *s
trailer = skb_tail_pointer(skb) - 4;
if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
+ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
goto out_drop;
source_port = trailer[1] & 7;

View File

@ -1,26 +0,0 @@
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -36,6 +36,13 @@ config NET_DSA_MV88E6060
This enables support for the Marvell 88E6060 ethernet switch
chip.
+config NET_DSA_MV88E6063
+ bool "Marvell 88E6063 ethernet switch chip support"
+ select NET_DSA_TAG_TRAILER
+ ---help---
+ This enables support for the Marvell 88E6063 ethernet switch
+ chip
+
config NET_DSA_MV88E6XXX_NEED_PPU
bool
default n
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag
# switch drivers
obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
obj-$(CONFIG_NET_DSA_MV88E6123_61_65) += mv88e6123_61_65.o
obj-$(CONFIG_NET_DSA_MV88E6131) += mv88e6131.o

View File

@ -1,79 +0,0 @@
--- a/include/linux/if_ether.h
+++ b/include/linux/if_ether.h
@@ -81,6 +81,7 @@
#define ETH_P_1588 0x88F7 /* IEEE 1588 Timesync */
#define ETH_P_FCOE 0x8906 /* Fibre Channel over Ethernet */
#define ETH_P_FIP 0x8914 /* FCoE Initialization Protocol */
+#define ETH_P_QINQ 0x9100 /* QinQ VLAN Stacking Protocol */
#define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
/*
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -174,6 +174,9 @@ netdev_tx_t dsa_xmit(struct sk_buff *skb
/* tag_edsa.c */
netdev_tx_t edsa_xmit(struct sk_buff *skb, struct net_device *dev);
+/* tag_qinq.c */
+netdev_tx_t qinq_xmit(struct sk_buff *skb, struct net_device *dev);
+
/* tag_trailer.c */
netdev_tx_t trailer_xmit(struct sk_buff *skb, struct net_device *dev);
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -23,6 +23,10 @@ config NET_DSA_TAG_TRAILER
bool
default n
+config NET_DSA_TAG_QINQ
+ bool
+ default y
+
# switch drivers
config NET_DSA_MV88E6XXX
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -1,6 +1,7 @@
# tagging formats
obj-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
obj-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
+obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qinq.o
obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o
# switch drivers
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -321,6 +321,19 @@ static const struct net_device_ops edsa_
.ndo_do_ioctl = dsa_slave_ioctl,
};
#endif
+#ifdef CONFIG_NET_DSA_TAG_QINQ
+static const struct net_device_ops qinq_netdev_ops = {
+ .ndo_init = dsa_slave_init,
+ .ndo_open = dsa_slave_open,
+ .ndo_stop = dsa_slave_close,
+ .ndo_start_xmit = qinq_xmit,
+ .ndo_change_rx_flags = dsa_slave_change_rx_flags,
+ .ndo_set_rx_mode = dsa_slave_set_rx_mode,
+ .ndo_set_multicast_list = dsa_slave_set_rx_mode,
+ .ndo_set_mac_address = dsa_slave_set_mac_address,
+ .ndo_do_ioctl = dsa_slave_ioctl,
+};
+#endif
#ifdef CONFIG_NET_DSA_TAG_TRAILER
static const struct net_device_ops trailer_netdev_ops = {
.ndo_init = dsa_slave_init,
@@ -366,6 +379,11 @@ dsa_slave_create(struct dsa_switch *ds,
slave_dev->netdev_ops = &edsa_netdev_ops;
break;
#endif
+#ifdef CONFIG_NET_DSA_TAG_QINQ
+ case htons(ETH_P_QINQ):
+ slave_dev->netdev_ops = &qinq_netdev_ops;
+ break;
+#endif
#ifdef CONFIG_NET_DSA_TAG_TRAILER
case htons(ETH_P_TRAILER):
slave_dev->netdev_ops = &trailer_netdev_ops;

View File

@ -1,28 +0,0 @@
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -29,6 +29,15 @@ config NET_DSA_TAG_QINQ
# switch drivers
+config NET_DSA_AR7240
+ bool "Atheros AR7240 built-in ethernet switch support"
+ depends on ATHEROS_AR71XX
+ default n
+ select NET_DSA_TAG_QINQ
+ ---help---
+ This enables support for the built-in ethernet switch of the
+ Atheros AR7240 SoC.
+
config NET_DSA_MV88E6XXX
bool
default n
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qi
obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o
# switch drivers
+obj-$(CONFIG_NET_DSA_AR7240) += ar7240.o
obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o

View File

@ -1,54 +0,0 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -60,31 +60,32 @@ static int parse_redboot_partitions(stru
static char nullstring[] = "unallocated";
#endif
+ buf = vmalloc(master->erasesize);
+ if (!buf)
+ return -ENOMEM;
+
+ restart:
if ( directory < 0 ) {
offset = master->size + directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
if (!offset) {
nogood:
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
+ vfree(buf);
return -EIO;
}
offset -= master->erasesize;
}
} else {
offset = directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
offset += master->erasesize;
if (offset == master->size)
goto nogood;
}
}
- buf = vmalloc(master->erasesize);
-
- if (!buf)
- return -ENOMEM;
-
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
master->name, offset);
@@ -156,6 +157,11 @@ static int parse_redboot_partitions(stru
}
if (i == numslots) {
/* Didn't find it */
+ if (offset + master->erasesize < master->size) {
+ /* not at the end of the flash yet, maybe next block :) */
+ directory++;
+ goto restart;
+ }
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
master->name);
ret = 0;

View File

@ -1,21 +0,0 @@
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -488,4 +488,8 @@ config MTD_NAND_W90P910
This enables the driver for the NAND Flash on evaluation board based
on w90p910.
+config MTD_NAND_RB4XX
+ tristate "NAND flash driver for RouterBoard 4xx series"
+ depends on MTD_NAND && AR71XX_MACH_RB4XX
+
endif # MTD_NAND
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o

View File

@ -1,27 +0,0 @@
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ endif
obj-$(CONFIG_SPI_MASTER) += spi.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AP83) += ap83_spi.o
obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o
obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -53,6 +53,14 @@ if SPI_MASTER
comment "SPI Master Controller Drivers"
+config SPI_AP83
+ tristate "Atheros AP83 specific SPI Controller"
+ depends on SPI_MASTER && AR71XX_MACH_AP83
+ select SPI_BITBANG
+ help
+ This is a specific SPI controller driver for the Atheros AP83
+ reference board.
+
config SPI_AR71XX
tristate "Atheros AR71xx SPI Controller"
depends on SPI_MASTER && ATHEROS_AR71XX

View File

@ -1,24 +0,0 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -365,6 +365,11 @@ config SPI_TLE62X0
sysfs interface, with each line presented as a kind of GPIO
exposing both switch control and diagnostic feedback.
+config SPI_VSC7385
+ tristate "Vitesse VSC7385 ethernet switch driver"
+ help
+ SPI driver for the Vitesse VSC7385 ethernet switch.
+
#
# Add new SPI protocol masters in alphabetical order above this line
#
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -54,6 +54,7 @@ spi_s3c24xx_hw-$(CONFIG_SPI_S3C24XX_FIQ)
# SPI protocol drivers (device/link on bus)
obj-$(CONFIG_SPI_SPIDEV) += spidev.o
+obj-$(CONFIG_SPI_VSC7385) += spi_vsc7385.o
obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o
# ... add above this line ...

View File

@ -1,27 +0,0 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -68,6 +68,14 @@ config SPI_AR71XX
help
This is the SPI contoller driver for Atheros AR71xx.
+config SPI_PB44
+ tristate "Atheros PB44 board specific SPI controller"
+ depends on SPI_MASTER && AR71XX_MACH_PB44
+ select SPI_BITBANG
+ help
+ This is a specific SPI controller driver for the Atheros PB44
+ reference board.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on (ARCH_AT91 || AVR32)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o
obj-$(CONFIG_SPI_IMX) += spi_imx.o
obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
+obj-$(CONFIG_SPI_PB44) += pb44_spi.o
obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o

View File

@ -1,26 +0,0 @@
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -269,6 +269,13 @@ config LEDS_ADP5520
To compile this driver as a module, choose M here: the module will
be called leds-adp5520.
+config LEDS_WNDR3700_USB
+ tristate "NETGEAR WNDR3700 USB LED driver"
+ depends on LEDS_CLASS && AR71XX_MACH_WNDR3700
+ help
+ This option enables support for the USB LED found on the
+ NETGEAR WNDR3700 board.
+
comment "LED Triggers"
config LEDS_TRIGGERS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903
obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
+obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o
obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o

View File

@ -1,25 +0,0 @@
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -255,4 +255,12 @@ config GPIO_UCB1400
To compile this driver as a module, choose M here: the
module will be called ucb1400_gpio.
+comment "Other GPIO expanders"
+
+config GPIO_NXP_74HC153
+ tristate "NXP 74HC153 Dual 4-input multiplexer"
+ help
+ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
+ provides a GPIO interface supporting inputs.
+
endif
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o
obj-$(CONFIG_GPIO_MAX732X) += max732x.o
obj-$(CONFIG_GPIO_MC33880) += mc33880.o
obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o
+obj-$(CONFIG_GPIO_NXP_74HC153) += nxp_74hc153.o
obj-$(CONFIG_GPIO_PCA953X) += pca953x.o
obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
obj-$(CONFIG_GPIO_PL061) += pl061.o

View File

@ -1,23 +0,0 @@
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -276,6 +276,10 @@ config LEDS_WNDR3700_USB
This option enables support for the USB LED found on the
NETGEAR WNDR3700 board.
+config LEDS_RB750
+ tristate "LED driver for the Mikrotik RouterBOARD 750"
+ depends on LEDS_CLASS && AR71XX_MACH_RB750
+
comment "LED Triggers"
config LEDS_TRIGGERS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_LEDS_REGULATOR) += leds-re
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o
+obj-$(CONFIG_LEDS_RB750) += leds-rb750.o
# LED SPI Drivers
obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o

View File

@ -1,21 +0,0 @@
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -492,4 +492,8 @@ config MTD_NAND_RB4XX
tristate "NAND flash driver for RouterBoard 4xx series"
depends on MTD_NAND && AR71XX_MACH_RB4XX
+config MTD_NAND_RB750
+ tristate "NAND flash driver for the RouterBoard 750"
+ depends on MTD_NAND && AR71XX_MACH_RB750
+
endif # MTD_NAND
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o

View File

@ -1,22 +0,0 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -190,6 +190,7 @@ endif
#
libs-$(CONFIG_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
libs-y += arch/mips/fw/lib/
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -877,6 +877,9 @@ config MIPS_NILE4
config MIPS_DISABLE_OBSOLETE_IDE
bool
+config MYLOADER
+ bool
+
config SYNC_R4K
bool

View File

@ -1,134 +0,0 @@
--- a/arch/mips/kernel/mips_machine.c
+++ b/arch/mips/kernel/mips_machine.c
@@ -7,12 +7,13 @@
*
*/
#include <linux/mm.h>
+#include <linux/string.h>
#include <asm/mips_machine.h>
-#include <asm/bootinfo.h>
static struct list_head mips_machines __initdata =
LIST_HEAD_INIT(mips_machines);
+static char *mips_machid __initdata;
char *mips_machine_name = "Unknown";
@@ -55,20 +56,65 @@ void __init mips_machine_set_name(char *
}
}
-void __init mips_machine_setup(unsigned long machtype)
+void __init mips_machine_setup(void)
{
struct mips_machine *mach;
- mach = mips_machine_find(machtype);
+ mach = mips_machine_find(mips_machtype);
if (!mach) {
- printk(KERN_ALERT "MIPS: no machine registered for "
- "machtype %lu\n", machtype);
+ printk(KERN_WARNING "MIPS: no machine registered for "
+ "machtype %lu\n", mips_machtype);
return;
}
mips_machine_set_name(mach->mach_name);
- printk(KERN_INFO "MIPS: machine is %s\n", mips_machine_name);
+ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name);
if (mach->mach_setup)
mach->mach_setup();
}
+
+int __init mips_machtype_setup(char *id)
+{
+ if (mips_machid == NULL)
+ mips_machid = id;
+
+ return 1;
+}
+
+__setup("machtype=", mips_machtype_setup);
+
+static int __init mips_machtype_init(void)
+{
+ struct list_head *this;
+ struct mips_machine *mach;
+
+ if (mips_machid == NULL)
+ return 0;
+
+ list_for_each(this, &mips_machines) {
+ mach = list_entry(this, struct mips_machine, list);
+ if (mach->mach_id == NULL)
+ continue;
+
+ if (strcmp(mach->mach_id, mips_machid) == 0) {
+ mips_machtype = mach->mach_type;
+ return 0;
+ }
+ }
+
+ printk(KERN_WARNING
+ "MIPS: no machine found for id: '%s', registered machines:\n",
+ mips_machid);
+ printk(KERN_WARNING "%32s %s\n", "id", "name");
+
+ list_for_each(this, &mips_machines) {
+ mach = list_entry(this, struct mips_machine, list);
+ printk(KERN_WARNING "%32s %s\n",
+ mach->mach_id ? mach->mach_id : "", mach->mach_name);
+ }
+
+ return 0;
+}
+
+core_initcall(mips_machtype_init);
--- a/arch/mips/include/asm/mips_machine.h
+++ b/arch/mips/include/asm/mips_machine.h
@@ -13,25 +13,33 @@
#include <linux/init.h>
#include <linux/list.h>
+#include <asm/bootinfo.h>
+
struct mips_machine {
unsigned long mach_type;
- void (*mach_setup)(void);
+ char *mach_id;
char *mach_name;
+ void (*mach_setup)(void);
struct list_head list;
};
void mips_machine_register(struct mips_machine *) __init;
-void mips_machine_setup(unsigned long machtype) __init;
+void mips_machine_setup(void) __init;
+int mips_machtype_setup(char *id) __init;
void mips_machine_set_name(char *name) __init;
extern char *mips_machine_name;
-#define MIPS_MACHINE(_type, _name, _setup) \
-static char machine_name_##_type[] __initdata = _name; \
+#define MIPS_MACHINE(_type, _id, _name, _setup) \
+static const char machine_name_##_type[] __initconst \
+ __aligned(1) = _name; \
+static const char machine_id_##_type[] __initconst \
+ __aligned(1) = _id; \
static struct mips_machine machine_##_type __initdata = \
{ \
.mach_type = _type, \
- .mach_name = machine_name_##_type, \
+ .mach_id = (char *) machine_id_##_type, \
+ .mach_name = (char *) machine_name_##_type, \
.mach_setup = _setup, \
}; \
\
@@ -44,4 +52,3 @@ static int __init register_machine_##_ty
pure_initcall(register_machine_##_type)
#endif /* __ASM_MIPS_MACHINE_H */
-

View File

@ -1,29 +0,0 @@
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -50,6 +50,7 @@
#include <asm/types.h>
#include <asm/stacktrace.h>
#include <asm/irq.h>
+#include <asm/time.h>
extern void check_wait(void);
extern asmlinkage void r4k_wait(void);
@@ -1496,6 +1497,8 @@ void __cpuinit per_cpu_trap_init(void)
if (cpu_has_mips_r2) {
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
+ if (get_c0_compare_irq)
+ cp0_compare_irq = get_c0_compare_irq();
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -52,6 +52,7 @@ extern int (*perf_irq)(void);
*/
#ifdef CONFIG_CEVT_R4K_LIB
extern unsigned int __weak get_c0_compare_int(void);
+extern unsigned int __weak get_c0_compare_irq(void);
extern int r4k_clockevent_init(void);
#endif

View File

@ -1,56 +0,0 @@
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -16,6 +16,22 @@
#include <asm/cevt-r4k.h>
/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register. 4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+ do { \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ } while (0)
+
+/*
* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
* of these routines with SMTC-specific variants.
*/
@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
+ compare_change_hazard();
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
return res;
}
@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
}
-/*
- * Compare interrupt can be routed and latched outside the core,
- * so a single execution hazard barrier may not be enough to give
- * it time to clear as seen in the Cause register. 4 time the
- * pipeline depth seems reasonably conservative, and empirically
- * works better in configurations with high CPU/bus clock ratios.
- */
-
-#define compare_change_hazard() \
- do { \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- } while (0)
-
int c0_compare_int_usable(void)
{
unsigned int delta;

View File

@ -1,50 +0,0 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -166,6 +166,13 @@ ifeq (,$(findstring march=octeon, $(cfla
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
endif
+#
+# Atheros AR71xx
+#
+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/
+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx
+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000
+
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -48,6 +48,23 @@ config AR7
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
+config ATHEROS_AR71XX
+ bool "Atheros AR71xx based boards"
+ select CEVT_R4K
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select IRQ_CPU
+ select ARCH_REQUIRE_GPIOLIB
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_EARLY_PRINTK
+ select MIPS_MACHINE
+ help
+ Support for Atheros AR71xx based boards.
+
config BCM47XX
bool "BCM47XX based boards"
select CEVT_R4K
@@ -682,6 +699,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
endchoice
source "arch/mips/alchemy/Kconfig"
+source "arch/mips/ar71xx/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"

View File

@ -1,10 +0,0 @@
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
ops-bcm63xx.o
+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o
#
# These are still pretty much in the old state, watch, go blind.

View File

@ -1,58 +0,0 @@
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -109,6 +109,13 @@ config XPS_USB_HCD_XILINX
support both high speed and full speed devices, or high speed
devices only.
+config USB_EHCI_AR71XX
+ bool "USB EHCI support for AR71xx"
+ depends on USB_EHCI_HCD && ATHEROS_AR71XX
+ default y
+ help
+ Support for Atheros AR71xx built-in EHCI controller
+
config USB_EHCI_FSL
bool "Support for Freescale on-chip EHCI USB controller"
depends on USB_EHCI_HCD && FSL_SOC
@@ -207,6 +214,13 @@ config USB_OHCI_HCD
To compile this driver as a module, choose M here: the
module will be called ohci-hcd.
+config USB_OHCI_AR71XX
+ bool "USB OHCI support for Atheros AR71xx"
+ depends on USB_OHCI_HCD && ATHEROS_AR71XX
+ default y
+ help
+ Support for Atheros AR71xx built-in OHCI controller
+
config USB_OHCI_HCD_PPC_SOC
bool "OHCI support for on-chip PPC USB controller"
depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx)
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1158,6 +1158,11 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ehci_atmel_driver
#endif
+#ifdef CONFIG_USB_EHCI_AR71XX
+#include "ehci-ar71xx.c"
+#define PLATFORM_DRIVER ehci_ar71xx_driver
+#endif
+
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
#error "missing bus glue for ehci-hcd"
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1085,6 +1085,11 @@ MODULE_LICENSE ("GPL");
#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
#endif
+#ifdef CONFIG_USB_OHCI_AR71XX
+#include "ohci-ar71xx.c"
+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver
+#endif
+
#if !defined(PCI_DRIVER) && \
!defined(PLATFORM_DRIVER) && \
!defined(OF_PLATFORM_DRIVER) && \

View File

@ -1,26 +0,0 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -53,6 +53,13 @@ if SPI_MASTER
comment "SPI Master Controller Drivers"
+config SPI_AR71XX
+ tristate "Atheros AR71xx SPI Controller"
+ depends on SPI_MASTER && ATHEROS_AR71XX
+ select SPI_BITBANG
+ help
+ This is the SPI contoller driver for Atheros AR71xx.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on (ARCH_AT91 || AVR32)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ endif
obj-$(CONFIG_SPI_MASTER) += spi.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o
obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o

View File

@ -1,21 +0,0 @@
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2128,6 +2128,8 @@ config ACENIC_OMIT_TIGON_I
The safe and default value for this is N.
+source drivers/net/ag71xx/Kconfig
+
config DL2K
tristate "DL2000/TC902x-based Gigabit Ethernet support"
depends on PCI
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac/
# end link order section
#
+obj-$(CONFIG_AG71XX) += ag71xx/
obj-$(CONFIG_SUNDANCE) += sundance.o
obj-$(CONFIG_HAMACHI) += hamachi.o
obj-$(CONFIG_NET) += Space.o loopback.o

View File

@ -1,26 +0,0 @@
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -840,6 +840,13 @@ config TXX9_WDT
help
Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
+config AR71XX_WDT
+ tristate "Atheros AR71xx Watchdog Timer"
+ depends on ATHEROS_AR71XX
+ help
+ Hardware driver for the built-in watchdog timer on the Atheros
+ AR71xx SoCs.
+
# PARISC Architecture
# POWERPC Architecture
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o
# PARISC Architecture

View File

@ -1,26 +0,0 @@
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -257,6 +257,13 @@ config MTD_ALCHEMY
help
Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
+config MTD_AR91XX_FLASH
+ tristate "Atheros AR91xx parallel flash support"
+ depends on ATHEROS_AR71XX
+ select MTD_COMPLEX_MAPPINGS
+ help
+ Parallel flash driver for the Atheros AR91xx based boards.
+
config MTD_DILNETPC
tristate "CFI Flash device mapped on DIL/Net PC"
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -40,6 +40,7 @@
obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o
obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
obj-$(CONFIG_MTD_PCI) += pci.o
+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o
obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
obj-$(CONFIG_MTD_EDB7312) += edb7312.o
obj-$(CONFIG_MTD_IMPA7) += impa7.o

View File

@ -1,24 +0,0 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -114,6 +114,11 @@ config RTL8306_PHY
tristate "Driver for Realtek RTL8306S switches"
select SWCONFIG
+config MICREL_PHY
+ tristate "Drivers for Micrel/Kendin PHYs"
+ ---help---
+ Currently has a driver for the KSZ8041
+
config FIXED_PHY
bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
depends on PHYLIB=y
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi
obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o
obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o
obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
+obj-$(CONFIG_MICREL) += micrel.o
obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o

View File

@ -1,19 +0,0 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -922,6 +922,16 @@ static int __devinit m25p_probe(struct s
part_probes, &parts, 0);
}
+#ifdef CONFIG_MTD_MYLOADER_PARTS
+ if (nr_parts <= 0) {
+ static const char *part_probes[]
+ = { "MyLoader", NULL, };
+
+ nr_parts = parse_mtd_partitions(&flash->mtd,
+ part_probes, &parts, 0);
+ }
+#endif
+
if (nr_parts <= 0 && data && data->parts) {
parts = data->parts;
nr_parts = data->nr_parts;

View File

@ -1,18 +0,0 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -932,6 +932,15 @@ static int __devinit m25p_probe(struct s
}
#endif
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+ if (nr_parts <= 0) {
+ static const char *part_probes[]
+ = { "RedBoot", NULL, };
+
+ nr_parts = parse_mtd_partitions(&flash->mtd,
+ part_probes, &parts, 0);
+ }
+#endif
if (nr_parts <= 0 && data && data->parts) {
parts = data->parts;
nr_parts = data->nr_parts;

View File

@ -1,29 +0,0 @@
--- a/drivers/mtd/chips/jedec_probe.c
+++ b/drivers/mtd/chips/jedec_probe.c
@@ -166,6 +166,7 @@
#define SST39LF160 0x2782
#define SST39VF1601 0x234b
#define SST39VF3201 0x235b
+#define SST39VF6401B 0x236d
#define SST39LF512 0x00D4
#define SST39LF010 0x00D5
#define SST39LF020 0x00D6
@@ -1556,6 +1557,18 @@ static const struct amd_flash_info jedec
ERASEINFO(0x10000,64),
}
}, {
+ .mfr_id = MANUFACTURER_SST,
+ .dev_id = SST39VF6401B,
+ .name = "SST 39VF6401B",
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_0xAAAA_0x5555,
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
+ .regions = {
+ ERASEINFO(0x10000,128)
+ }
+ }, {
.mfr_id = MANUFACTURER_ST,
.dev_id = M29F800AB,
.name = "ST M29F800AB",

View File

@ -1,69 +0,0 @@
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -1130,8 +1130,8 @@ static int __xipram do_write_oneword(str
break;
}
- if (chip_ready(map, adr))
- break;
+ if (chip_good(map, adr, datum))
+ goto enable_xip;
/* Latency issues. Drop the lock, wait a while and retry */
UDELAY(map, chip, adr, 1);
@@ -1147,6 +1147,8 @@ static int __xipram do_write_oneword(str
ret = -EIO;
}
+
+ enable_xip:
xip_enable(map, chip, adr);
op_done:
chip->state = FL_READY;
@@ -1493,7 +1495,6 @@ static int cfi_amdstd_write_buffers(stru
return 0;
}
-
/*
* Handle devices with one erase region, that only implement
* the chip erase command.
@@ -1557,8 +1558,8 @@ static int __xipram do_erase_chip(struct
chip->erase_suspended = 0;
}
- if (chip_ready(map, adr))
- break;
+ if (chip_good(map, adr, map_word_ff(map)))
+ goto op_done;
if (time_after(jiffies, timeo)) {
printk(KERN_WARNING "MTD %s(): software timeout\n",
@@ -1578,6 +1579,7 @@ static int __xipram do_erase_chip(struct
ret = -EIO;
}
+ op_done:
chip->state = FL_READY;
xip_enable(map, chip, adr);
put_chip(map, chip, adr);
@@ -1645,9 +1647,9 @@ static int __xipram do_erase_oneblock(st
chip->erase_suspended = 0;
}
- if (chip_ready(map, adr)) {
+ if (chip_good(map, adr, map_word_ff(map))) {
xip_enable(map, chip, adr);
- break;
+ goto op_done;
}
if (time_after(jiffies, timeo)) {
@@ -1669,6 +1671,7 @@ static int __xipram do_erase_oneblock(st
ret = -EIO;
}
+ op_done:
chip->state = FL_READY;
put_chip(map, chip, adr);
spin_unlock(chip->mutex);

View File

@ -1,44 +0,0 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -941,6 +941,16 @@ static int __devinit m25p_probe(struct s
part_probes, &parts, 0);
}
#endif
+
+#ifdef CONFIG_MTD_WRT160NL_PARTS
+ if (nr_parts <= 0) {
+ static const char *part_probes[]
+ = { "wrt160nl", NULL, };
+
+ nr_parts = parse_mtd_partitions(&flash->mtd,
+ part_probes, &parts, 0);
+ }
+#endif
if (nr_parts <= 0 && data && data->parts) {
parts = data->parts;
nr_parts = data->nr_parts;
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -181,6 +181,12 @@ config MTD_AR7_PARTS
---help---
TI AR7 partitioning support
+config MTD_WRT160NL_PARTS
+ tristate "Linksys WRT160NL partitioning support"
+ depends on MTD_PARTITIONS && AR71XX_MACH_WRT160NL
+ ---help---
+ Linksys WRT160NL partitioning support
+
config MTD_MYLOADER_PARTS
tristate "MyLoader partition parsing"
depends on MTD_PARTITIONS && (ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX)
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redbo
obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
+obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o

View File

@ -1,22 +0,0 @@
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -1194,6 +1194,9 @@ static void end_unlink_async (struct ehc
ehci->reclaim = NULL;
start_unlink_async (ehci, next);
}
+
+ if (ehci->has_synopsys_hc_bug)
+ writel((u32)ehci->async->qh_dma, &ehci->regs->async_next);
}
/* makes sure the async qh will become idle */
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -129,6 +129,7 @@ struct ehci_hcd { /* one per controlle
unsigned has_amcc_usb23:1;
unsigned need_io_watchdog:1;
unsigned broken_periodic:1;
+ unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
/* required for usb32 quirk */
#define OHCI_CTRL_HCFS (3 << 6)

View File

@ -1,61 +0,0 @@
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -39,7 +39,7 @@
#include <linux/mtd/xip.h>
#define AMD_BOOTLOC_BUG
-#define FORCE_WORD_WRITE 0
+#define FORCE_WORD_WRITE 1
#define MAX_WORD_RETRIES 3
@@ -55,7 +55,9 @@
static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+#if !FORCE_WORD_WRITE
static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+#endif
static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
static void cfi_amdstd_sync (struct mtd_info *);
@@ -190,6 +192,7 @@ static void fixup_amd_bootblock(struct m
}
#endif
+#if !FORCE_WORD_WRITE
static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
{
struct map_info *map = mtd->priv;
@@ -199,6 +202,7 @@ static void fixup_use_write_buffers(stru
mtd->write = cfi_amdstd_write_buffers;
}
}
+#endif /* !FORCE_WORD_WRITE */
/* Atmel chips don't use the same PRI format as AMD chips */
static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
@@ -1304,6 +1308,7 @@ static int cfi_amdstd_write_words(struct
/*
* FIXME: interleaved mode not tested, and probably not supported!
*/
+#if !FORCE_WORD_WRITE
static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
unsigned long adr, const u_char *buf,
int len)
@@ -1415,7 +1420,6 @@ static int __xipram do_write_buffer(stru
return ret;
}
-
static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
@@ -1494,6 +1498,7 @@ static int cfi_amdstd_write_buffers(stru
return 0;
}
+#endif /* !FORCE_WORD_WRITE */
/*
* Handle devices with one erase region, that only implement

View File

@ -1,11 +0,0 @@
--- a/net/dsa/tag_trailer.c
+++ b/net/dsa/tag_trailer.c
@@ -86,7 +86,7 @@ static int trailer_rcv(struct sk_buff *s
trailer = skb_tail_pointer(skb) - 4;
if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
+ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
goto out_drop;
source_port = trailer[1] & 7;

View File

@ -1,26 +0,0 @@
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -36,6 +36,13 @@ config NET_DSA_MV88E6060
This enables support for the Marvell 88E6060 ethernet switch
chip.
+config NET_DSA_MV88E6063
+ bool "Marvell 88E6063 ethernet switch chip support"
+ select NET_DSA_TAG_TRAILER
+ ---help---
+ This enables support for the Marvell 88E6063 ethernet switch
+ chip
+
config NET_DSA_MV88E6XXX_NEED_PPU
bool
default n
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag
# switch drivers
obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
+obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
obj-$(CONFIG_NET_DSA_MV88E6123_61_65) += mv88e6123_61_65.o
obj-$(CONFIG_NET_DSA_MV88E6131) += mv88e6131.o

View File

@ -1,79 +0,0 @@
--- a/include/linux/if_ether.h
+++ b/include/linux/if_ether.h
@@ -81,6 +81,7 @@
#define ETH_P_1588 0x88F7 /* IEEE 1588 Timesync */
#define ETH_P_FCOE 0x8906 /* Fibre Channel over Ethernet */
#define ETH_P_FIP 0x8914 /* FCoE Initialization Protocol */
+#define ETH_P_QINQ 0x9100 /* QinQ VLAN Stacking Protocol */
#define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
/*
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -174,6 +174,9 @@ netdev_tx_t dsa_xmit(struct sk_buff *skb
/* tag_edsa.c */
netdev_tx_t edsa_xmit(struct sk_buff *skb, struct net_device *dev);
+/* tag_qinq.c */
+netdev_tx_t qinq_xmit(struct sk_buff *skb, struct net_device *dev);
+
/* tag_trailer.c */
netdev_tx_t trailer_xmit(struct sk_buff *skb, struct net_device *dev);
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -23,6 +23,10 @@ config NET_DSA_TAG_TRAILER
bool
default n
+config NET_DSA_TAG_QINQ
+ bool
+ default y
+
# switch drivers
config NET_DSA_MV88E6XXX
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -1,6 +1,7 @@
# tagging formats
obj-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
obj-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
+obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qinq.o
obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o
# switch drivers
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -321,6 +321,19 @@ static const struct net_device_ops edsa_
.ndo_do_ioctl = dsa_slave_ioctl,
};
#endif
+#ifdef CONFIG_NET_DSA_TAG_QINQ
+static const struct net_device_ops qinq_netdev_ops = {
+ .ndo_init = dsa_slave_init,
+ .ndo_open = dsa_slave_open,
+ .ndo_stop = dsa_slave_close,
+ .ndo_start_xmit = qinq_xmit,
+ .ndo_change_rx_flags = dsa_slave_change_rx_flags,
+ .ndo_set_rx_mode = dsa_slave_set_rx_mode,
+ .ndo_set_multicast_list = dsa_slave_set_rx_mode,
+ .ndo_set_mac_address = dsa_slave_set_mac_address,
+ .ndo_do_ioctl = dsa_slave_ioctl,
+};
+#endif
#ifdef CONFIG_NET_DSA_TAG_TRAILER
static const struct net_device_ops trailer_netdev_ops = {
.ndo_init = dsa_slave_init,
@@ -366,6 +379,11 @@ dsa_slave_create(struct dsa_switch *ds,
slave_dev->netdev_ops = &edsa_netdev_ops;
break;
#endif
+#ifdef CONFIG_NET_DSA_TAG_QINQ
+ case htons(ETH_P_QINQ):
+ slave_dev->netdev_ops = &qinq_netdev_ops;
+ break;
+#endif
#ifdef CONFIG_NET_DSA_TAG_TRAILER
case htons(ETH_P_TRAILER):
slave_dev->netdev_ops = &trailer_netdev_ops;

View File

@ -1,28 +0,0 @@
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -29,6 +29,15 @@ config NET_DSA_TAG_QINQ
# switch drivers
+config NET_DSA_AR7240
+ bool "Atheros AR7240 built-in ethernet switch support"
+ depends on ATHEROS_AR71XX
+ default n
+ select NET_DSA_TAG_QINQ
+ ---help---
+ This enables support for the built-in ethernet switch of the
+ Atheros AR7240 SoC.
+
config NET_DSA_MV88E6XXX
bool
default n
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_TAG_QINQ) += tag_qi
obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o
# switch drivers
+obj-$(CONFIG_NET_DSA_AR7240) += ar7240.o
obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o

View File

@ -1,54 +0,0 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -60,31 +60,32 @@ static int parse_redboot_partitions(stru
static char nullstring[] = "unallocated";
#endif
+ buf = vmalloc(master->erasesize);
+ if (!buf)
+ return -ENOMEM;
+
+ restart:
if ( directory < 0 ) {
offset = master->size + directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
if (!offset) {
nogood:
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
+ vfree(buf);
return -EIO;
}
offset -= master->erasesize;
}
} else {
offset = directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
offset += master->erasesize;
if (offset == master->size)
goto nogood;
}
}
- buf = vmalloc(master->erasesize);
-
- if (!buf)
- return -ENOMEM;
-
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
master->name, offset);
@@ -156,6 +157,11 @@ static int parse_redboot_partitions(stru
}
if (i == numslots) {
/* Didn't find it */
+ if (offset + master->erasesize < master->size) {
+ /* not at the end of the flash yet, maybe next block :) */
+ directory++;
+ goto restart;
+ }
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
master->name);
ret = 0;

View File

@ -1,21 +0,0 @@
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -488,4 +488,8 @@ config MTD_NAND_W90P910
This enables the driver for the NAND Flash on evaluation board based
on w90p910.
+config MTD_NAND_RB4XX
+ tristate "NAND flash driver for RouterBoard 4xx series"
+ depends on MTD_NAND && AR71XX_MACH_RB4XX
+
endif # MTD_NAND
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o

View File

@ -1,27 +0,0 @@
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@ endif
obj-$(CONFIG_SPI_MASTER) += spi.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AP83) += ap83_spi.o
obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o
obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -53,6 +53,14 @@ if SPI_MASTER
comment "SPI Master Controller Drivers"
+config SPI_AP83
+ tristate "Atheros AP83 specific SPI Controller"
+ depends on SPI_MASTER && AR71XX_MACH_AP83
+ select SPI_BITBANG
+ help
+ This is a specific SPI controller driver for the Atheros AP83
+ reference board.
+
config SPI_AR71XX
tristate "Atheros AR71xx SPI Controller"
depends on SPI_MASTER && ATHEROS_AR71XX

View File

@ -1,24 +0,0 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -365,6 +365,11 @@ config SPI_TLE62X0
sysfs interface, with each line presented as a kind of GPIO
exposing both switch control and diagnostic feedback.
+config SPI_VSC7385
+ tristate "Vitesse VSC7385 ethernet switch driver"
+ help
+ SPI driver for the Vitesse VSC7385 ethernet switch.
+
#
# Add new SPI protocol masters in alphabetical order above this line
#
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -54,6 +54,7 @@ spi_s3c24xx_hw-$(CONFIG_SPI_S3C24XX_FIQ)
# SPI protocol drivers (device/link on bus)
obj-$(CONFIG_SPI_SPIDEV) += spidev.o
+obj-$(CONFIG_SPI_VSC7385) += spi_vsc7385.o
obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o
# ... add above this line ...

View File

@ -1,27 +0,0 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -68,6 +68,14 @@ config SPI_AR71XX
help
This is the SPI contoller driver for Atheros AR71xx.
+config SPI_PB44
+ tristate "Atheros PB44 board specific SPI controller"
+ depends on SPI_MASTER && AR71XX_MACH_PB44
+ select SPI_BITBANG
+ help
+ This is a specific SPI controller driver for the Atheros PB44
+ reference board.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on (ARCH_AT91 || AVR32)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o
obj-$(CONFIG_SPI_IMX) += spi_imx.o
obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
+obj-$(CONFIG_SPI_PB44) += pb44_spi.o
obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o

View File

@ -1,26 +0,0 @@
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -269,6 +269,13 @@ config LEDS_ADP5520
To compile this driver as a module, choose M here: the module will
be called leds-adp5520.
+config LEDS_WNDR3700_USB
+ tristate "NETGEAR WNDR3700 USB LED driver"
+ depends on LEDS_CLASS && AR71XX_MACH_WNDR3700
+ help
+ This option enables support for the USB LED found on the
+ NETGEAR WNDR3700 board.
+
comment "LED Triggers"
config LEDS_TRIGGERS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903
obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
+obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o
obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o

View File

@ -1,25 +0,0 @@
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -255,4 +255,12 @@ config GPIO_UCB1400
To compile this driver as a module, choose M here: the
module will be called ucb1400_gpio.
+comment "Other GPIO expanders"
+
+config GPIO_NXP_74HC153
+ tristate "NXP 74HC153 Dual 4-input multiplexer"
+ help
+ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
+ provides a GPIO interface supporting inputs.
+
endif
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o
obj-$(CONFIG_GPIO_MAX732X) += max732x.o
obj-$(CONFIG_GPIO_MC33880) += mc33880.o
obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o
+obj-$(CONFIG_GPIO_NXP_74HC153) += nxp_74hc153.o
obj-$(CONFIG_GPIO_PCA953X) += pca953x.o
obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
obj-$(CONFIG_GPIO_PL061) += pl061.o

View File

@ -1,23 +0,0 @@
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -276,6 +276,10 @@ config LEDS_WNDR3700_USB
This option enables support for the USB LED found on the
NETGEAR WNDR3700 board.
+config LEDS_RB750
+ tristate "LED driver for the Mikrotik RouterBOARD 750"
+ depends on LEDS_CLASS && AR71XX_MACH_RB750
+
comment "LED Triggers"
config LEDS_TRIGGERS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_LEDS_REGULATOR) += leds-re
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o
+obj-$(CONFIG_LEDS_RB750) += leds-rb750.o
# LED SPI Drivers
obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o

View File

@ -1,21 +0,0 @@
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -492,4 +492,8 @@ config MTD_NAND_RB4XX
tristate "NAND flash driver for RouterBoard 4xx series"
depends on MTD_NAND && AR71XX_MACH_RB4XX
+config MTD_NAND_RB750
+ tristate "NAND flash driver for the RouterBoard 750"
+ depends on MTD_NAND && AR71XX_MACH_RB750
+
endif # MTD_NAND
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
+obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
obj-$(CONFIG_MTD_ALAUDA) += alauda.o
obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o

View File

@ -1,22 +0,0 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -188,6 +188,7 @@ endif
#
libs-$(CONFIG_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
libs-y += arch/mips/fw/lib/
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -877,6 +877,9 @@ config MIPS_NILE4
config MIPS_DISABLE_OBSOLETE_IDE
bool
+config MYLOADER
+ bool
+
config SYNC_R4K
bool

View File

@ -1,134 +0,0 @@
--- a/arch/mips/kernel/mips_machine.c
+++ b/arch/mips/kernel/mips_machine.c
@@ -7,12 +7,13 @@
*
*/
#include <linux/mm.h>
+#include <linux/string.h>
#include <asm/mips_machine.h>
-#include <asm/bootinfo.h>
static struct list_head mips_machines __initdata =
LIST_HEAD_INIT(mips_machines);
+static char *mips_machid __initdata;
char *mips_machine_name = "Unknown";
@@ -55,20 +56,65 @@ void __init mips_machine_set_name(char *
}
}
-void __init mips_machine_setup(unsigned long machtype)
+void __init mips_machine_setup(void)
{
struct mips_machine *mach;
- mach = mips_machine_find(machtype);
+ mach = mips_machine_find(mips_machtype);
if (!mach) {
- printk(KERN_ALERT "MIPS: no machine registered for "
- "machtype %lu\n", machtype);
+ printk(KERN_WARNING "MIPS: no machine registered for "
+ "machtype %lu\n", mips_machtype);
return;
}
mips_machine_set_name(mach->mach_name);
- printk(KERN_INFO "MIPS: machine is %s\n", mips_machine_name);
+ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name);
if (mach->mach_setup)
mach->mach_setup();
}
+
+int __init mips_machtype_setup(char *id)
+{
+ if (mips_machid == NULL)
+ mips_machid = id;
+
+ return 1;
+}
+
+__setup("machtype=", mips_machtype_setup);
+
+static int __init mips_machtype_init(void)
+{
+ struct list_head *this;
+ struct mips_machine *mach;
+
+ if (mips_machid == NULL)
+ return 0;
+
+ list_for_each(this, &mips_machines) {
+ mach = list_entry(this, struct mips_machine, list);
+ if (mach->mach_id == NULL)
+ continue;
+
+ if (strcmp(mach->mach_id, mips_machid) == 0) {
+ mips_machtype = mach->mach_type;
+ return 0;
+ }
+ }
+
+ printk(KERN_WARNING
+ "MIPS: no machine found for id: '%s', registered machines:\n",
+ mips_machid);
+ printk(KERN_WARNING "%32s %s\n", "id", "name");
+
+ list_for_each(this, &mips_machines) {
+ mach = list_entry(this, struct mips_machine, list);
+ printk(KERN_WARNING "%32s %s\n",
+ mach->mach_id ? mach->mach_id : "", mach->mach_name);
+ }
+
+ return 0;
+}
+
+core_initcall(mips_machtype_init);
--- a/arch/mips/include/asm/mips_machine.h
+++ b/arch/mips/include/asm/mips_machine.h
@@ -13,25 +13,33 @@
#include <linux/init.h>
#include <linux/list.h>
+#include <asm/bootinfo.h>
+
struct mips_machine {
unsigned long mach_type;
- void (*mach_setup)(void);
+ char *mach_id;
char *mach_name;
+ void (*mach_setup)(void);
struct list_head list;
};
void mips_machine_register(struct mips_machine *) __init;
-void mips_machine_setup(unsigned long machtype) __init;
+void mips_machine_setup(void) __init;
+int mips_machtype_setup(char *id) __init;
void mips_machine_set_name(char *name) __init;
extern char *mips_machine_name;
-#define MIPS_MACHINE(_type, _name, _setup) \
-static char machine_name_##_type[] __initdata = _name; \
+#define MIPS_MACHINE(_type, _id, _name, _setup) \
+static const char machine_name_##_type[] __initconst \
+ __aligned(1) = _name; \
+static const char machine_id_##_type[] __initconst \
+ __aligned(1) = _id; \
static struct mips_machine machine_##_type __initdata = \
{ \
.mach_type = _type, \
- .mach_name = machine_name_##_type, \
+ .mach_id = (char *) machine_id_##_type, \
+ .mach_name = (char *) machine_name_##_type, \
.mach_setup = _setup, \
}; \
\
@@ -44,4 +52,3 @@ static int __init register_machine_##_ty
pure_initcall(register_machine_##_type)
#endif /* __ASM_MIPS_MACHINE_H */
-

View File

@ -1,29 +0,0 @@
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -51,6 +51,7 @@
#include <asm/stacktrace.h>
#include <asm/irq.h>
#include <asm/uasm.h>
+#include <asm/time.h>
extern void check_wait(void);
extern asmlinkage void r4k_wait(void);
@@ -1501,6 +1502,8 @@
if (cpu_has_mips_r2) {
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
+ if (get_c0_compare_irq)
+ cp0_compare_irq = get_c0_compare_irq();
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -52,6 +52,7 @@ extern int (*perf_irq)(void);
*/
#ifdef CONFIG_CEVT_R4K_LIB
extern unsigned int __weak get_c0_compare_int(void);
+extern unsigned int __weak get_c0_compare_irq(void);
extern int r4k_clockevent_init(void);
#endif

View File

@ -1,56 +0,0 @@
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -16,6 +16,22 @@
#include <asm/cevt-r4k.h>
/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register. 4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+ do { \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ } while (0)
+
+/*
* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
* of these routines with SMTC-specific variants.
*/
@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
+ compare_change_hazard();
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
return res;
}
@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
}
-/*
- * Compare interrupt can be routed and latched outside the core,
- * so a single execution hazard barrier may not be enough to give
- * it time to clear as seen in the Cause register. 4 time the
- * pipeline depth seems reasonably conservative, and empirically
- * works better in configurations with high CPU/bus clock ratios.
- */
-
-#define compare_change_hazard() \
- do { \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- } while (0)
-
int c0_compare_int_usable(void)
{
unsigned int delta;

View File

@ -1,201 +0,0 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_ADM6996_PHY=y
# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
CONFIG_AR231X_ETHERNET=y
# CONFIG_AR7 is not set
CONFIG_AR8216_PHY=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ATHEROS_AR2315=y
CONFIG_ATHEROS_AR2315_PCI=y
CONFIG_ATHEROS_AR231X=y
CONFIG_ATHEROS_AR5312=y
CONFIG_ATHEROS_WDT=y
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
CONFIG_BITREVERSE=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_BUG is not set
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CEVT_R4K=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_CAVIUM_OCTEON is not set
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_CPU_LOONGSON2E is not set
# CONFIG_CPU_LOONGSON2F is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CSRC_R4K=y
CONFIG_CSRC_R4K_LIB=y
CONFIG_DECOMPRESS_LZMA=y
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
# CONFIG_FSNOTIFY is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GPIO_DEVICE=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_IMAGE_CMDLINE_HACK=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
CONFIG_IP175C_PHY=y
CONFIG_IRQ_CPU=y
# CONFIG_LEDS_GPIO is not set
CONFIG_LOONGSON_UART_BASE=y
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_LOONGSON is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MIKROTIK_RB532 is not set
CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MTD_AR2315=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
# CONFIG_MTD_CFI_GEOMETRY is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_MYLOADER_PARTS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
CONFIG_MTD_REDBOOT_PARTS=y
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
CONFIG_MVSWITCH_PHY=y
# CONFIG_NET_PCI is not set
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PHYLIB=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_POWERTV is not set
CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_EXTENDED is not set
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SWAP is not set
CONFIG_SWCONFIG=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_TRAD_SIGNALS=y
# CONFIG_TREE_PREEMPT_RCU is not set
CONFIG_USB_SUPPORT=y
CONFIG_ZONE_DMA_FLAG=0

View File

@ -1,39 +0,0 @@
Fix the usage of get_c0_compare_int: override cp0_compare_irq if the returned
value is in the MIPS CPU IRQ range to ensure that c0_compare_int_usable()
still works.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -168,20 +168,23 @@ int __cpuinit r4k_clockevent_init(void)
struct clock_event_device *cd;
unsigned int irq;
- if (!cpu_has_counter || !mips_hpt_frequency)
- return -ENXIO;
-
- if (!c0_compare_int_usable())
- return -ENXIO;
-
/*
* With vectored interrupts things are getting platform specific.
* get_c0_compare_int is a hook to allow a platform to return the
* interrupt number of it's liking.
*/
irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
- if (get_c0_compare_int)
+ if (get_c0_compare_int) {
irq = get_c0_compare_int();
+ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8))
+ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE;
+ }
+
+ if (!cpu_has_counter || !mips_hpt_frequency)
+ return -ENXIO;
+
+ if (!c0_compare_int_usable())
+ return -ENXIO;
cd = &per_cpu(mips_clockevent_device, cpu);

View File

@ -1,56 +0,0 @@
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -16,6 +16,22 @@
#include <asm/cevt-r4k.h>
/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register. 4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+ do { \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ irq_disable_hazard(); \
+ } while (0)
+
+/*
* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
* of these routines with SMTC-specific variants.
*/
@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
+ compare_change_hazard();
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
return res;
}
@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
}
-/*
- * Compare interrupt can be routed and latched outside the core,
- * so a single execution hazard barrier may not be enough to give
- * it time to clear as seen in the Cause register. 4 time the
- * pipeline depth seems reasonably conservative, and empirically
- * works better in configurations with high CPU/bus clock ratios.
- */
-
-#define compare_change_hazard() \
- do { \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- } while (0)
-
int c0_compare_int_usable(void)
{
unsigned int delta;

File diff suppressed because it is too large Load Diff

View File

@ -1,68 +0,0 @@
--- /dev/null
+++ b/arch/mips/ar231x/early_printk.c
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-ar231x/ar2315_regs.h>
+#include <asm/mach-ar231x/ar5312_regs.h>
+#include "devices.h"
+
+static inline void prom_uart_wr(void __iomem *base, unsigned reg,
+ unsigned char ch)
+{
+ __raw_writeb(ch, base + 4 * reg);
+}
+
+static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg)
+{
+ return __raw_readb(base + 4 * reg);
+}
+
+void prom_putchar(unsigned char ch)
+{
+ static void __iomem *base;
+
+ if (unlikely(base == NULL)) {
+ if (is_2315())
+ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0));
+ else
+ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0));
+ }
+
+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0);
+ prom_uart_wr(base, UART_TX, ch);
+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0);
+}
+
--- a/arch/mips/ar231x/Makefile
+++ b/arch/mips/ar231x/Makefile
@@ -9,5 +9,8 @@
#
obj-y += board.o prom.o devices.o
+
+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+
obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -94,6 +94,7 @@ config ATHEROS_AR231X
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_32BIT_KERNEL
select GENERIC_GPIO
+ select SYS_HAS_EARLY_PRINTK
help
Support for AR231x and AR531x based boards

View File

@ -1,297 +0,0 @@
--- a/arch/mips/ar231x/Makefile
+++ b/arch/mips/ar231x/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
--- /dev/null
+++ b/arch/mips/ar231x/pci.c
@@ -0,0 +1,230 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <asm/bootinfo.h>
+#include <asm/paccess.h>
+#include <asm/irq_cpu.h>
+#include <asm/io.h>
+#include <ar231x_platform.h>
+#include <ar231x.h>
+#include <ar2315_regs.h>
+#include "devices.h"
+
+#define AR531X_MEM_BASE 0x80800000UL
+#define AR531X_MEM_SIZE 0x00ffffffUL
+#define AR531X_IO_SIZE 0x00007fffUL
+
+static unsigned long configspace;
+
+static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
+{
+ unsigned long flags;
+ int func = PCI_FUNC(devfn);
+ int dev = PCI_SLOT(devfn);
+ u32 value = 0;
+ int err = 0;
+ u32 addr;
+
+ if (((dev != 0) && (dev != 3)) || (func > 2))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Select Configuration access */
+ local_irq_save(flags);
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
+ mb();
+
+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
+ if (size == 1)
+ addr ^= 0x3;
+ else if (size == 2)
+ addr ^= 0x2;
+
+ if (write) {
+ value = *ptr;
+ if (size == 1)
+ err = put_dbe(value, (u8 *) addr);
+ else if (size == 2)
+ err = put_dbe(value, (u16 *) addr);
+ else if (size == 4)
+ err = put_dbe(value, (u32 *) addr);
+ } else {
+ if (size == 1)
+ err = get_dbe(value, (u8 *) addr);
+ else if (size == 2)
+ err = get_dbe(value, (u16 *) addr);
+ else if (size == 4)
+ err = get_dbe(value, (u32 *) addr);
+ if (err)
+ *ptr = 0xffffffff;
+ else
+ *ptr = value;
+ }
+
+ /* Select Memory access */
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
+ local_irq_restore(flags);
+
+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
+}
+
+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
+{
+ return config_access(devfn, where, size, value, 0);
+}
+
+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
+{
+ return config_access(devfn, where, size, &value, 1);
+}
+
+struct pci_ops ar231x_pci_ops = {
+ .read = ar231x_pci_read,
+ .write = ar231x_pci_write,
+};
+
+static struct resource ar231x_mem_resource = {
+ .name = "AR531x PCI MEM",
+ .start = AR531X_MEM_BASE,
+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource ar231x_io_resource = {
+ .name = "AR531x PCI I/O",
+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
+ .flags = IORESOURCE_IO,
+};
+
+struct pci_controller ar231x_pci_controller = {
+ .pci_ops = &ar231x_pci_ops,
+ .mem_resource = &ar231x_mem_resource,
+ .io_resource = &ar231x_io_resource,
+ .mem_offset = 0x00000000UL,
+ .io_offset = 0x00000000UL,
+};
+
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ return AR2315_IRQ_LCBUS_PCI;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
+ pci_write_config_word(dev, 0x40, 0);
+
+ /* Clear any pending Abort or external Interrupts
+ * and enable interrupt processing */
+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
+
+ return 0;
+}
+
+static void
+ar2315_pci_fixup(struct pci_dev *dev)
+{
+ unsigned int devfn = dev->devfn;
+
+ if (dev->bus->number != 0)
+ return;
+
+ /* Only fix up the PCI host settings */
+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
+ return;
+
+ /* Fix up MBARs */
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
+ pci_write_config_dword(dev, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
+ PCI_COMMAND_FAST_BACK);
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
+
+static int __init
+ar2315_pci_init(void)
+{
+ u32 reg;
+
+ if (ar231x_devtype != DEV_TYPE_AR2315)
+ return -ENODEV;
+
+ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
+ ar231x_pci_controller.io_map_base =
+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
+
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
+ msleep(10);
+
+ reg &= ~AR2315_RESET_PCIDMA;
+ ar231x_write_reg(AR2315_RESET, reg);
+ msleep(10);
+
+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
+
+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
+
+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
+ AR2315_PCIRST_LOW);
+ msleep(100);
+
+ /* Bring the PCI out of reset */
+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
+
+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
+ 0x1E | /* 1GB uncached */
+ (1 << 5) | /* Enable uncached */
+ (0x2 << 30) /* Base: 0x80000000 */
+ );
+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
+
+ msleep(500);
+
+ /* dirty hack - anyone with a datasheet that knows the memory map ? */
+ ioport_resource.start = 0x10000000;
+ ioport_resource.end = 0xffffffff;
+ iomem_resource.start = 0x10000000;
+ iomem_resource.end = 0xffffffff;
+
+ register_pci_controller(&ar231x_pci_controller);
+
+ return 0;
+}
+
+arch_initcall(ar2315_pci_init);
--- a/arch/mips/ar231x/Kconfig
+++ b/arch/mips/ar231x/Kconfig
@@ -15,3 +15,13 @@ config ATHEROS_AR2315
select SYS_SUPPORTS_BIG_ENDIAN
select GENERIC_GPIO
default y
+
+config ATHEROS_AR2315_PCI
+ bool "PCI support"
+ depends on ATHEROS_AR2315
+ select HW_HAS_PCI
+ select PCI
+ select USB_ARCH_HAS_HCD
+ select USB_ARCH_HAS_OHCI
+ select USB_ARCH_HAS_EHCI
+ default y
--- a/arch/mips/ar231x/ar2315.c
+++ b/arch/mips/ar231x/ar2315.c
@@ -63,6 +63,27 @@ static inline void ar2315_gpio_irq(void)
do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
}
+#ifdef CONFIG_ATHEROS_AR2315_PCI
+static inline void pci_abort_irq(void)
+{
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
+}
+
+static inline void pci_ack_irq(void)
+{
+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
+}
+
+void ar2315_pci_irq(int irq)
+{
+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
+ pci_abort_irq();
+ else {
+ do_IRQ(irq);
+ pci_ack_irq();
+ }
+}
+#endif /* CONFIG_ATHEROS_AR2315_PCI */
/*
* Called when an interrupt is received, this function
@@ -81,6 +102,10 @@ ar2315_irq_dispatch(void)
do_IRQ(AR2315_IRQ_WLAN0_INTRS);
else if (pending & CAUSEF_IP4)
do_IRQ(AR2315_IRQ_ENET0_INTRS);
+#ifdef CONFIG_ATHEROS_AR2315_PCI
+ else if (pending & CAUSEF_IP5)
+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
+#endif
else if (pending & CAUSEF_IP2) {
unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);

File diff suppressed because it is too large Load Diff

View File

@ -1,659 +0,0 @@
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -112,6 +112,10 @@ config MTD_SST25L
Set up your spi devices with the right board-specific platform data,
if you want to specify device partitioning.
+config MTD_AR2315
+ tristate "Atheros AR2315+ SPI Flash support"
+ depends on ATHEROS_AR2315
+
config MTD_SLRAM
tristate "Uncached system RAM"
help
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd
obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
obj-$(CONFIG_MTD_M25P80) += m25p80.o
obj-$(CONFIG_MTD_SST25L) += sst25l.o
+obj-$(CONFIG_MTD_AR2315) += ar2315.o
--- /dev/null
+++ b/drivers/mtd/devices/ar2315.c
@@ -0,0 +1,517 @@
+
+/*
+ * MTD driver for the SPI Flash Memory support on Atheros AR2315
+ *
+ * Copyright (c) 2005-2006 Atheros Communications Inc.
+ * Copyright (C) 2006-2007 FON Technology, SL.
+ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/root_dev.h>
+#include <linux/delay.h>
+#include <asm/delay.h>
+#include <asm/io.h>
+
+#include <ar2315_spiflash.h>
+#include <ar231x_platform.h>
+#include <ar231x.h>
+
+
+#define SPIFLASH "spiflash: "
+#define busy_wait(_priv, _condition, _wait) do { \
+ while (_condition) { \
+ spin_unlock_bh(&_priv->lock); \
+ if (_wait > 1) \
+ msleep(_wait); \
+ else if ((_wait == 1) && need_resched()) \
+ schedule(); \
+ else \
+ udelay(1); \
+ spin_lock_bh(&_priv->lock); \
+ } \
+} while (0)
+
+enum {
+ FLASH_NONE,
+ FLASH_1MB,
+ FLASH_2MB,
+ FLASH_4MB,
+ FLASH_8MB,
+ FLASH_16MB,
+};
+
+/* Flash configuration table */
+struct flashconfig {
+ u32 byte_cnt;
+ u32 sector_cnt;
+ u32 sector_size;
+};
+
+const struct flashconfig flashconfig_tbl[] = {
+ [FLASH_NONE] = { 0, 0, 0},
+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE},
+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE},
+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE},
+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE},
+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE}
+};
+
+/* Mapping of generic opcodes to STM serial flash opcodes */
+enum {
+ SPI_WRITE_ENABLE,
+ SPI_WRITE_DISABLE,
+ SPI_RD_STATUS,
+ SPI_WR_STATUS,
+ SPI_RD_DATA,
+ SPI_FAST_RD_DATA,
+ SPI_PAGE_PROGRAM,
+ SPI_SECTOR_ERASE,
+ SPI_BULK_ERASE,
+ SPI_DEEP_PWRDOWN,
+ SPI_RD_SIG,
+};
+
+struct opcodes {
+ __u16 code;
+ __s8 tx_cnt;
+ __s8 rx_cnt;
+};
+const struct opcodes stm_opcodes[] = {
+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
+};
+
+/* Driver private data structure */
+struct spiflash_priv {
+ struct mtd_info mtd;
+ void *readaddr; /* memory mapped data for read */
+ void *mmraddr; /* memory mapped register space */
+ wait_queue_head_t wq;
+ spinlock_t lock;
+ int state;
+};
+
+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
+
+enum {
+ FL_READY,
+ FL_READING,
+ FL_ERASING,
+ FL_WRITING
+};
+
+/***************************************************************************************************/
+
+static u32
+spiflash_read_reg(struct spiflash_priv *priv, int reg)
+{
+ return ar231x_read_reg((u32) priv->mmraddr + reg);
+}
+
+static void
+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
+{
+ ar231x_write_reg((u32) priv->mmraddr + reg, data);
+}
+
+static u32
+spiflash_wait_busy(struct spiflash_priv *priv)
+{
+ u32 reg;
+
+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
+ SPI_CTL_BUSY, 0);
+ return reg;
+}
+
+static u32
+spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr)
+{
+ const struct opcodes *op;
+ u32 reg, mask;
+
+ op = &stm_opcodes[opcode];
+ reg = spiflash_wait_busy(priv);
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE,
+ ((u32) op->code) | (addr << 8));
+
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
+
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
+ spiflash_wait_busy(priv);
+
+ if (!op->rx_cnt)
+ return 0;
+
+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
+
+ switch (op->rx_cnt) {
+ case 1:
+ mask = 0x000000ff;
+ break;
+ case 2:
+ mask = 0x0000ffff;
+ break;
+ case 3:
+ mask = 0x00ffffff;
+ break;
+ default:
+ mask = 0xffffffff;
+ break;
+ }
+ reg &= mask;
+
+ return reg;
+}
+
+
+/*
+ * Probe SPI flash device
+ * Function returns 0 for failure.
+ * and flashconfig_tbl array index for success.
+ */
+static int
+spiflash_probe_chip (struct spiflash_priv *priv)
+{
+ u32 sig;
+ int flash_size;
+
+ /* Read the signature on the flash device */
+ spin_lock_bh(&priv->lock);
+ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
+ spin_unlock_bh(&priv->lock);
+
+ switch (sig) {
+ case STM_8MBIT_SIGNATURE:
+ flash_size = FLASH_1MB;
+ break;
+ case STM_16MBIT_SIGNATURE:
+ flash_size = FLASH_2MB;
+ break;
+ case STM_32MBIT_SIGNATURE:
+ flash_size = FLASH_4MB;
+ break;
+ case STM_64MBIT_SIGNATURE:
+ flash_size = FLASH_8MB;
+ break;
+ case STM_128MBIT_SIGNATURE:
+ flash_size = FLASH_16MB;
+ break;
+ default:
+ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
+ return 0;
+ }
+
+ return flash_size;
+}
+
+
+/* wait until the flash chip is ready and grab a lock */
+static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
+{
+ DECLARE_WAITQUEUE(wait, current);
+
+retry:
+ spin_lock_bh(&priv->lock);
+ if (priv->state != FL_READY) {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ add_wait_queue(&priv->wq, &wait);
+ spin_unlock_bh(&priv->lock);
+ schedule();
+ remove_wait_queue(&priv->wq, &wait);
+
+ if(signal_pending(current))
+ return 0;
+
+ goto retry;
+ }
+ priv->state = state;
+
+ return 1;
+}
+
+static inline void spiflash_done(struct spiflash_priv *priv)
+{
+ priv->state = FL_READY;
+ spin_unlock_bh(&priv->lock);
+ wake_up(&priv->wq);
+}
+
+static void
+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
+{
+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
+ SPI_STATUS_WIP, timeout);
+ spiflash_done(priv);
+}
+
+
+
+static int
+spiflash_erase (struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct spiflash_priv *priv = to_spiflash(mtd);
+ const struct opcodes *op;
+ u32 temp, reg;
+
+ if (instr->addr + instr->len > mtd->size)
+ return -EINVAL;
+
+ if (!spiflash_wait_ready(priv, FL_ERASING))
+ return -EINTR;
+
+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
+ reg = spiflash_wait_busy(priv);
+
+ op = &stm_opcodes[SPI_SECTOR_ERASE];
+ temp = ((u32)instr->addr << 8) | (u32)(op->code);
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
+
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
+ reg |= op->tx_cnt | SPI_CTL_START;
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
+
+ spiflash_wait_complete(priv, 20);
+
+ instr->state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+
+ return 0;
+}
+
+static int
+spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
+{
+ struct spiflash_priv *priv = to_spiflash(mtd);
+ u8 *read_addr;
+
+ if (!len)
+ return 0;
+
+ if (from + len > mtd->size)
+ return -EINVAL;
+
+ *retlen = len;
+
+ if (!spiflash_wait_ready(priv, FL_READING))
+ return -EINTR;
+
+ read_addr = (u8 *)(priv->readaddr + from);
+ memcpy_fromio(buf, read_addr, len);
+ spiflash_done(priv);
+
+ return 0;
+}
+
+static int
+spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf)
+{
+ struct spiflash_priv *priv = to_spiflash(mtd);
+ u32 opcode, bytes_left;
+
+ *retlen = 0;
+
+ if (!len)
+ return 0;
+
+ if (to + len > mtd->size)
+ return -EINVAL;
+
+ bytes_left = len;
+
+ do {
+ u32 read_len, reg, page_offset, spi_data = 0;
+
+ read_len = min(bytes_left, sizeof(u32));
+
+ /* 32-bit writes cannot span across a page boundary
+ * (256 bytes). This types of writes require two page
+ * program operations to handle it correctly. The STM part
+ * will write the overflow data to the beginning of the
+ * current page as opposed to the subsequent page.
+ */
+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
+
+ if (page_offset > STM_PAGE_SIZE)
+ read_len -= (page_offset - STM_PAGE_SIZE);
+
+ if (!spiflash_wait_ready(priv, FL_WRITING))
+ return -EINTR;
+
+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
+ spi_data = 0;
+ switch (read_len) {
+ case 4:
+ spi_data |= buf[3] << 24;
+ /* fall through */
+ case 3:
+ spi_data |= buf[2] << 16;
+ /* fall through */
+ case 2:
+ spi_data |= buf[1] << 8;
+ /* fall through */
+ case 1:
+ spi_data |= buf[0] & 0xff;
+ break;
+ default:
+ break;
+ }
+
+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
+ (to & 0x00ffffff) << 8;
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
+
+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
+ reg |= (read_len + 4) | SPI_CTL_START;
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
+
+ spiflash_wait_complete(priv, 1);
+
+ bytes_left -= read_len;
+ to += read_len;
+ buf += read_len;
+
+ *retlen += read_len;
+ } while (bytes_left != 0);
+
+ return 0;
+}
+
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
+#endif
+
+
+static int
+spiflash_probe(struct platform_device *pdev)
+{
+ struct spiflash_priv *priv;
+ struct mtd_partition *parts;
+ struct mtd_info *mtd;
+ int index, num_parts;
+ int result = 0;
+
+ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
+ spin_lock_init(&priv->lock);
+ init_waitqueue_head(&priv->wq);
+ priv->state = FL_READY;
+ mtd = &priv->mtd;
+
+ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
+ if (!priv->mmraddr) {
+ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n");
+ goto error;
+ }
+
+ index = spiflash_probe_chip(priv);
+ if (!index) {
+ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
+ goto error;
+ }
+
+ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
+ if (!priv->readaddr) {
+ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
+ goto error;
+ }
+
+ platform_set_drvdata(pdev, priv);
+ mtd->name = "spiflash";
+ mtd->type = MTD_NORFLASH;
+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
+ mtd->size = flashconfig_tbl[index].byte_cnt;
+ mtd->erasesize = flashconfig_tbl[index].sector_size;
+ mtd->writesize = 1;
+ mtd->numeraseregions = 0;
+ mtd->eraseregions = NULL;
+ mtd->erase = spiflash_erase;
+ mtd->read = spiflash_read;
+ mtd->write = spiflash_write;
+ mtd->owner = THIS_MODULE;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ /* parse redboot partitions */
+ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0);
+ if (!num_parts)
+ goto error;
+
+ result = add_mtd_partitions(mtd, parts, num_parts);
+#endif
+
+ return result;
+
+error:
+ if (priv->mmraddr)
+ iounmap(priv->mmraddr);
+ kfree(priv);
+ return -ENXIO;
+}
+
+static int
+spiflash_remove (struct platform_device *pdev)
+{
+ struct spiflash_priv *priv = platform_get_drvdata(pdev);
+ struct mtd_info *mtd = &priv->mtd;
+
+ del_mtd_partitions(mtd);
+ iounmap(priv->mmraddr);
+ iounmap(priv->readaddr);
+ kfree(priv);
+
+ return 0;
+}
+
+struct platform_driver spiflash_driver = {
+ .driver.name = "spiflash",
+ .probe = spiflash_probe,
+ .remove = spiflash_remove,
+};
+
+int __init
+spiflash_init (void)
+{
+ return platform_driver_register(&spiflash_driver);
+}
+
+void __exit
+spiflash_exit (void)
+{
+ return platform_driver_unregister(&spiflash_driver);
+}
+
+module_init (spiflash_init);
+module_exit (spiflash_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
+
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
@@ -0,0 +1,116 @@
+/*
+ * SPI Flash Memory support header file.
+ *
+ * Copyright (c) 2005, Atheros Communications Inc.
+ * Copyright (C) 2006 FON Technology, SL.
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __AR2315_SPIFLASH_H
+#define __AR2315_SPIFLASH_H
+
+#define STM_PAGE_SIZE 256
+
+#define SFI_WRITE_BUFFER_SIZE 4
+#define SFI_FLASH_ADDR_MASK 0x00ffffff
+
+#define STM_8MBIT_SIGNATURE 0x13
+#define STM_M25P80_BYTE_COUNT 1048576
+#define STM_M25P80_SECTOR_COUNT 16
+#define STM_M25P80_SECTOR_SIZE 0x10000
+
+#define STM_16MBIT_SIGNATURE 0x14
+#define STM_M25P16_BYTE_COUNT 2097152
+#define STM_M25P16_SECTOR_COUNT 32
+#define STM_M25P16_SECTOR_SIZE 0x10000
+
+#define STM_32MBIT_SIGNATURE 0x15
+#define STM_M25P32_BYTE_COUNT 4194304
+#define STM_M25P32_SECTOR_COUNT 64
+#define STM_M25P32_SECTOR_SIZE 0x10000
+
+#define STM_64MBIT_SIGNATURE 0x16
+#define STM_M25P64_BYTE_COUNT 8388608
+#define STM_M25P64_SECTOR_COUNT 128
+#define STM_M25P64_SECTOR_SIZE 0x10000
+
+#define STM_128MBIT_SIGNATURE 0x17
+#define STM_M25P128_BYTE_COUNT 16777216
+#define STM_M25P128_SECTOR_COUNT 256
+#define STM_M25P128_SECTOR_SIZE 0x10000
+
+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
+
+/*
+ * ST Microelectronics Opcodes for Serial Flash
+ */
+
+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
+#define STM_OP_RD_STATUS 0x05 /* Read Status */
+#define STM_OP_WR_STATUS 0x01 /* Write Status */
+#define STM_OP_RD_DATA 0x03 /* Read Data */
+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
+
+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
+
+/*
+ * SPI Flash Interface Registers
+ */
+#define AR531XPLUS_SPI_READ 0x08000000
+#define AR531XPLUS_SPI_MMR 0x11300000
+#define AR531XPLUS_SPI_MMR_SIZE 12
+
+#define AR531XPLUS_SPI_CTL 0x00
+#define AR531XPLUS_SPI_OPCODE 0x04
+#define AR531XPLUS_SPI_DATA 0x08
+
+#define SPI_FLASH_READ AR531XPLUS_SPI_READ
+#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR
+#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE
+#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL
+#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE
+#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA
+
+#define SPI_CTL_START 0x00000100
+#define SPI_CTL_BUSY 0x00010000
+#define SPI_CTL_TXCNT_MASK 0x0000000f
+#define SPI_CTL_RXCNT_MASK 0x000000f0
+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
+#define SPI_CTL_SIZE_MASK 0x00060000
+
+#define SPI_CTL_CLK_SEL_MASK 0x03000000
+#define SPI_OPCODE_MASK 0x000000ff
+
+#define SPI_STATUS_WIP STM_STATUS_WIP
+
+#endif

View File

@ -1,228 +0,0 @@
--- /dev/null
+++ b/drivers/watchdog/ar2315-wtd.c
@@ -0,0 +1,200 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
+ * Based on EP93xx and ifxmips wdt driver
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/fs.h>
+#include <linux/ioport.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/addrspace.h>
+#include <ar231x_platform.h>
+#include <ar2315_regs.h>
+#include <ar231x.h>
+
+#define CLOCK_RATE 40000000
+#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x)
+
+static int wdt_timeout = 20;
+static int started = 0;
+static int in_use = 0;
+
+static void
+ar2315_wdt_enable(void)
+{
+ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE);
+ ar231x_write_reg(AR2315_ISR, 0x80);
+}
+
+static ssize_t
+ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos)
+{
+ if(len)
+ ar2315_wdt_enable();
+ return len;
+}
+
+static int
+ar2315_wdt_open(struct inode *inode, struct file *file)
+{
+ if(in_use)
+ return -EBUSY;
+ ar2315_wdt_enable();
+ in_use = started = 1;
+ return nonseekable_open(inode, file);
+}
+
+static int
+ar2315_wdt_release(struct inode *inode, struct file *file)
+{
+ in_use = 0;
+ return 0;
+}
+
+static irqreturn_t
+ar2315_wdt_interrupt(int irq, void *dev_id)
+{
+ if(started)
+ {
+ printk(KERN_CRIT "watchdog expired, rebooting system\n");
+ emergency_restart();
+ } else {
+ ar231x_write_reg(AR2315_WDC, 0);
+ ar231x_write_reg(AR2315_WD, 0);
+ ar231x_write_reg(AR2315_ISR, 0x80);
+ }
+ return IRQ_HANDLED;
+}
+
+static struct watchdog_info ident = {
+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+ .identity = "ar2315 Watchdog",
+};
+
+static int
+ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+ int new_wdt_timeout;
+ int ret = -ENOIOCTLCMD;
+
+ switch(cmd)
+ {
+ case WDIOC_GETSUPPORT:
+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0;
+ break;
+
+ case WDIOC_KEEPALIVE:
+ ar2315_wdt_enable();
+ ret = 0;
+ break;
+
+ case WDIOC_SETTIMEOUT:
+ if((ret = get_user(new_wdt_timeout, (int __user *)arg)))
+ break;
+ wdt_timeout = HEARTBEAT(new_wdt_timeout);
+ ar2315_wdt_enable();
+ break;
+
+ case WDIOC_GETTIMEOUT:
+ ret = put_user(wdt_timeout, (int __user *)arg);
+ break;
+ }
+ return ret;
+}
+
+static struct file_operations ar2315_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = ar2315_wdt_write,
+ .ioctl = ar2315_wdt_ioctl,
+ .open = ar2315_wdt_open,
+ .release = ar2315_wdt_release,
+};
+
+static struct miscdevice ar2315_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &ar2315_wdt_fops,
+};
+
+static int
+ar2315_wdt_probe(struct platform_device *dev)
+{
+ int ret = 0;
+
+ ar2315_wdt_enable();
+ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL);
+ if(ret)
+ {
+ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n");
+ goto out;
+ }
+
+ ret = misc_register(&ar2315_wdt_miscdev);
+ if(ret)
+ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n");
+
+out:
+ return ret;
+}
+
+static int
+ar2315_wdt_remove(struct platform_device *dev)
+{
+ misc_deregister(&ar2315_wdt_miscdev);
+ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL);
+ return 0;
+}
+
+static struct platform_driver ar2315_wdt_driver = {
+ .probe = ar2315_wdt_probe,
+ .remove = ar2315_wdt_remove,
+ .driver = {
+ .name = "ar2315_wdt",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init
+init_ar2315_wdt(void)
+{
+ int ret = platform_driver_register(&ar2315_wdt_driver);
+ if(ret)
+ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!");
+ return ret;
+}
+
+static void __exit
+exit_ar2315_wdt(void)
+{
+ platform_driver_unregister(&ar2315_wdt_driver);
+}
+
+module_init(init_ar2315_wdt);
+module_exit(exit_ar2315_wdt);
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -840,6 +840,12 @@ config TXX9_WDT
help
Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
+config ATHEROS_WDT
+ tristate "Atheros wisoc Watchdog Timer"
+ depends on ATHEROS_AR231X
+ help
+ Hardware driver for the Atheros wisoc Watchdog Timer.
+
# PARISC Architecture
# POWERPC Architecture
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -112,6 +112,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o
# PARISC Architecture

View File

@ -1,54 +0,0 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -60,31 +60,32 @@ static int parse_redboot_partitions(stru
static char nullstring[] = "unallocated";
#endif
+ buf = vmalloc(master->erasesize);
+ if (!buf)
+ return -ENOMEM;
+
+ restart:
if ( directory < 0 ) {
offset = master->size + directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
if (!offset) {
nogood:
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
+ vfree(buf);
return -EIO;
}
offset -= master->erasesize;
}
} else {
offset = directory * master->erasesize;
- while (master->block_isbad &&
+ while (master->block_isbad &&
master->block_isbad(master, offset)) {
offset += master->erasesize;
if (offset == master->size)
goto nogood;
}
}
- buf = vmalloc(master->erasesize);
-
- if (!buf)
- return -ENOMEM;
-
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
master->name, offset);
@@ -156,6 +157,11 @@ static int parse_redboot_partitions(stru
}
if (i == numslots) {
/* Didn't find it */
+ if (offset + master->erasesize < master->size) {
+ /* not at the end of the flash yet, maybe next block :) */
+ directory++;
+ goto restart;
+ }
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
master->name);
ret = 0;

View File

@ -1,72 +0,0 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -39,6 +39,22 @@ static inline int redboot_checksum(struc
return 1;
}
+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset)
+{
+ struct mtd_erase_region_info *regions = mtd->eraseregions;
+ int i;
+
+ for (i = 0; i < mtd->numeraseregions; i++) {
+ if (regions[i].offset +
+ regions[i].numblocks * regions[i].erasesize <= offset)
+ continue;
+
+ return regions[i].erasesize;
+ }
+
+ return mtd->erasesize;
+}
+
static int parse_redboot_partitions(struct mtd_info *master,
struct mtd_partition **pparts,
unsigned long fis_origin)
@@ -55,6 +71,7 @@ static int parse_redboot_partitions(stru
int namelen = 0;
int nulllen = 0;
int numslots;
+ int first_slot;
unsigned long offset;
#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
static char nullstring[] = "unallocated";
@@ -168,7 +185,10 @@ static int parse_redboot_partitions(stru
goto out;
}
- for (i = 0; i < numslots; i++) {
+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) /
+ sizeof(struct fis_image_desc);
+
+ for (i = first_slot; i < first_slot + numslots; i++) {
struct fis_list *new_fl, **prev;
if (buf[i].name[0] == 0xff) {
@@ -244,12 +264,13 @@ static int parse_redboot_partitions(stru
}
#endif
for ( ; i<nrparts; i++) {
- if(max_offset < buf[i].flash_base + buf[i].size)
- max_offset = buf[i].flash_base + buf[i].size;
parts[i].size = fl->img->size;
parts[i].offset = fl->img->flash_base;
parts[i].name = names;
+ if (max_offset < parts[i].offset + parts[i].size)
+ max_offset = parts[i].offset + parts[i].size;
+
strcpy(names, fl->img->name);
#ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY
if (!memcmp(names, "RedBoot", 8) ||
@@ -279,7 +300,9 @@ static int parse_redboot_partitions(stru
fl = fl->next;
kfree(tmp_fl);
}
- if(master->size - max_offset >= master->erasesize)
+
+ if (master->size - max_offset >=
+ mtd_get_offset_erasesize(master, max_offset))
{
parts[nrparts].size = master->size - max_offset;
parts[nrparts].offset = max_offset;

View File

@ -1,70 +0,0 @@
--- a/drivers/net/ar231x.c
+++ b/drivers/net/ar231x.c
@@ -735,6 +735,7 @@ static void ar231x_load_rx_ring(struct n
for (i = 0; i < nr_bufs; i++) {
struct sk_buff *skb;
ar231x_descr_t *rd;
+ int offset = RX_OFFSET;
if (sp->rx_skb[idx])
break;
@@ -750,7 +751,9 @@ static void ar231x_load_rx_ring(struct n
* Make sure IP header starts on a fresh cache line.
*/
skb->dev = dev;
- skb_reserve(skb, RX_OFFSET);
+ if (sp->phy_dev)
+ offset += sp->phy_dev->pkt_align;
+ skb_reserve(skb, offset);
sp->rx_skb[idx] = skb;
rd = (ar231x_descr_t *) & sp->rx_ring[idx];
@@ -824,20 +827,23 @@ static int ar231x_rx_int(struct net_devi
/* alloc new buffer. */
skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET);
if (skb_new != NULL) {
+ int offset;
skb = sp->rx_skb[idx];
/* set skb */
skb_put(skb,
((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
-
dev->stats.rx_bytes += skb->len;
- skb->protocol = eth_type_trans(skb, dev);
- /* pass the packet to upper layers */
- netif_rx(skb);
+ /* pass the packet to upper layers */
+ sp->rx(skb);
skb_new->dev = dev;
+
/* 16 bit align */
- skb_reserve(skb_new, RX_OFFSET);
+ offset = RX_OFFSET;
+ if (sp->phy_dev)
+ offset += sp->phy_dev->pkt_align;
+ skb_reserve(skb_new, offset);
/* reset descriptor's curr_addr */
rxdesc->addr = virt_to_phys(skb_new->data);
@@ -1239,6 +1245,8 @@ static int ar231x_mdiobus_probe (struct
return PTR_ERR(phydev);
}
+ sp->rx = phydev->netif_rx;
+
/* mask with MAC supported features */
phydev->supported &= (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
--- a/drivers/net/ar231x.h
+++ b/drivers/net/ar231x.h
@@ -221,6 +221,8 @@ typedef struct {
*/
struct ar231x_private {
struct net_device *dev;
+ int (*rx)(struct sk_buff *skb);
+
int version;
u32 mb[2];

View File

@ -1,174 +0,0 @@
--- a/arch/mips/ar231x/Makefile
+++ b/arch/mips/ar231x/Makefile
@@ -8,7 +8,7 @@
# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
#
-obj-y += board.o prom.o devices.o
+obj-y += board.o prom.o devices.o reset.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
--- /dev/null
+++ b/arch/mips/ar231x/reset.c
@@ -0,0 +1,160 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/kobject.h>
+#include <linux/workqueue.h>
+#include <linux/skbuff.h>
+#include <linux/netlink.h>
+#include <net/sock.h>
+#include <asm/uaccess.h>
+#include <ar231x_platform.h>
+#include <ar231x.h>
+#include <gpio.h>
+#include "devices.h"
+
+#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio))
+
+struct event_t {
+ struct work_struct wq;
+ int set;
+ unsigned long jiffies;
+};
+
+static struct timer_list rst_button_timer;
+static unsigned long seen;
+
+extern struct sock *uevent_sock;
+extern u64 uevent_next_seqnum(void);
+
+static int no_release_workaround = 1;
+module_param(no_release_workaround, int, 0);
+
+static inline void
+add_msg(struct sk_buff *skb, char *msg)
+{
+ char *scratch;
+ scratch = skb_put(skb, strlen(msg) + 1);
+ sprintf(scratch, msg);
+}
+
+static void
+hotplug_button(struct work_struct *wq)
+{
+ struct sk_buff *skb;
+ struct event_t *event;
+ size_t len;
+ char *scratch, *s;
+ char buf[128];
+
+ event = container_of(wq, struct event_t, wq);
+ if (!uevent_sock)
+ goto done;
+
+ /* allocate message with the maximum possible size */
+ s = event->set ? "pressed" : "released";
+ len = strlen(s) + 2;
+ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL);
+ if (!skb)
+ goto done;
+
+ /* add header */
+ scratch = skb_put(skb, len);
+ sprintf(scratch, "%s@",s);
+
+ /* copy keys to our continuous event payload buffer */
+ add_msg(skb, "HOME=/");
+ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin");
+ add_msg(skb, "SUBSYSTEM=button");
+ add_msg(skb, "BUTTON=reset");
+ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released"));
+ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ);
+ add_msg(skb, buf);
+ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum());
+ add_msg(skb, buf);
+
+ NETLINK_CB(skb).dst_group = 1;
+ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL);
+
+done:
+ kfree(event);
+}
+
+static void
+reset_button_poll(unsigned long unused)
+{
+ struct event_t *event;
+ int gpio = ~0;
+
+ if(!no_release_workaround)
+ return;
+
+ gpio = ar231x_gpiodev->get();
+ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE));
+ if(gpio) {
+ rst_button_timer.expires = jiffies + (HZ / 4);
+ add_timer(&rst_button_timer);
+ return;
+ }
+
+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
+ if (!event)
+ return;
+
+ event->set = 0;
+ event->jiffies = jiffies;
+ INIT_WORK(&event->wq, hotplug_button);
+ schedule_work(&event->wq);
+}
+
+static irqreturn_t
+button_handler(int irq, void *dev_id)
+{
+ static int pressed = 0;
+ struct event_t *event;
+ u32 gpio = ~0;
+
+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
+ if (!event)
+ return IRQ_NONE;
+
+ pressed = !pressed;
+
+ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE));
+
+ event->set = gpio;
+ if(!event->set)
+ no_release_workaround = 0;
+
+ event->jiffies = jiffies;
+
+ INIT_WORK(&event->wq, hotplug_button);
+ schedule_work(&event->wq);
+
+ seen = jiffies;
+ if(event->set && no_release_workaround)
+ mod_timer(&rst_button_timer, jiffies + (HZ / 4));
+
+ return IRQ_HANDLED;
+}
+
+
+static int __init
+ar231x_init_reset(void)
+{
+ seen = jiffies;
+
+ if (ar231x_board.config->resetConfigGpio == 0xffff)
+ return -ENODEV;
+
+ init_timer(&rst_button_timer);
+ rst_button_timer.function = reset_button_poll;
+ rst_button_timer.expires = jiffies + HZ / 50;
+ add_timer(&rst_button_timer);
+
+ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL);
+
+ return 0;
+}
+
+module_init(ar231x_init_reset);

View File

@ -1,69 +0,0 @@
--- a/drivers/net/ar231x.c
+++ b/drivers/net/ar231x.c
@@ -148,6 +148,7 @@ static int ar231x_mdiobus_write(struct m
static int ar231x_mdiobus_reset(struct mii_bus *bus);
static int ar231x_mdiobus_probe (struct net_device *dev);
static void ar231x_adjust_link(struct net_device *dev);
+static bool no_phy = false;
#ifndef ERR
#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
@@ -278,6 +279,21 @@ int __init ar231x_probe(struct platform_
mdiobus_register(sp->mii_bus);
+ /* Workaround for Micrel switch, which is only available on
+ * one PHY and cannot be configured through MDIO */
+ if (!no_phy) {
+ u32 phy_id = 0;
+ get_phy_id(sp->mii_bus, 1, &phy_id);
+ if (phy_id == 0x00221450)
+ no_phy = true;
+ }
+ if (no_phy) {
+ sp->link = 1;
+ netif_carrier_on(dev);
+ return 0;
+ }
+ no_phy = true;
+
if (ar231x_mdiobus_probe(dev) != 0) {
printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
rx_tasklet_cleanup(dev);
@@ -334,8 +350,10 @@ static int __exit ar231x_remove(struct p
rx_tasklet_cleanup(dev);
ar231x_init_cleanup(dev);
unregister_netdev(dev);
- mdiobus_unregister(sp->mii_bus);
- mdiobus_free(sp->mii_bus);
+ if (sp->mii_bus) {
+ mdiobus_unregister(sp->mii_bus);
+ mdiobus_free(sp->mii_bus);
+ }
kfree(dev);
return 0;
}
@@ -836,7 +854,12 @@ static int ar231x_rx_int(struct net_devi
dev->stats.rx_bytes += skb->len;
/* pass the packet to upper layers */
- sp->rx(skb);
+ if (sp->rx) {
+ sp->rx(skb);
+ } else {
+ skb->protocol = eth_type_trans(skb, skb->dev);
+ netif_rx(skb);
+ }
skb_new->dev = dev;
/* 16 bit align */
@@ -1123,6 +1146,9 @@ static int ar231x_ioctl(struct net_devic
struct ar231x_private *sp = netdev_priv(dev);
int ret;
+ if (!sp->phy_dev)
+ return -ENODEV;
+
switch (cmd) {
case SIOCETHTOOL:

View File

@ -1,208 +0,0 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
# CONFIG_AR7 is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_ARPD is not set
CONFIG_B44=y
CONFIG_B44_PCI=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_BCM47XX=y
CONFIG_BCM47XX_WDT=y
# CONFIG_BCM63XX is not set
CONFIG_BITREVERSE=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
CONFIG_CEVT_R4K=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CFE=y
CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_CPU_CAVIUM_OCTEON is not set
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_LOONGSON2E is not set
# CONFIG_CPU_LOONGSON2F is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CSRC_R4K=y
CONFIG_CSRC_R4K_LIB=y
CONFIG_DECOMPRESS_LZMA=y
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_FSNOTIFY is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
# CONFIG_HAMRADIO is not set
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_IP_ROUTE_VERBOSE is not set
CONFIG_IRQ_CPU=y
CONFIG_KALLSYMS=y
CONFIG_LEDS_GPIO=y
CONFIG_LOONGSON_UART_BASE=y
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_LOONGSON is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MIKROTIK_RB532 is not set
CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MTD_BCM47XX=y
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PHYLIB=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_POWERTV is not set
# CONFIG_PROC_KCORE is not set
CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
CONFIG_SSB=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_DEBUG=y
CONFIG_SSB_DRIVER_EXTIF=y
CONFIG_SSB_DRIVER_GIGE=y
CONFIG_SSB_DRIVER_MIPS=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_EMBEDDED=y
CONFIG_SSB_PCICORE_HOSTMODE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_SERIAL=y
CONFIG_SSB_SPROM=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
# CONFIG_TC35815 is not set
# CONFIG_TINY_RCU is not set
CONFIG_TRAD_SIGNALS=y
# CONFIG_TREE_PREEMPT_RCU is not set
CONFIG_TREE_RCU=y
CONFIG_USB_SUPPORT=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_ZONE_DMA_FLAG=0

View File

@ -1,25 +0,0 @@
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -325,6 +325,12 @@ config MTD_CFI_FLAGADM
Mapping for the Flaga digital module. If you don't have one, ignore
this setting.
+config MTD_BCM47XX
+ tristate "BCM47xx flash device"
+ depends on MIPS && MTD_CFI && BCM47XX
+ help
+ Support for the flash chips on the BCM947xx board.
+
config MTD_REDWOOD
tristate "CFI Flash devices mapped on IBM Redwood"
depends on MTD_CFI && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 )
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_MTD_PMC_MSP_EVM) += pmcms
obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
obj-$(CONFIG_MTD_SC520CDP) += sc520cdp.o

View File

@ -1,89 +0,0 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -205,7 +205,6 @@ config MIPS_MALTA
select I8259
select MIPS_BOARDS_GEN
select MIPS_BONITO64
- select MIPS_CPU_SCACHE
select PCI_GT64XXX_PCI0
select MIPS_MSC
select SWAP_IO_SPACE
@@ -1561,13 +1560,6 @@ config IP22_CPU_SCACHE
bool
select BOARD_SCACHE
-#
-# Support for a MIPS32 / MIPS64 style S-caches
-#
-config MIPS_CPU_SCACHE
- bool
- select BOARD_SCACHE
-
config R5000_CPU_SCACHE
bool
select BOARD_SCACHE
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -759,6 +759,8 @@ static inline void cpu_probe_mips(struct
case PRID_IMP_25KF:
c->cputype = CPU_25KF;
__cpu_name[cpu] = "MIPS 25Kc";
+ /* Probe for L2 cache */
+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_34K:
c->cputype = CPU_34K;
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -33,6 +33,5 @@ obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-oct
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
EXTRA_CFLAGS += -Werror
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1148,7 +1148,6 @@ static void __init loongson2_sc_init(voi
extern int r5k_sc_init(void);
extern int rm7k_sc_init(void);
-extern int mips_sc_init(void);
static void __cpuinit setup_scache(void)
{
@@ -1202,29 +1201,17 @@ static void __cpuinit setup_scache(void)
#endif
default:
- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
- c->isa_level == MIPS_CPU_ISA_M32R2 ||
- c->isa_level == MIPS_CPU_ISA_M64R1 ||
- c->isa_level == MIPS_CPU_ISA_M64R2) {
-#ifdef CONFIG_MIPS_CPU_SCACHE
- if (mips_sc_init ()) {
- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
- scache_size >> 10,
- way_string[c->scache.ways], c->scache.linesz);
- }
-#else
- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
-#endif
- return;
- }
sc_present = 0;
}
if (!sc_present)
return;
+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+
/* compute a couple of other cache variables */
c->scache.waysize = scache_size / c->scache.ways;

View File

@ -1,367 +0,0 @@
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -17,6 +17,20 @@
#include <asm/cpu-features.h>
#include <asm/mipsmtregs.h>
+#ifdef CONFIG_BCM47XX
+#include <asm/paccess.h>
+#include <linux/ssb/ssb.h>
+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
+
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
+#else
+#define BCM4710_DUMMY_RREG()
+
+#define BCM4710_FILL_TLB(addr)
+#define BCM4710_PROTECTED_FILL_TLB(addr)
+#endif
+
/*
* This macro return a properly sign-extended address suitable as base address
* for indexed cache operations. Two issues here:
@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__dflush_prologue
+ BCM4710_DUMMY_RREG();
cache_op(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
static inline void flush_dcache_line(unsigned long addr)
{
__dflush_prologue
+ BCM4710_DUMMY_RREG();
cache_op(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
static inline void invalidate_dcache_line(unsigned long addr)
{
__dflush_prologue
+ BCM4710_DUMMY_RREG();
cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
*/
static inline void protected_flush_icache_line(unsigned long addr)
{
+ BCM4710_DUMMY_RREG();
protected_cache_op(Hit_Invalidate_I, addr);
}
@@ -219,6 +237,7 @@ static inline void protected_flush_icach
*/
static inline void protected_writeback_dcache_line(unsigned long addr)
{
+ BCM4710_DUMMY_RREG();
protected_cache_op(Hit_Writeback_Inv_D, addr);
}
@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
: "r" (base), \
"i" (op));
+static inline void blast_dcache(void)
+{
+ unsigned long start = KSEG0;
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
+ unsigned long end = (start + dcache_size);
+
+ do {
+ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, start);
+ start += current_cpu_data.dcache.linesz;
+ } while(start < end);
+}
+
+static inline void blast_dcache_page(unsigned long page)
+{
+ unsigned long start = page;
+ unsigned long end = start + PAGE_SIZE;
+
+ BCM4710_FILL_TLB(start);
+ do {
+ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Writeback_Inv_D, start);
+ start += current_cpu_data.dcache.linesz;
+ } while(start < end);
+}
+
+static inline void blast_dcache_page_indexed(unsigned long page)
+{
+ unsigned long start = page;
+ unsigned long end = start + PAGE_SIZE;
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
+ current_cpu_data.dcache.waybit;
+ unsigned long ws, addr;
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
+ start = page + ws;
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
+ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, addr);
+ }
+ }
+}
+
+
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
static inline void blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
\
__##pfx##flush_prologue \
\
+ war \
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws, indexop); \
@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
\
__##pfx##flush_prologue \
\
+ war \
do { \
cache##lsize##_unroll32(start, hitop); \
start += lsize * 32; \
@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
+ war \
+ \
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
@@ -393,36 +460,38 @@ static inline void blast_##pfx##cache##l
__##pfx##flush_epilogue \
}
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
-
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
/* build blast_xxx_range, protected_blast_xxx_range */
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
unsigned long end) \
{ \
unsigned long lsize = cpu_##desc##_line_size(); \
unsigned long addr = start & ~(lsize - 1); \
unsigned long aend = (end - 1) & ~(lsize - 1); \
+ war \
\
__##pfx##flush_prologue \
\
while (1) { \
+ war2 \
prot##cache_op(hitop, addr); \
if (addr == aend) \
break; \
@@ -432,13 +501,13 @@ static inline void prot##blast_##pfx##ca
__##pfx##flush_epilogue \
}
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
/* blast_inv_dcache_range */
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
#endif /* _ASM_R4KCACHE_H */
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -430,6 +430,10 @@
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
.set mips3
+#ifdef CONFIG_BCM47XX
+ nop
+ nop
+#endif
eret
.set mips0
.endm
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -52,6 +52,10 @@ NESTED(except_vec1_generic, 0, sp)
NESTED(except_vec3_generic, 0, sp)
.set push
.set noat
+#ifdef CONFIG_BCM47XX
+ nop
+ nop
+#endif
#if R5432_CP0_INTERRUPT_WAR
mfc0 k0, CP0_INDEX
#endif
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -35,6 +35,9 @@
#include <asm/cacheflush.h> /* for run_uncached() */
+/* For enabling BCM4710 cache workarounds */
+int bcm4710 = 0;
+
/*
* Special Variant of smp_call_function for use by cache functions:
*
@@ -111,6 +114,9 @@ static void __cpuinit r4k_blast_dcache_p
{
unsigned long dc_lsize = cpu_dcache_line_size();
+ if (bcm4710)
+ r4k_blast_dcache_page = blast_dcache_page;
+ else
if (dc_lsize == 0)
r4k_blast_dcache_page = (void *)cache_noop;
else if (dc_lsize == 16)
@@ -127,6 +133,9 @@ static void __cpuinit r4k_blast_dcache_p
{
unsigned long dc_lsize = cpu_dcache_line_size();
+ if (bcm4710)
+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
+ else
if (dc_lsize == 0)
r4k_blast_dcache_page_indexed = (void *)cache_noop;
else if (dc_lsize == 16)
@@ -143,6 +152,9 @@ static void __cpuinit r4k_blast_dcache_s
{
unsigned long dc_lsize = cpu_dcache_line_size();
+ if (bcm4710)
+ r4k_blast_dcache = blast_dcache;
+ else
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
@@ -680,6 +692,8 @@ static void local_r4k_flush_cache_sigtra
unsigned long addr = (unsigned long) arg;
R4600_HIT_CACHEOP_WAR_IMPL;
+ BCM4710_PROTECTED_FILL_TLB(addr);
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
if (dc_lsize)
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
if (!cpu_icache_snoops_remote_store && scache_size)
@@ -1298,6 +1312,17 @@ static void __cpuinit coherency_setup(vo
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
+ case CPU_BCM3302:
+ {
+ u32 cm;
+ cm = read_c0_diag();
+ /* Enable icache */
+ cm |= (1 << 31);
+ /* Enable dcache */
+ cm |= (1 << 30);
+ write_c0_diag(cm);
+ }
+ break;
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
@@ -1354,6 +1379,15 @@ void __cpuinit r4k_cache_init(void)
break;
}
+ /* Check if special workarounds are required */
+#ifdef CONFIG_BCM47XX
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
+ printk("Enabling BCM4710A0 cache workarounds.\n");
+ bcm4710 = 1;
+ } else
+#endif
+ bcm4710 = 0;
+
probe_pcache();
setup_scache();
@@ -1412,5 +1446,13 @@ void __cpuinit r4k_cache_init(void)
#if !defined(CONFIG_MIPS_CMP)
local_r4k___flush_cache_all(NULL);
#endif
+#ifdef CONFIG_BCM47XX
+ {
+ static void (*_coherency_setup)(void);
+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
+ _coherency_setup();
+ }
+#else
coherency_setup();
+#endif
}
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -749,6 +749,9 @@ static void __cpuinit build_r4000_tlb_re
/* No need for uasm_i_nop */
}
+#ifdef CONFIG_BCM47XX
+ uasm_i_nop(&p);
+#endif
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
@@ -1203,6 +1206,9 @@ build_r4000_tlbchange_handler_head(u32 *
struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{
+#ifdef CONFIG_BCM47XX
+ uasm_i_nop(p);
+#endif
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
#else

View File

@ -1,77 +0,0 @@
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -107,6 +107,9 @@
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
+#ifndef cpu_use_kmap_coherent
+#define cpu_use_kmap_coherent 1
+#endif
/*
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_use_kmap_coherent 0
+
+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -507,7 +507,7 @@ static inline void local_r4k_flush_cache
*/
map_coherent = (cpu_has_dc_aliases &&
page_mapped(page) && !Page_dcache_dirty(page));
- if (map_coherent)
+ if (map_coherent && cpu_use_kmap_coherent)
vaddr = kmap_coherent(page, addr);
else
vaddr = kmap_atomic(page, KM_USER0);
@@ -530,7 +530,7 @@ static inline void local_r4k_flush_cache
}
if (vaddr) {
- if (map_coherent)
+ if (map_coherent && cpu_use_kmap_coherent)
kunmap_coherent();
else
kunmap_atomic(vaddr, KM_USER0);
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -209,7 +209,7 @@ void copy_user_highpage(struct page *to,
void *vfrom, *vto;
vto = kmap_atomic(to, KM_USER1);
- if (cpu_has_dc_aliases &&
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
page_mapped(from) && !Page_dcache_dirty(from)) {
vfrom = kmap_coherent(from, vaddr);
copy_page(vto, vfrom);
@@ -231,7 +231,7 @@ void copy_to_user_page(struct vm_area_st
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
- if (cpu_has_dc_aliases &&
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
page_mapped(page) && !Page_dcache_dirty(page)) {
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(vto, src, len);
@@ -249,7 +249,7 @@ void copy_from_user_page(struct vm_area_
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
- if (cpu_has_dc_aliases &&
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
page_mapped(page) && !Page_dcache_dirty(page)) {
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(dst, vfrom, len);

View File

@ -1,45 +0,0 @@
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -126,6 +126,7 @@ static __init void prom_init_cmdline(voi
static __init void prom_init_mem(void)
{
unsigned long mem;
+ unsigned long max;
/* Figure out memory size by finding aliases.
*
@@ -134,21 +135,26 @@ static __init void prom_init_mem(void)
* want to reuse the memory used by CFE (around 4MB). That means cfe_*
* functions stop to work at some point during the boot, we should only
* call them at the beginning of the boot.
+ *
+ * BCM47XX uses 128MB for addressing the ram, if the system contains
+ * less that that amount of ram it remaps the ram more often into the
+ * available space.
+ * Accessing memory after 128MB will cause an exception.
+ * max contains the biggest possible address supported by the platform.
+ * If the method wants to try something above we assume 128MB ram.
*/
+ max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
+ if (((unsigned long)(prom_init) + mem) > max) {
+ mem = (128 << 20);
+ printk("assume 128MB RAM\n");
+ break;
+ }
if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
*(unsigned long *)(prom_init))
break;
}
- /* Ignoring the last page when ddr size is 128M. Cached
- * accesses to last page is causing the processor to prefetch
- * using address above 128M stepping out of the ddr address
- * space.
- */
- if (mem == 0x8000000)
- mem -= 0x1000;
-
add_memory_region(0, mem, BOOT_MEM_RAM);
}

View File

@ -1,36 +0,0 @@
From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
From: Jochen Friedrich <jochen@scram.de>
Date: Wed, 3 Feb 2010 21:28:11 +0100
Subject: [PATCH 1/1] ssb: fix interrupt assignment
Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
Also remove a bogus comment.
Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---
drivers/ssb/driver_mipscore.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
set_irq(dev, irq++);
}
break;
- /* fallthrough */
case SSB_DEV_PCI:
case SSB_DEV_ETHERNET:
case SSB_DEV_ETHERNET_GBIT:
@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
set_irq(dev, irq++);
break;
}
+ /* fallthrough */
+ case SSB_DEV_EXTIF:
+ set_irq(dev, 0);
+ break;
}
}
ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");

View File

@ -1,22 +0,0 @@
--- a/drivers/net/b44.c
+++ b/drivers/net/b44.c
@@ -339,7 +339,7 @@ static int b44_phy_reset(struct b44 *bp)
}
}
- return 0;
+ return err;
}
static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
@@ -2223,6 +2223,10 @@ static int __devinit b44_init_one(struct
*/
b44_chip_reset(bp, B44_CHIP_RESET_FULL);
+ /* do a phy reset to test if there is an active phy */
+ if (b44_phy_reset(bp) < 0)
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
+
printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
dev->name, dev->dev_addr);

View File

@ -1,42 +0,0 @@
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
+ return;
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
switch (*plltype) {
@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
u32 *plltype, u32 *n, u32 *m)
{
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
+ return;
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
switch (*plltype) {
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -217,6 +217,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
rate = 200000000;
+ } else if (bus->chip_id == 0x5354) {
+ rate = 240000000;
} else {
rate = ssb_calc_clock_rate(pll_type, n, m);
}
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -1069,6 +1069,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
if (bus->chip_id == 0x5365) {
rate = 100000000;
+ } else if (bus->chip_id == 0x5354) {
+ rate = 120000000;
} else {
rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */

View File

@ -1,60 +0,0 @@
---
drivers/usb/host/ohci-ssb.c | 39 ++++++++++++++++++++++++++++++++++++---
1 file changed, 36 insertions(+), 3 deletions(-)
--- a/drivers/usb/host/ohci-ssb.c
+++ b/drivers/usb/host/ohci-ssb.c
@@ -106,10 +106,42 @@ static int ssb_ohci_attach(struct ssb_de
int err = -ENOMEM;
u32 tmp, flags = 0;
- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
+ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
+ /* Put the device into host-mode. */
flags |= SSB_OHCI_TMSLOW_HOSTMODE;
-
- ssb_device_enable(dev, flags);
+ ssb_device_enable(dev, flags);
+ } else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
+ /*
+ * USB 2.0 special considerations:
+ *
+ * 1. Since the core supports both OHCI and EHCI functions, it must
+ * only be reset once.
+ *
+ * 2. In addition to the standard SSB reset sequence, the Host Control
+ * Register must be programmed to bring the USB core and various
+ * phy components out of reset.
+ */
+ ssb_device_enable(dev, 0);
+ ssb_write32(dev, 0x200, 0x7ff);
+ udelay(1);
+ if (dev->id.revision == 1) { // bug in rev 1
+
+ /* Change Flush control reg */
+ tmp = ssb_read32(dev, 0x400);
+ tmp &= ~8;
+ ssb_write32(dev, 0x400, tmp);
+ tmp = ssb_read32(dev, 0x400);
+ printk("USB20H fcr: 0x%0x\n", tmp);
+
+ /* Change Shim control reg */
+ tmp = ssb_read32(dev, 0x304);
+ tmp &= ~0x100;
+ ssb_write32(dev, 0x304, tmp);
+ tmp = ssb_read32(dev, 0x304);
+ printk("USB20H shim: 0x%0x\n", tmp);
+ }
+ } else
+ ssb_device_enable(dev, 0);
hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
dev_name(dev->dev));
@@ -200,6 +232,7 @@ static int ssb_ohci_resume(struct ssb_de
static const struct ssb_device_id ssb_ohci_table[] = {
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
SSB_DEVTABLE_END
};
MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);

View File

@ -1,16 +0,0 @@
---
drivers/usb/host/ohci-ssb.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/usb/host/ohci-ssb.c
+++ b/drivers/usb/host/ohci-ssb.c
@@ -106,6 +106,9 @@ static int ssb_ohci_attach(struct ssb_de
int err = -ENOMEM;
u32 tmp, flags = 0;
+ if (ssb_dma_set_mask(dev, DMA_BIT_MASK(32)))
+ return -EOPNOTSUPP;
+
if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
/* Put the device into host-mode. */
flags |= SSB_OHCI_TMSLOW_HOSTMODE;

View File

@ -1,314 +0,0 @@
---
drivers/usb/host/Kconfig | 13 ++
drivers/usb/host/ehci-hcd.c | 12 ++
drivers/usb/host/ehci-ssb.c | 201 ++++++++++++++++++++++++++++++++++++++++++++
drivers/usb/host/ohci-ssb.c | 23 +++++
4 files changed, 247 insertions(+), 2 deletions(-)
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -150,6 +150,19 @@ config USB_OXU210HP_HCD
To compile this driver as a module, choose M here: the
module will be called oxu210hp-hcd.
+config USB_EHCI_HCD_SSB
+ bool "EHCI support for Broadcom SSB EHCI core"
+ depends on USB_EHCI_HCD && SSB && EXPERIMENTAL
+ default n
+ ---help---
+ Support for the Sonics Silicon Backplane (SSB) attached
+ Broadcom USB EHCI core.
+
+ This device is present in some embedded devices with
+ Broadcom based SSB bus.
+
+ If unsure, say N.
+
config USB_ISP116X_HCD
tristate "ISP116X HCD support"
depends on USB
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1158,8 +1158,16 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ehci_atmel_driver
#endif
-#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
- !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+#include "ehci-ssb.c"
+#define SSB_EHCI_DRIVER ssb_ehci_driver
+#endif
+
+#if !defined(PCI_DRIVER) && \
+ !defined(PLATFORM_DRIVER) && \
+ !defined(PS3_SYSTEM_BUS_DRIVER) && \
+ !defined(OF_PLATFORM_DRIVER) && \
+ !defined(SSB_EHCI_DRIVER)
#error "missing bus glue for ehci-hcd"
#endif
--- /dev/null
+++ b/drivers/usb/host/ehci-ssb.c
@@ -0,0 +1,201 @@
+/*
+ * Sonics Silicon Backplane
+ * Broadcom USB-core EHCI driver (SSB bus glue)
+ *
+ * Copyright 2007 Steven Brown <sbrown@cortland.com>
+ *
+ * Derived from the OHCI-SSB driver
+ * Copyright 2007 Michael Buesch <mb@bu3sch.de>
+ *
+ * Derived from the EHCI-PCI driver
+ * Copyright (c) 2000-2004 by David Brownell
+ *
+ * Derived from the OHCI-PCI driver
+ * Copyright 1999 Roman Weissgaerber
+ * Copyright 2000-2002 David Brownell
+ * Copyright 1999 Linus Torvalds
+ * Copyright 1999 Gregory P. Smith
+ *
+ * Derived from the USBcore related parts of Broadcom-SB
+ * Copyright 2005 Broadcom Corporation
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include <linux/ssb/ssb.h>
+
+#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29)
+
+struct ssb_ehci_device {
+ struct ehci_hcd ehci; /* _must_ be at the beginning. */
+
+ u32 enable_flags;
+};
+
+static inline
+struct ssb_ehci_device *hcd_to_ssb_ehci(struct usb_hcd *hcd)
+{
+ return (struct ssb_ehci_device *)(hcd->hcd_priv);
+}
+
+
+static int ssb_ehci_reset(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ int err;
+
+ ehci->caps = hcd->regs;
+ ehci->regs = hcd->regs +
+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+
+ dbg_hcs_params(ehci, "reset");
+ dbg_hcc_params(ehci, "reset");
+
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+ err = ehci_halt(ehci);
+
+ if (err)
+ return err;
+
+ err = ehci_init(hcd);
+
+ if (err)
+ return err;
+
+ ehci_port_power(ehci, 0);
+
+ return err;
+}
+
+static int ssb_ehci_start(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ int err;
+
+ err = ehci_run(hcd);
+ if (err < 0) {
+ ehci_err(ehci, "can't start\n");
+ ehci_stop(hcd);
+ }
+
+ return err;
+}
+
+#ifdef CONFIG_PM
+static int ssb_ehci_hcd_suspend(struct usb_hcd *hcd, pm_message_t message)
+{
+ struct ssb_ehci_device *ehcidev = hcd_to_ssb_ehci(hcd);
+ struct ehci_hcd *ehci = &ehcidev->ehci;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ehci->lock, flags);
+
+ ehci_writel(ehci, EHCI_INTR_MIE, &ehci->regs->intrdisable);
+ ehci_readl(ehci, &ehci->regs->intrdisable); /* commit write */
+
+ /* make sure snapshot being resumed re-enumerates everything */
+ if (message.event == PM_EVENT_PRETHAW)
+ ehci_usb_reset(ehci);
+
+ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+ spin_unlock_irqrestore(&ehci->lock, flags);
+ return 0;
+}
+
+static int ssb_ehci_hcd_resume(struct usb_hcd *hcd)
+{
+ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+ usb_hcd_resume_root_hub(hcd);
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+static const struct hc_driver ssb_ehci_hc_driver = {
+ .description = "ssb-usb-ehci",
+ .product_desc = "SSB EHCI Controller",
+ .hcd_priv_size = sizeof(struct ssb_ehci_device),
+
+ .irq = ehci_irq,
+ .flags = HCD_MEMORY | HCD_USB2,
+
+ .reset = ssb_ehci_reset,
+ .start = ssb_ehci_start,
+ .stop = ehci_stop,
+ .shutdown = ehci_shutdown,
+
+#ifdef CONFIG_PM
+ .suspend = ssb_ehci_hcd_suspend,
+ .resume = ssb_ehci_hcd_resume,
+#endif
+
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+
+ .get_frame_number = ehci_get_frame,
+
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = ehci_hub_control,
+#ifdef CONFIG_PM
+ .bus_suspend = ehci_bus_suspend,
+ .bus_resume = ehci_bus_resume,
+#endif
+
+};
+
+static void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd)
+{
+
+ usb_remove_hcd(hcd);
+ iounmap(hcd->regs);
+ usb_put_hcd(hcd);
+}
+EXPORT_SYMBOL_GPL(ssb_ehci_detach);
+
+static int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **ehci_hcd)
+{
+ struct ssb_ehci_device *ehcidev;
+ struct usb_hcd *hcd;
+ int err = -ENOMEM;
+ u32 tmp, flags = 0;
+
+ hcd = usb_create_hcd(&ssb_ehci_hc_driver, dev->dev,
+ dev_name(dev->dev));
+ if (!hcd)
+ goto err_dev_disable;
+
+ ehcidev = hcd_to_ssb_ehci(hcd);
+ ehcidev->enable_flags = flags;
+ tmp = ssb_read32(dev, SSB_ADMATCH0);
+ hcd->rsrc_start = ssb_admatch_base(tmp) + 0x800; /* ehci core offset */
+ hcd->rsrc_len = 0x100; /* ehci reg block size */
+ /*
+ * start & size modified per sbutils.c
+ */
+ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs)
+ goto err_put_hcd;
+ err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED | IRQF_DISABLED);
+ if (err)
+ goto err_iounmap;
+
+ *ehci_hcd = hcd;
+
+ return err;
+
+err_iounmap:
+ iounmap(hcd->regs);
+err_put_hcd:
+ usb_put_hcd(hcd);
+err_dev_disable:
+ ssb_device_disable(dev, flags);
+ return err;
+}
+EXPORT_SYMBOL_GPL(ssb_ehci_attach);
+
+static const struct ssb_device_id ssb_ehci_table[] = {
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
+ SSB_DEVTABLE_END
+};
+MODULE_DEVICE_TABLE(ssb, ssb_ehci_table);
--- a/drivers/usb/host/ohci-ssb.c
+++ b/drivers/usb/host/ohci-ssb.c
@@ -17,6 +17,8 @@
*/
#include <linux/ssb/ssb.h>
+extern int ssb_ehci_attach(struct ssb_device *dev, struct usb_hcd **hcd);
+extern void ssb_ehci_detach(struct ssb_device *dev, struct usb_hcd *hcd);
#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29)
@@ -24,6 +26,7 @@ struct ssb_ohci_device {
struct ohci_hcd ohci; /* _must_ be at the beginning. */
u32 enable_flags;
+ struct usb_hcd *ehci_hcd;
};
static inline
@@ -92,13 +95,25 @@ static const struct hc_driver ssb_ohci_h
static void ssb_ohci_detach(struct ssb_device *dev)
{
struct usb_hcd *hcd = ssb_get_drvdata(dev);
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
+#endif
usb_remove_hcd(hcd);
iounmap(hcd->regs);
usb_put_hcd(hcd);
+
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+ /*
+ * Also detach ehci function
+ */
+ if (dev->id.coreid == SSB_DEV_USB20_HOST)
+ ssb_ehci_detach(dev, ohcidev->ehci_hcd);
+#endif
ssb_device_disable(dev, 0);
}
+
static int ssb_ohci_attach(struct ssb_device *dev)
{
struct ssb_ohci_device *ohcidev;
@@ -165,6 +180,14 @@ static int ssb_ohci_attach(struct ssb_de
ssb_set_drvdata(dev, hcd);
+#ifdef CONFIG_USB_EHCI_HCD_SSB
+ /*
+ * attach ehci function in this core
+ */
+ if (dev->id.coreid == SSB_DEV_USB20_HOST)
+ err = ssb_ehci_attach(dev, &(ohcidev->ehci_hcd));
+#endif
+
return err;
err_iounmap:

View File

@ -1,63 +0,0 @@
This patch significantly improves the reliability of high speed
usb writes on the bcm5354. It implements a work around for version 2
of the usb20 core that was cribbed from the GPL sources for the
Asus wl500gpv2 and verified against the wl520gu sources.
Reference:
GPL/WL-520gu-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
GPL/WL-500gPV2-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
Signed-off-by: Steve Brown <sbrown@cortland.com>
---
drivers/usb/host/ohci-ssb.c | 37 +++++++++++++++++++++++--------------
1 file changed, 23 insertions(+), 14 deletions(-)
--- a/drivers/usb/host/ohci-ssb.c
+++ b/drivers/usb/host/ohci-ssb.c
@@ -141,22 +141,31 @@ static int ssb_ohci_attach(struct ssb_de
*/
ssb_device_enable(dev, 0);
ssb_write32(dev, 0x200, 0x7ff);
+
+ /* Change Flush control reg */
+ tmp = ssb_read32(dev, 0x400);
+ tmp &= ~8;
+ ssb_write32(dev, 0x400, tmp);
+ tmp = ssb_read32(dev, 0x400);
+
+ /* Change Shim control reg */
+ tmp = ssb_read32(dev, 0x304);
+ tmp &= ~0x100;
+ ssb_write32(dev, 0x304, tmp);
+ tmp = ssb_read32(dev, 0x304);
+
udelay(1);
- if (dev->id.revision == 1) { // bug in rev 1
- /* Change Flush control reg */
- tmp = ssb_read32(dev, 0x400);
- tmp &= ~8;
- ssb_write32(dev, 0x400, tmp);
- tmp = ssb_read32(dev, 0x400);
- printk("USB20H fcr: 0x%0x\n", tmp);
-
- /* Change Shim control reg */
- tmp = ssb_read32(dev, 0x304);
- tmp &= ~0x100;
- ssb_write32(dev, 0x304, tmp);
- tmp = ssb_read32(dev, 0x304);
- printk("USB20H shim: 0x%0x\n", tmp);
+ /* Work around for 5354 failures */
+ if ((dev->id.revision == 2) && (dev->bus->chip_id == 0x5354)) {
+ /* Change syn01 reg */
+ tmp = 0x00fe00fe;
+ ssb_write32(dev, 0x894, tmp);
+
+ /* Change syn03 reg */
+ tmp = ssb_read32(dev, 0x89c);
+ tmp |= 0x1;
+ ssb_write32(dev, 0x89c, tmp);
}
} else
ssb_device_enable(dev, 0);

View File

@ -1,16 +0,0 @@
This prevents the options from being delete with make kernel_oldconfig.
---
drivers/ssb/Kconfig | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/ssb/Kconfig
+++ b/drivers/ssb/Kconfig
@@ -140,6 +140,8 @@ config SSB_DRIVER_MIPS
config SSB_EMBEDDED
bool
depends on SSB_DRIVER_MIPS
+ select USB_EHCI_HCD_SSB if USB_EHCI_HCD
+ select USB_OHCI_HCD_SSB if USB_OHCI_HCD
default y
config SSB_DRIVER_EXTIF

View File

@ -1,11 +0,0 @@
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -32,7 +32,7 @@
extern void (*flush_cache_all)(void);
extern void (*__flush_cache_all)(void);
extern void (*flush_cache_mm)(struct mm_struct *mm);
-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
extern void (*flush_cache_range)(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);

View File

@ -1,31 +0,0 @@
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -373,7 +373,7 @@ static inline void local_r4k___flush_cac
}
}
-static void r4k___flush_cache_all(void)
+void r4k___flush_cache_all(void)
{
r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
}
@@ -537,7 +537,7 @@ static inline void local_r4k_flush_cache
}
}
-static void r4k_flush_cache_page(struct vm_area_struct *vma,
+void r4k_flush_cache_page(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn)
{
struct flush_cache_page_args args;
@@ -1456,3 +1456,10 @@ void __cpuinit r4k_cache_init(void)
coherency_setup();
#endif
}
+
+// fuse package DCACHE BUG patch exports
+void (*fuse_flush_cache_all)(void) = r4k___flush_cache_all;
+void (*fuse_flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
+ unsigned long pfn) = r4k_flush_cache_page;
+EXPORT_SYMBOL(fuse_flush_cache_page);
+EXPORT_SYMBOL(fuse_flush_cache_all);

View File

@ -1,82 +0,0 @@
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -533,6 +533,11 @@ static void fuse_copy_finish(struct fuse
}
}
+#ifdef DCACHE_BUG
+extern void (*fuse_flush_cache_all)(void);
+extern void (*fuse_flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
+#endif
+
/*
* Get another pagefull of userspace buffer, and map it to kernel
* address space, and lock request
@@ -541,6 +546,9 @@ static int fuse_copy_fill(struct fuse_co
{
unsigned long offset;
int err;
+#ifdef DCACHE_BUG
+ struct vm_area_struct *vma;
+#endif
unlock_request(cs->fc, cs->req);
fuse_copy_finish(cs);
@@ -552,14 +560,22 @@ static int fuse_copy_fill(struct fuse_co
cs->nr_segs--;
}
down_read(&current->mm->mmap_sem);
+#ifndef DCACHE_BUG
err = get_user_pages(current, current->mm, cs->addr, 1, cs->write, 0,
&cs->pg, NULL);
+#else
+ err = get_user_pages(current, current->mm, cs->addr, 1, cs->write, 0,
+ &cs->pg, &vma);
+#endif
up_read(&current->mm->mmap_sem);
if (err < 0)
return err;
BUG_ON(err != 1);
offset = cs->addr % PAGE_SIZE;
cs->mapaddr = kmap_atomic(cs->pg, KM_USER0);
+#ifdef DCACHE_BUG
+ fuse_flush_cache_page(vma, cs->addr, page_to_pfn(cs->pg));
+#endif
cs->buf = cs->mapaddr + offset;
cs->len = min(PAGE_SIZE - offset, cs->seglen);
cs->seglen -= cs->len;
@@ -573,6 +589,11 @@ static int fuse_copy_do(struct fuse_copy
{
unsigned ncpy = min(*size, cs->len);
if (val) {
+#ifdef DCACHE_BUG
+ // patch from mailing list, it is very important, otherwise,
+ // can't mount, or ls mount point will hang
+ fuse_flush_cache_all();
+#endif
if (cs->write)
memcpy(cs->buf, *val, ncpy);
else
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -8,6 +8,7 @@
#ifndef _FS_FUSE_I_H
#define _FS_FUSE_I_H
+#define DCACHE_BUG
#include <linux/fuse.h>
#include <linux/fs.h>
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -1201,6 +1201,10 @@ static int __init fuse_init(void)
printk(KERN_INFO "fuse init (API version %i.%i)\n",
FUSE_KERNEL_VERSION, FUSE_KERNEL_MINOR_VERSION);
+#ifdef DCACHE_BUG
+printk("fuse init: DCACHE_BUG enabled\n");
+#endif
+
INIT_LIST_HEAD(&fuse_conn_list);
res = fuse_fs_init();
if (res)

View File

@ -1,66 +0,0 @@
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -43,6 +43,7 @@
#ifndef __ASSEMBLY__
#include <linux/pfn.h>
+#include <asm/cpu-features.h>
#include <asm/io.h>
extern void build_clear_page(void);
@@ -78,13 +79,16 @@ static inline void clear_user_page(void
flush_data_cache_page((unsigned long)addr);
}
-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
- struct page *to);
-struct vm_area_struct;
-extern void copy_user_highpage(struct page *to, struct page *from,
- unsigned long vaddr, struct vm_area_struct *vma);
+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+ struct page *to)
+{
+ extern void (*flush_data_cache_page)(unsigned long addr);
-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+ copy_page(vto, vfrom);
+ if (!cpu_has_ic_fills_f_dc ||
+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+ flush_data_cache_page((unsigned long)vto);
+}
/*
* These are used to make use of C type-checking..
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -203,30 +203,6 @@ void kunmap_coherent(void)
preempt_check_resched();
}
-void copy_user_highpage(struct page *to, struct page *from,
- unsigned long vaddr, struct vm_area_struct *vma)
-{
- void *vfrom, *vto;
-
- vto = kmap_atomic(to, KM_USER1);
- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapped(from) && !Page_dcache_dirty(from)) {
- vfrom = kmap_coherent(from, vaddr);
- copy_page(vto, vfrom);
- kunmap_coherent();
- } else {
- vfrom = kmap_atomic(from, KM_USER0);
- copy_page(vto, vfrom);
- kunmap_atomic(vfrom, KM_USER0);
- }
- if ((!cpu_has_ic_fills_f_dc) ||
- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
- flush_data_cache_page((unsigned long)vto);
- kunmap_atomic(vto, KM_USER1);
- /* Make sure this page is cleared on other CPU's too before using it */
- smp_wmb();
-}
-
void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)

View File

@ -1,319 +0,0 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -62,6 +62,7 @@ config BCM47XX
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
select SSB_EMBEDDED
+ select SSB_B43_PCI_BRIDGE if PCI
select SSB_PCICORE_HOSTMODE if PCI
select GENERIC_GPIO
select SYS_HAS_EARLY_PRINTK
--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
@@ -3,4 +3,4 @@
# under Linux.
#
-obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
+obj-y := cfe_env.o gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
--- a/arch/mips/bcm47xx/irq.c
+++ b/arch/mips/bcm47xx/irq.c
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
+ * Copyright (C) 2008 Michael Buesch <mb@bu3sch.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -23,10 +24,19 @@
*/
#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pci.h>
+#include <linux/ssb/ssb.h>
+
#include <asm/irq_cpu.h>
+
+extern struct ssb_bus ssb_bcm47xx;
+
+
void plat_irq_dispatch(void)
{
u32 cause;
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -24,10 +24,10 @@
#include <asm/io.h>
#include <asm/uaccess.h>
-#include <nvram.h>
+#include "include/nvram.h"
#define MB * 1048576
-extern struct ssb_bus ssb;
+extern struct ssb_bus ssb_bcm47xx;
static char nvram_buf[NVRAM_SPACE];
static int cfe_env;
@@ -36,7 +36,7 @@ extern char *cfe_env_get(char *nv_buf, c
/* Probe for NVRAM header */
static void __init early_nvram_init(void)
{
- struct ssb_mipscore *mcore = &ssb.mipscore;
+ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
struct nvram_header *header;
int i;
u32 base, lim, off;
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -2,7 +2,7 @@
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
+ * Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -25,18 +25,28 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <linux/init.h>
#include <linux/types.h>
#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_embedded.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
-#include <bcm47xx.h>
#include <asm/fw/cfe/cfe_api.h>
+#include <linux/pm.h>
+
+#include "include/nvram.h"
struct ssb_bus ssb_bcm47xx;
EXPORT_SYMBOL(ssb_bcm47xx);
+extern void bcm47xx_pci_init(void);
+
static void bcm47xx_machine_restart(char *command)
{
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
@@ -56,7 +66,7 @@ static void bcm47xx_machine_halt(void)
cpu_relax();
}
-static void str2eaddr(char *str, char *dest)
+static void e_aton(char *str, char *dest)
{
int i = 0;
@@ -73,52 +83,142 @@ static void str2eaddr(char *str, char *d
}
}
-static int bcm47xx_get_invariants(struct ssb_bus *bus,
- struct ssb_init_invariants *iv)
+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
{
- char buf[100];
+ char *s;
- /* Fill boardinfo structure */
- memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
+ memset(sprom, 0xFF, sizeof(struct ssb_sprom));
- if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
- if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
- iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
- if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
- iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
-
- /* Fill sprom structure */
- memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
- iv->sprom.revision = 3;
-
- if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
- str2eaddr(buf, iv->sprom.et0mac);
- if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
- str2eaddr(buf, iv->sprom.et1mac);
- if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
- iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 10);
- if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
- iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 10);
- if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
- iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
- if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
- iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
+ sprom->revision = 1;
+ if ((s = nvram_get("il0macaddr")))
+ e_aton(s, sprom->il0mac);
+ if ((s = nvram_get("et0macaddr")))
+ e_aton(s, sprom->et0mac);
+ if ((s = nvram_get("et1macaddr")))
+ e_aton(s, sprom->et1mac);
+ if ((s = nvram_get("et0phyaddr")))
+ sprom->et0phyaddr = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("et1phyaddr")))
+ sprom->et1phyaddr = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("et0mdcport")))
+ sprom->et0mdcport = !!simple_strtoul(s, NULL, 10);
+ if ((s = nvram_get("et1mdcport")))
+ sprom->et1mdcport = !!simple_strtoul(s, NULL, 10);
+ if ((s = nvram_get("pa0b0")))
+ sprom->pa0b0 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0b1")))
+ sprom->pa0b1 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0b2")))
+ sprom->pa0b2 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1b0")))
+ sprom->pa1b0 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1b1")))
+ sprom->pa1b1 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1b2")))
+ sprom->pa1b2 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio0")))
+ sprom->gpio0 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio1")))
+ sprom->gpio1 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio2")))
+ sprom->gpio2 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("wl0gpio3")))
+ sprom->gpio3 = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0maxpwr")))
+ sprom->maxpwr_bg = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1maxpwr")))
+ sprom->maxpwr_a = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa0itssit")))
+ sprom->itssi_bg = simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("pa1itssit")))
+ sprom->itssi_a = simple_strtoul(s, NULL, 0);
+ sprom->boardflags_lo = 0;
+ if ((s = nvram_get("boardflags")))
+ sprom->boardflags_lo = simple_strtoul(s, NULL, 0);
+ sprom->boardflags_hi = 0;
+ if ((s = nvram_get("boardflags2")))
+ sprom->boardflags_hi = simple_strtoul(s, NULL, 0);
+}
+
+static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
+{
+ char *s;
+
+ iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
+ if ((s = nvram_get("boardtype")))
+ iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
+ if ((s = nvram_get("boardrev")))
+ iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
+
+ bcm47xx_fill_sprom(&iv->sprom);
+
+ if ((s = nvram_get("cardbus")))
+ iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10);
return 0;
}
void __init plat_mem_setup(void)
{
- int err;
+ int i, err;
+ char *s;
+ struct ssb_mipscore *mcore;
+
+ err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, bcm47xx_get_invariants);
+ if (err) {
+ const char *msg = "Failed to initialize SSB bus (err %d)\n";
+ printk(msg, err); /* Make sure the message gets out of the box. */
+ panic(msg, err);
+ }
+ mcore = &ssb_bcm47xx.mipscore;
- err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
- bcm47xx_get_invariants);
- if (err)
- panic("Failed to initialize SSB bus (err %d)\n", err);
+ s = nvram_get("kernel_args");
+ if (s && !strncmp(s, "console=ttyS1", 13)) {
+ struct ssb_serial_port port;
+
+ printk("Swapping serial ports!\n");
+ /* swap serial ports */
+ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
+ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
+ }
+
+ for (i = 0; i < mcore->nr_serial_ports; i++) {
+ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
+ struct uart_port s;
+
+ memset(&s, 0, sizeof(s));
+ s.line = i;
+ s.mapbase = (unsigned int) port->regs;
+ s.membase = port->regs;
+ s.irq = port->irq + 2;
+ s.uartclk = port->baud_base;
+ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+ s.iotype = SERIAL_IO_MEM;
+ s.regshift = port->reg_shift;
+
+ early_serial_setup(&s);
+ }
+ printk("Serial init done.\n");
_machine_restart = bcm47xx_machine_restart;
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;
}
+static int __init bcm47xx_register_gpiodev(void)
+{
+ static struct resource res = {
+ .start = 0xFFFFFFFF,
+ };
+ struct platform_device *pdev;
+
+ pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
+ if (!pdev) {
+ printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+device_initcall(bcm47xx_register_gpiodev);
--- a/arch/mips/bcm47xx/time.c
+++ b/arch/mips/bcm47xx/time.c
@@ -22,11 +22,17 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-
#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/serial_reg.h>
+#include <linux/interrupt.h>
#include <linux/ssb/ssb.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
#include <asm/time.h>
-#include <bcm47xx.h>
+
+extern struct ssb_bus ssb_bcm47xx;
void __init plat_time_init(void)
{

View File

@ -1,18 +0,0 @@
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -185,12 +185,10 @@ static int pcibios_enable_resources(stru
if ((idx == PCI_ROM_RESOURCE) &&
(!(r->flags & IORESOURCE_ROM_ENABLE)))
continue;
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available "
- "because of resource collisions\n",
+ if (!r->start && r->end)
+ printk(KERN_WARNING "PCI: Device %s resource"
+ "collisions detected. Ignoring...\n",
pci_name(dev));
- return -EINVAL;
- }
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)

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