qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00
Code Activity

[lantiq] cleanup patches

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32953 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
2012-08-03 08:53:02 +00:00
parent 6b899d5dea
commit cea2b4210d
209 changed files with 146978 additions and 82080 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
target/linux/lantiq/files/arch/mips/include/asm/clkdev.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* based on arch/arm/include/asm/clkdev.h
*
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#ifndef __ASM_CLKDEV_H
#define __ASM_CLKDEV_H
#include <linux/slab.h>
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{
return kzalloc(size, GFP_KERNEL);
}
#endif

268
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h Normal file
View File

@@ -0,0 +1,268 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
*/
#ifndef _FALCON_IRQ__
#define _FALCON_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define MIPS_CPU_TIMER_IRQ 7
/* HOST IF Event Interrupt */
#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0)
/* HOST IF Mailbox0 Receive Interrupt */
#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1)
/* HOST IF Mailbox0 Transmit Interrupt */
#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2)
/* HOST IF Mailbox1 Receive Interrupt */
#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3)
/* HOST IF Mailbox1 Transmit Interrupt */
#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4)
/* I2C Last Single Data Transfer Request */
#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8)
/* I2C Single Data Transfer Request */
#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9)
/* I2C Last Burst Data Transfer Request */
#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10)
/* I2C Burst Data Transfer Request */
#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11)
/* I2C Error Interrupt */
#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12)
/* I2C Protocol Interrupt */
#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13)
/* SSC Transmit Interrupt */
#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14)
/* SSC Receive Interrupt */
#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15)
/* SSC Error Interrupt */
#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16)
/* SSC Frame Interrupt */
#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17)
/* Advanced Encryption Standard Interrupt */
#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27)
/* Secure Hash Algorithm Interrupt */
#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28)
/* PCM Receive Interrupt */
#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29)
/* PCM Transmit Interrupt */
#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30)
/* PCM Transmit Crash Interrupt */
#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31)
/* EBU Serial Flash Command Error */
#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0)
/* EBU Serial Flash Command Overwrite Error */
#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1)
/* EBU Serial Flash Busy */
#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2)
/* External Interrupt from GPIO P0 */
#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4)
/* External Interrupt from GPIO P1 */
#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5)
/* External Interrupt from GPIO P2 */
#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6)
/* External Interrupt from GPIO P3 */
#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7)
/* External Interrupt from GPIO P4 */
#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8)
/* 8kHz backup interrupt derived from core-PLL */
#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10)
/* FSC Timer Interrupt 0 */
#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11)
/* FSC Timer Interrupt 1 */
#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12)
/* 8kHz root interrupt derived from GPON interface */
#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13)
/* Time of Day */
#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14)
/* PMA Interrupt from IntNode of the 200MHz Domain */
#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15)
/* PMA Interrupt from IntNode of the TX Clk Domain */
#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16)
/* PMA Interrupt from IntNode of the RX Clk Domain */
#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17)
/* SYS1 Interrupt */
#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20)
/* SYS GPE Interrupt */
#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21)
/* Watchdog Access Error Interrupt */
#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24)
/* Watchdog Prewarning Interrupt */
#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25)
/* SBIU interrupt */
#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27)
/* FPI Bus Control Unit Interrupt */
#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29)
/* DDR Controller Interrupt */
#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30)
/* Crossbar Error Interrupt */
#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31)
/* ICTRLL 0 Interrupt */
#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0)
/* ICTRLL 1 Interrupt */
#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1)
/* ICTRLL 2 Interrupt */
#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2)
/* ICTRLL 3 Interrupt */
#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3)
/* OCTRLL 0 Interrupt */
#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4)
/* OCTRLL 1 Interrupt */
#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5)
/* OCTRLL 2 Interrupt */
#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6)
/* OCTRLL 3 Interrupt */
#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7)
/* OCTRLG Interrupt */
#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9)
/* IQM Interrupt */
#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10)
/* FSQM Interrupt */
#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11)
/* TMU Interrupt */
#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12)
/* LINK1 Interrupt */
#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14)
/* ICTRLC 0 Interrupt */
#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16)
/* ICTRLC 1 Interrupt */
#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17)
/* OCTRLC Interrupt */
#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18)
/* CONFIG Break Interrupt */
#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19)
/* CONFIG Interrupt */
#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20)
/* Dispatcher Interrupt */
#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21)
/* TBM Interrupt */
#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22)
/* GTC Downstream Interrupt */
#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29)
/* GTC Upstream Interrupt */
#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30)
/* EIM Interrupt */
#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31)
/* ASC0 Transmit Interrupt */
#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0)
/* ASC0 Receive Interrupt */
#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1)
/* ASC0 Error Interrupt */
#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2)
/* ASC0 Transmit Buffer Interrupt */
#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3)
/* ASC0 Autobaud Start Interrupt */
#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4)
/* ASC0 Autobaud Detection Interrupt */
#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5)
/* ASC1 Modem Status Interrupt */
#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6)
/* ASC0 Soft Flow Control Interrupt */
#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7)
/* ASC1 Transmit Interrupt */
#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8)
/* ASC1 Receive Interrupt */
#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9)
/* ASC1 Error Interrupt */
#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10)
/* ASC1 Transmit Buffer Interrupt */
#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11)
/* ASC1 Autobaud Start Interrupt */
#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12)
/* ASC1 Autobaud Detection Interrupt */
#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13)
/* ASC1 Modem Status Interrupt */
#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14)
/* ASC1 Soft Flow Control Interrupt */
#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15)
/* GPTC Timer/Counter 1A Interrupt */
#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16)
/* GPTC Timer/Counter 1B Interrupt */
#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17)
/* GPTC Timer/Counter 2A Interrupt */
#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18)
/* GPTC Timer/Counter 2B Interrupt */
#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19)
/* GPTC Timer/Counter 3A Interrupt */
#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20)
/* GPTC Timer/Counter 3B Interrupt */
#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21)
/* DFEV0, Channel 1 Transmit Interrupt */
#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26)
/* DFEV0, Channel 1 Receive Interrupt */
#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27)
/* DFEV0, Channel 1 General Purpose Interrupt */
#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28)
/* DFEV0, Channel 0 Transmit Interrupt */
#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29)
/* DFEV0, Channel 0 Receive Interrupt */
#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30)
/* DFEV0, Channel 0 General Purpose Interrupt */
#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31)
/* ICTRLL 0 Error */
#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0)
/* ICTRLL 1 Error */
#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1)
/* ICTRLL 2 Error */
#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2)
/* ICTRLL 3 Error */
#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3)
/* OCTRLL 0 Error */
#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4)
/* OCTRLL 1 Error */
#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5)
/* OCTRLL 2 Error */
#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6)
/* OCTRLL 3 Error */
#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7)
/* ICTRLG Error */
#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8)
/* OCTRLG Error */
#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9)
/* IQM Error */
#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10)
/* FSQM Error */
#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11)
/* TMU Error */
#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12)
/* MPS Status Interrupt #0 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14)
/* MPS Status Interrupt #1 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15)
/* MPS Status Interrupt #2 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16)
/* MPS Status Interrupt #3 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17)
/* MPS Status Interrupt #4 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18)
/* MPS Status Interrupt #5 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19)
/* MPS Status Interrupt #6 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20)
/* MPS Status Interrupt #7 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21)
/* MPS Status Interrupt #8 (VPE1 to VPE0) */
#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22)
/* VPE0 Exception Level Flag Interrupt */
#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29)
/* VPE0 Error Level Flag Interrupt */
#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30)
/* VPE0 Performance Monitoring Counter Interrupt */
#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31)
#endif /* _FALCON_IRQ__ */

18
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h Normal file
View File

@@ -0,0 +1,18 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
*/
#ifndef __FALCON_IRQ_H
#define __FALCON_IRQ_H
#include <falcon_irq.h>
#define NR_IRQS 328
#include_next <irq.h>
#endif

152
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h Normal file
View File

@@ -0,0 +1,152 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#ifndef _LTQ_FALCON_H__
#define _LTQ_FALCON_H__
#ifdef CONFIG_SOC_FALCON
#include <lantiq.h>
/* Chip IDs */
#define SOC_ID_FALCON 0x01B8
/* SoC Types */
#define SOC_TYPE_FALCON 0x01
/* ASC0/1 - serial port */
#define LTQ_ASC0_BASE_ADDR 0x1E100C00
#define LTQ_ASC1_BASE_ADDR 0x1E100B00
#define LTQ_ASC_SIZE 0x100
#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
/*
* during early_printk no ioremap possible at this early stage
* lets use KSEG1 instead
*/
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
/* ICU - interrupt control unit */
#define LTQ_ICU_BASE_ADDR 0x1F880200
#define LTQ_ICU_SIZE 0x100
/* WDT */
#define LTQ_WDT_BASE_ADDR 0x1F8803F0
#define LTQ_WDT_SIZE 0x10
#define LTQ_RST_CAUSE_WDTRST 0x0002
/* EBU - external bus unit */
#define LTQ_EBU_BASE_ADDR 0x18000000
#define LTQ_EBU_SIZE 0x0100
#define LTQ_EBU_MODCON 0x000C
/* GPIO */
#define LTQ_GPIO0_BASE_ADDR 0x1D810000
#define LTQ_GPIO0_SIZE 0x0080
#define LTQ_GPIO1_BASE_ADDR 0x1E800100
#define LTQ_GPIO1_SIZE 0x0080
#define LTQ_GPIO2_BASE_ADDR 0x1D810100
#define LTQ_GPIO2_SIZE 0x0080
#define LTQ_GPIO3_BASE_ADDR 0x1E800200
#define LTQ_GPIO3_SIZE 0x0080
#define LTQ_GPIO4_BASE_ADDR 0x1E800300
#define LTQ_GPIO4_SIZE 0x0080
#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000
#define LTQ_PADCTRL0_SIZE 0x0100
#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400
#define LTQ_PADCTRL1_SIZE 0x0100
#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000
#define LTQ_PADCTRL2_SIZE 0x0100
#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500
#define LTQ_PADCTRL3_SIZE 0x0100
#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600
#define LTQ_PADCTRL4_SIZE 0x0100
/* I2C */
#define GPON_I2C_BASE 0x1E200000
#define GPON_I2C_SIZE 0x00010000
/* CHIP ID */
#define LTQ_STATUS_BASE_ADDR 0x1E802000
#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
#define LTQ_SYS1_BASE_ADDR 0x1EF00000
#define LTQ_SYS1_SIZE 0x0100
#define LTQ_STATUS_BASE_ADDR 0x1E802000
#define LTQ_STATUS_SIZE 0x0080
#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000
#define LTQ_SYS_ETH_SIZE 0x0100
#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000
#define LTQ_SYS_GPE_SIZE 0x0100
#define SYSCTL_SYS1 0
#define SYSCTL_SYSETH 1
#define SYSCTL_SYSGPE 2
/* Activation Status Register */
#define ACTS_ASC1_ACT 0x00000800
#define ACTS_I2C_ACT 0x00004000
#define ACTS_P0 0x00010000
#define ACTS_P1 0x00010000
#define ACTS_P2 0x00020000
#define ACTS_P3 0x00020000
#define ACTS_P4 0x00040000
#define ACTS_PADCTRL0 0x00100000
#define ACTS_PADCTRL1 0x00100000
#define ACTS_PADCTRL2 0x00200000
#define ACTS_PADCTRL3 0x00200000
#define ACTS_PADCTRL4 0x00400000
#define ACTS_I2C_ACT 0x00004000
/* global register ranges */
extern __iomem void *ltq_ebu_membase;
extern __iomem void *ltq_sys1_membase;
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
#define ltq_ebu_w32_mask(clear, set, reg) \
ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
#define ltq_sys1_w32_mask(clear, set, reg) \
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
/* gpio wrapper to help configure the pin muxing */
extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
/* to keep the irq code generic we need to define these to 0 as falcon
has no EIU/EBU */
#define LTQ_EIU_BASE_ADDR 0
#define LTQ_EBU_PCC_ISTAT 0
static inline int ltq_is_ar9(void)
{
return 0;
}
static inline int ltq_is_vr9(void)
{
return 0;
}
static inline int ltq_is_falcon(void)
{
return 1;
}
#endif /* CONFIG_SOC_FALCON */
#endif /* _LTQ_XWAY_H__ */

155
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h Normal file
View File

@@ -0,0 +1,155 @@
#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
/******************************************************************************
Copyright (c) 2002, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
******************************************************************************/
/*
* ####################################
* Definition
* ####################################
*/
/*
* Available Timer/Counter Index
*/
#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
#define TIMER_ANY 0x00
#define TIMER1A TIMER(1, 0)
#define TIMER1B TIMER(1, 1)
#define TIMER2A TIMER(2, 0)
#define TIMER2B TIMER(2, 1)
#define TIMER3A TIMER(3, 0)
#define TIMER3B TIMER(3, 1)
/*
* Flag of Timer/Counter
* These flags specify the way in which timer is configured.
*/
/* Bit size of timer/counter. */
#define TIMER_FLAG_16BIT 0x0000
#define TIMER_FLAG_32BIT 0x0001
/* Switch between timer and counter. */
#define TIMER_FLAG_TIMER 0x0000
#define TIMER_FLAG_COUNTER 0x0002
/* Stop or continue when overflowing/underflowing. */
#define TIMER_FLAG_ONCE 0x0000
#define TIMER_FLAG_CYCLIC 0x0004
/* Count up or counter down. */
#define TIMER_FLAG_UP 0x0000
#define TIMER_FLAG_DOWN 0x0008
/* Count on specific level or edge. */
#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
#define TIMER_FLAG_RISE_EDGE 0x0010
#define TIMER_FLAG_FALL_EDGE 0x0020
#define TIMER_FLAG_ANY_EDGE 0x0030
/* Signal is syncronous to module clock or not. */
#define TIMER_FLAG_UNSYNC 0x0000
#define TIMER_FLAG_SYNC 0x0080
/* Different interrupt handle type. */
#define TIMER_FLAG_NO_HANDLE 0x0000
#if defined(__KERNEL__)
#define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
#endif // defined(__KERNEL__)
#define TIMER_FLAG_SIGNAL 0x0300
/* Internal clock source or external clock source */
#define TIMER_FLAG_INT_SRC 0x0000
#define TIMER_FLAG_EXT_SRC 0x1000
/*
* ioctl Command
*/
#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
/*
* Data Type Used to Call ioctl
*/
struct gptu_ioctl_param {
unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
* GPTU_SET_COUNTER, this field is ID of expected *
* timer/counter. If it's zero, a timer/counter would *
* be dynamically allocated and ID would be stored in *
* this field. *
* In command GPTU_GET_COUNT_VALUE, this field is *
* ignored. *
* In other command, this field is ID of timer/counter *
* allocated. */
unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
* GPTU_SET_COUNTER, this field contains flags to *
* specify how to configure timer/counter. *
* In command GPTU_START_TIMER, zero indicate start *
* and non-zero indicate resume timer/counter. *
* In other command, this field is ignored. */
unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
* init/reload value. *
* In command GPTU_SET_TIMER, this field contains *
* frequency (0.001Hz) of timer. *
* In command GPTU_GET_COUNT_VALUE, current count *
* value would be stored in this field. *
* In command GPTU_CALCULATE_DIVIDER, this field *
* contains frequency wanted, and after calculation, *
* divider would be stored in this field to overwrite *
* the frequency. *
* In other command, this field is ignored. */
int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
* if signal is required, this field contains process *
* ID to which signal would be sent. *
* In other command, this field is ignored. */
int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
* if signal is required, this field contains signal *
* number which would be sent. *
* In other command, this field is ignored. */
};
/*
* ####################################
* Data Type
* ####################################
*/
typedef void (*timer_callback)(unsigned long arg);
extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
extern int lq_free_timer(unsigned int);
extern int lq_start_timer(unsigned int, int);
extern int lq_stop_timer(unsigned int);
extern int lq_reset_counter_flags(u32 timer, u32 flags);
extern int lq_get_count_value(unsigned int, unsigned long *);
extern u32 lq_cal_divider(unsigned long);
extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
extern int lq_set_counter(unsigned int timer, unsigned int flag,
u32 reload, unsigned long arg1, unsigned long arg2);
#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */

56
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h Normal file
View File

@@ -0,0 +1,56 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __BASE_REG_H
#define __BASE_REG_H
#ifndef KSEG1
#define KSEG1 0xA0000000
#endif
#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000)
#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000)
#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000)
#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000)
#define LTQ_ASC0_BASE (KSEG1 + 0x14100100)
#define LTQ_ASC1_BASE (KSEG1 + 0x14100200)
#define LTQ_SSC0_BASE (0x14100300)
#define LTQ_SSC1_BASE (0x14100400)
#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600)
#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100)
#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800)
#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900)
#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400)
#define LTQ_EBU_BASE (KSEG1 + 0x14102000)
#define LTQ_DMA_BASE (KSEG1 + 0x14104000)
#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000)
#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000)
#define LTQ_ES_BASE (KSEG1 + 0x18000000)
#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000)
#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800)
#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000)
#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000)
#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100)
#define LTQ_MBS_BASE (KSEG1 + 0x1E000200)
#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500)
#endif

37
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h Normal file
View File

@@ -0,0 +1,37 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __BOOT_REG_H
#define __BOOT_REG_H
#define LTQ_BOOT_CPU_OFFSET 0x20
#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x00)
#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x04)
#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x08)
#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C)
#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x10)
#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x14)
#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */
#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */
#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
(cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C)
#endif

308
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h Normal file
View File

@@ -0,0 +1,308 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __DMA_REG_H
#define __DMA_REG_H
#define dma_r32(reg) ltq_r32(&dma->reg)
#define dma_w32(val, reg) ltq_w32(val, &dma->reg)
#define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg)
/** DMA register structure */
struct svip_reg_dma {
volatile unsigned long clc; /* 0x00 */
volatile unsigned long reserved0; /* 0x04 */
volatile unsigned long id; /* 0x08 */
volatile unsigned long reserved1; /* 0x0c */
volatile unsigned long ctrl; /* 0x10 */
volatile unsigned long cpoll; /* 0x14 */
volatile unsigned long cs; /* 0x18 */
volatile unsigned long cctrl; /* 0x1C */
volatile unsigned long cdba; /* 0x20 */
volatile unsigned long cdlen; /* 0x24 */
volatile unsigned long cis; /* 0x28 */
volatile unsigned long cie; /* 0x2C */
volatile unsigned long cgbl; /* 0x30 */
volatile unsigned long reserved2[3]; /* 0x34 */
volatile unsigned long ps; /* 0x40 */
volatile unsigned long pctrl; /* 0x44 */
volatile unsigned long reserved3[43]; /* 0x48 */
volatile unsigned long irnen; /* 0xF4 */
volatile unsigned long irncr; /* 0xF8 */
volatile unsigned long irnicr; /* 0xFC */
};
/*******************************************************************************
* CLC Register
******************************************************************************/
/* Fast Shut-Off Enable Bit (5) */
#define DMA_CLC_FSOE (0x1 << 5)
#define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5)
#define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1)
#define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5))
/* Suspend Bit Write Enable for OCDS (4) */
#define DMA_CLC_SBWE (0x1 << 4)
#define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4)
#define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4)
/* External Request Disable (3) */
#define DMA_CLC_EDIS (0x1 << 3)
#define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3)
#define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1)
#define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3))
/* Suspend Enable Bit for OCDS (2) */
#define DMA_CLC_SPEN (0x1 << 2)
#define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2)
#define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1)
#define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2))
/* Disable Status Bit (1) */
#define DMA_CLC_DISS (0x1 << 1)
#define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1)
/* Disable Request Bit (0) */
#define DMA_CLC_DISR (0x1)
#define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0)
#define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1)
#define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0))
/*******************************************************************************
* ID Register
******************************************************************************/
/* Number of Channels (25:20) */
#define DMA_ID_CHNR (0x3f << 20)
#define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f)
/* Number of Ports (19:16) */
#define DMA_ID_PRTNR (0xf << 16)
#define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf)
/* Module ID (15:8) */
#define DMA_ID_ID (0xff << 8)
#define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff)
/* Revision (4:0) */
#define DMA_ID_REV (0x1f)
#define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f)
/*******************************************************************************
* Control Register
******************************************************************************/
/* Global Software Reset (0) */
#define DMA_CTRL_RST (0x1)
#define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1)
/*******************************************************************************
* Channel Polling Register
******************************************************************************/
/* Enable (31) */
#define DMA_CPOLL_EN (0x1 << 31)
#define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31)
#define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1)
#define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31))
/* Counter (15:4) */
#define DMA_CPOLL_CNT (0xfff << 4)
#define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4)
#define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff)
#define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4))
/*******************************************************************************
* Global Buffer Length Register
******************************************************************************/
/* Global Buffer Length (15:0) */
#define DMA_CGBL_GBL (0xffff)
#define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0)
#define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff)
#define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0))
/*******************************************************************************
* Channel Select Register
******************************************************************************/
/* Channel Selection (4:0) */
#define DMA_CS_CS (0x1f)
#define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0)
#define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f)
#define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0))
/*******************************************************************************
* Channel Control Register
******************************************************************************/
/* Peripheral to Peripheral Copy (24) */
#define DMA_CCTRL_P2PCPY (0x1 << 24)
#define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24)
#define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1)
#define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24))
/* Channel Weight for Transmit Direction (17:16) */
#define DMA_CCTRL_TXWGT (0x3 << 16)
#define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16)
#define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3)
#define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16))
/* Port Assignment (13:11) */
#define DMA_CCTRL_PRTNR (0x7 << 11)
#define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7)
/* Class (10:9) */
#define DMA_CCTRL_CLASS (0x3 << 9)
#define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9)
#define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3)
#define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9))
/* Direction (8) */
#define DMA_CCTRL_DIR (0x1 << 8)
#define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1)
/* Reset (1) */
#define DMA_CCTRL_RST (0x1 << 1)
#define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1)
#define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1)
#define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1))
/* Channel On or Off (0) */
#define DMA_CCTRL_ON_OFF (0x1)
#define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0)
#define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1)
#define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0))
/*******************************************************************************
* Channel Descriptor Base Address Register
******************************************************************************/
/* Channel Descriptor Base Address (29:3) */
#define DMA_CDBA_CDBA (0x7ffffff << 3)
#define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3)
#define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff)
#define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3))
/*******************************************************************************
* Channel Descriptor Length Register
******************************************************************************/
/* Channel Descriptor Length (7:0) */
#define DMA_CDLEN_CDLEN (0xff)
#define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0)
#define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff)
#define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0))
/*******************************************************************************
* Channel Interrupt Status Register
******************************************************************************/
/* SAI Read Error Interrupt (5) */
#define DMA_CIS_RDERR (0x1 << 5)
#define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1)
/* Channel Off Interrupt (4) */
#define DMA_CIS_CHOFF (0x1 << 4)
#define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1)
/* Descriptor Complete Interrupt (3) */
#define DMA_CIS_DESCPT (0x1 << 3)
#define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1)
/* Descriptor Under-Run Interrupt (2) */
#define DMA_CIS_DUR (0x1 << 2)
#define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1)
/* End of Packet Interrupt (1) */
#define DMA_CIS_EOP (0x1 << 1)
#define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1)
/*******************************************************************************
* Channel Interrupt Enable Register
******************************************************************************/
/* SAI Read Error Interrupt (5) */
#define DMA_CIE_RDERR (0x1 << 5)
#define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1)
/* Channel Off Interrupt (4) */
#define DMA_CIE_CHOFF (0x1 << 4)
#define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1)
/* Descriptor Complete Interrupt Enable (3) */
#define DMA_CIE_DESCPT (0x1 << 3)
#define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1)
/* Descriptor Under Run Interrupt Enable (2) */
#define DMA_CIE_DUR (0x1 << 2)
#define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1)
/* End of Packet Interrupt Enable (1) */
#define DMA_CIE_EOP (0x1 << 1)
#define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1)
/*******************************************************************************
* Port Select Register
******************************************************************************/
/* Port Selection (2:0) */
#define DMA_PS_PS (0x7)
#define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0)
#define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7)
#define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0))
/*******************************************************************************
* Port Control Register
******************************************************************************/
/* General Purpose Control (16) */
#define DMA_PCTRL_GPC (0x1 << 16)
#define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16)
#define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1)
#define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16))
/* Port Weight for Transmit Direction (14:12) */
#define DMA_PCTRL_TXWGT (0x7 << 12)
#define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12)
#define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7)
#define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12))
/* Endianness for Transmit Direction (11:10) */
#define DMA_PCTRL_TXENDI (0x3 << 10)
#define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10)
#define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3)
#define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10))
/* Endianness for Receive Direction (9:8) */
#define DMA_PCTRL_RXENDI (0x3 << 8)
#define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8)
#define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3)
#define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8))
/* Packet Drop Enable (6) */
#define DMA_PCTRL_PDEN (0x1 << 6)
#define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6)
#define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1)
#define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6))
/* Burst Length for Transmit Direction (5:4) */
#define DMA_PCTRL_TXBL (0x3 << 4)
#define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4)
#define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3)
#define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4))
/* Burst Length for Receive Direction (3:2) */
#define DMA_PCTRL_RXBL (0x3 << 2)
#define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2)
#define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3)
#define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2))
/*******************************************************************************
* DMA_IRNEN Register
******************************************************************************/
/* Channel x Interrupt Request Enable (23) */
#define DMA_IRNEN_CH23 (0x1 << 23)
#define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23)
#define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1)
#define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23))
/*******************************************************************************
* DMA_IRNCR Register
******************************************************************************/
/* Channel x Interrupt (23) */
#define DMA_IRNCR_CH23 (0x1 << 23)
#define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1)
/*******************************************************************************
* DMA_IRNICR Register
******************************************************************************/
/* Channel x Interrupt Request (23) */
#define DMA_IRNICR_CH23 (0x1 << 23)
#define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1)
#endif

615
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h Normal file
View File

@@ -0,0 +1,615 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __EBU_REG_H
#define __EBU_REG_H
#define ebu_r32(reg) ltq_r32(&ebu->reg)
#define ebu_w32(val, reg) ltq_w32(val, &ebu->reg)
#define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg)
/** EBU register structure */
struct svip_reg_ebu {
volatile unsigned long clc; /* 0x0000 */
volatile unsigned long reserved0; /* 0x04 */
volatile unsigned long id; /* 0x0008 */
volatile unsigned long reserved1; /* 0x0c */
volatile unsigned long con; /* 0x0010 */
volatile unsigned long reserved2[3]; /* 0x14 */
volatile unsigned long addr_sel_0; /* 0x0020 */
volatile unsigned long addr_sel_1; /* 0x0024 */
volatile unsigned long addr_sel_2; /* 0x0028 */
volatile unsigned long addr_sel_3; /* 0x002c */
volatile unsigned long reserved3[12]; /* 0x30 */
volatile unsigned long con_0; /* 0x0060 */
volatile unsigned long con_1; /* 0x0064 */
volatile unsigned long con_2; /* 0x0068 */
volatile unsigned long con_3; /* 0x006c */
volatile unsigned long reserved4[4]; /* 0x70 */
volatile unsigned long emu_addr; /* 0x0080 */
volatile unsigned long emu_bc; /* 0x0084 */
volatile unsigned long emu_con; /* 0x0088 */
volatile unsigned long reserved5; /* 0x8c */
volatile unsigned long pcc_con; /* 0x0090 */
volatile unsigned long pcc_stat; /* 0x0094 */
volatile unsigned long reserved6[2]; /* 0x98 */
volatile unsigned long pcc_istat; /* 0x00A0 */
volatile unsigned long pcc_ien; /* 0x00A4 */
volatile unsigned long pcc_int_out; /* 0x00A8 */
volatile unsigned long pcc_irs; /* 0x00AC */
volatile unsigned long nand_con; /* 0x00B0 */
volatile unsigned long nand_wait; /* 0x00B4 */
volatile unsigned long nand_ecc0; /* 0x00B8 */
volatile unsigned long nand_ecc_ac; /* 0x00BC */
};
/*******************************************************************************
* EBU
******************************************************************************/
#define LTQ_EBU_CLC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000))
#define LTQ_EBU_ID ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008))
#define LTQ_EBU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010))
#define LTQ_EBU_ADDR_SEL_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020))
#define LTQ_EBU_ADDR_SEL_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024))
#define LTQ_EBU_ADDR_SEL_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028))
#define LTQ_EBU_ADDR_SEL_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c))
#define LTQ_EBU_CON_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060))
#define LTQ_EBU_CON_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064))
#define LTQ_EBU_CON_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068))
#define LTQ_EBU_CON_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c))
#define LTQ_EBU_EMU_BC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084))
#define LTQ_EBU_PCC_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090))
#define LTQ_EBU_PCC_STAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094))
#define LTQ_EBU_PCC_ISTAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0))
#define LTQ_EBU_PCC_IEN ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4))
#define LTQ_EBU_PCC_INT_OUT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8))
#define LTQ_EBU_PCC_IRS ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC))
#define LTQ_EBU_NAND_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0))
#define LTQ_EBU_NAND_WAIT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4))
#define LTQ_EBU_NAND_ECC0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8))
#define LTQ_EBU_NAND_ECC_AC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC))
#define LTQ_EBU_EMU_ADDR ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080))
#define LTQ_EBU_EMU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088))
/*******************************************************************************
* EBU Clock Control Register
******************************************************************************/
/* EBU Disable Status Bit (1) */
#define LTQ_EBU_CLC_DISS (0x1 << 1)
#define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1)
/* Used for Enable/disable Control of the EBU (0) */
#define LTQ_EBU_CLC_DISR (0x1)
#define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1)
#define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0))
/*******************************************************************************
* EBU Identification Register (Internal)
******************************************************************************/
/* Module Number (31:8) */
#define LTQ_EBU_ID_MODNUM (0xffffff << 8)
#define LTQ_EBU_ID_MODNUM_GET(val) ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff)
/* Revision Number (7:0) */
#define LTQ_EBU_ID_REVNUM (0xff)
#define LTQ_EBU_ID_REVNUM_GET(val) ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff)
/*******************************************************************************
* External Bus Unit Control Register
******************************************************************************/
/* Driver Turn-Around Control, Chip Select Triggered (22:20) */
#define LTQ_EBU_CON_DTACS (0x7 << 20)
#define LTQ_EBU_CON_DTACS_VAL(val) (((val) & 0x7) << 20)
#define LTQ_EBU_CON_DTACS_GET(val) ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7)
#define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20))
/* Driver Turn-Around Control, Read-write Triggered (18:16) */
#define LTQ_EBU_CON_DTARW (0x7 << 16)
#define LTQ_EBU_CON_DTARW_VAL(val) (((val) & 0x7) << 16)
#define LTQ_EBU_CON_DTARW_GET(val) ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7)
#define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16))
/* Time-Out Control (15:8) */
#define LTQ_EBU_CON_TOUTC (0xff << 8)
#define LTQ_EBU_CON_TOUTC_VAL(val) (((val) & 0xff) << 8)
#define LTQ_EBU_CON_TOUTC_GET(val) ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff)
#define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8))
/* Arbitration Mode (7:6) */
#define LTQ_EBU_CON_ARBMODE (0x3 << 6)
#define LTQ_EBU_CON_ARBMODE_VAL(val) (((val) & 0x3) << 6)
#define LTQ_EBU_CON_ARBMODE_GET(val) ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3)
#define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6))
/* Arbitration Synchronization (5) */
#define LTQ_EBU_CON_ARBSYNC (0x1 << 5)
#define LTQ_EBU_CON_ARBSYNC_VAL(val) (((val) & 0x1) << 5)
#define LTQ_EBU_CON_ARBSYNC_GET(val) ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1)
#define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5))
/*******************************************************************************
* Address Select Registers
******************************************************************************/
/* Memory Region Base Address (31:12) */
#define LTQ_EBU_ADDR_SEL_0_BASE (0xfffff << 12)
#define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val) (((val) & 0xfffff) << 12)
#define LTQ_EBU_ADDR_SEL_0_BASE_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff)
#define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12))
/* Memory Region Address Mask (7:4) */
#define LTQ_EBU_ADDR_SEL_0_MASK (0xf << 4)
#define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val) (((val) & 0xf) << 4)
#define LTQ_EBU_ADDR_SEL_0_MASK_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf)
#define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4))
/* Memory Region Mirror Enable Control (1) */
#define LTQ_EBU_ADDR_SEL_0_MRME (0x1 << 1)
#define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_ADDR_SEL_0_MRME_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1)
#define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1))
/* Memory Region Enable Control (0) */
#define LTQ_EBU_ADDR_SEL_0_REGEN (0x1)
#define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1)
#define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* Bus Configuration Registers
******************************************************************************/
/* Memory Region Write Protection (31) */
#define LTQ_EBU_CON_0_WRDIS (0x1 << 31)
#define LTQ_EBU_CON_0_WRDIS_VAL(val) (((val) & 0x1) << 31)
#define LTQ_EBU_CON_0_WRDIS_GET(val) ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1)
#define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31))
/* Address Swapping (30) */
#define LTQ_EBU_CON_0_ADSWP (0x1 << 30)
#define LTQ_EBU_CON_0_ADSWP_VAL(val) (((val) & 0x1) << 30)
#define LTQ_EBU_CON_0_ADSWP_GET(val) ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1)
#define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30))
/* Address Generation Control (26:24) */
#define LTQ_EBU_CON_0_AGEN (0x7 << 24)
#define LTQ_EBU_CON_0_AGEN_VAL(val) (((val) & 0x7) << 24)
#define LTQ_EBU_CON_0_AGEN_GET(val) ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7)
#define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24))
/* Extended Address Setup Control (22) */
#define LTQ_EBU_CON_0_SETUP (0x1 << 22)
#define LTQ_EBU_CON_0_SETUP_VAL(val) (((val) & 0x1) << 22)
#define LTQ_EBU_CON_0_SETUP_GET(val) ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1)
#define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22))
/* Variable Wait-State Insertion Control (21:20) */
#define LTQ_EBU_CON_0_WAIT (0x3 << 20)
#define LTQ_EBU_CON_0_WAIT_VAL(val) (((val) & 0x3) << 20)
#define LTQ_EBU_CON_0_WAIT_GET(val) ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3)
#define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20))
/* Active WAIT Level Control (19) */
#define LTQ_EBU_CON_0_WINV (0x1 << 19)
#define LTQ_EBU_CON_0_WINV_VAL(val) (((val) & 0x1) << 19)
#define LTQ_EBU_CON_0_WINV_GET(val) ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1)
#define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19))
/* External Device Data Width Control (17:16) */
#define LTQ_EBU_CON_0_PW (0x3 << 16)
#define LTQ_EBU_CON_0_PW_VAL(val) (((val) & 0x3) << 16)
#define LTQ_EBU_CON_0_PW_GET(val) ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3)
#define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16))
/* Address Latch Enable ALE Duration Control (15:14) */
#define LTQ_EBU_CON_0_ALEC (0x3 << 14)
#define LTQ_EBU_CON_0_ALEC_VAL(val) (((val) & 0x3) << 14)
#define LTQ_EBU_CON_0_ALEC_GET(val) ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3)
#define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14))
/* Byte Control Signal Timing Mode Control (13:12) */
#define LTQ_EBU_CON_0_BCGEN (0x3 << 12)
#define LTQ_EBU_CON_0_BCGEN_VAL(val) (((val) & 0x3) << 12)
#define LTQ_EBU_CON_0_BCGEN_GET(val) ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3)
#define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12))
/* Write Access Wait-State Control (10:8) */
#define LTQ_EBU_CON_0_WAITWRC (0x7 << 8)
#define LTQ_EBU_CON_0_WAITWRC_VAL(val) (((val) & 0x7) << 8)
#define LTQ_EBU_CON_0_WAITWRC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7)
#define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8))
/* Read Access Wait-State Control (7:6) */
#define LTQ_EBU_CON_0_WAITRDC (0x3 << 6)
#define LTQ_EBU_CON_0_WAITRDC_VAL(val) (((val) & 0x3) << 6)
#define LTQ_EBU_CON_0_WAITRDC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3)
#define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6))
/* Hold/Pause Cycle Control (5:4) */
#define LTQ_EBU_CON_0_HOLDC (0x3 << 4)
#define LTQ_EBU_CON_0_HOLDC_VAL(val) (((val) & 0x3) << 4)
#define LTQ_EBU_CON_0_HOLDC_GET(val) ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3)
#define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4))
/* Recovery Cycle Control (3:2) */
#define LTQ_EBU_CON_0_RECOVC (0x3 << 2)
#define LTQ_EBU_CON_0_RECOVC_VAL(val) (((val) & 0x3) << 2)
#define LTQ_EBU_CON_0_RECOVC_GET(val) ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3)
#define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2))
/* Wait Cycle Multiplier Control (1:0) */
#define LTQ_EBU_CON_0_CMULT (0x3)
#define LTQ_EBU_CON_0_CMULT_VAL(val) (((val) & 0x3) << 0)
#define LTQ_EBU_CON_0_CMULT_GET(val) ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3)
#define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0))
/*******************************************************************************
* External Bus Unit Emulator Bus Configuration Register
******************************************************************************/
/* Write Protection (31) */
#define LTQ_EBU_EMU_BC_WRITE (0x1 << 31)
#define LTQ_EBU_EMU_BC_WRITE_VAL(val) (((val) & 0x1) << 31)
#define LTQ_EBU_EMU_BC_WRITE_GET(val) ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1)
#define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31))
/* Address Generation Control (26:24) */
#define LTQ_EBU_EMU_BC_AGEN (0x7 << 24)
#define LTQ_EBU_EMU_BC_AGEN_VAL(val) (((val) & 0x7) << 24)
#define LTQ_EBU_EMU_BC_AGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7)
#define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24))
/* Extended Address Setup Control (22) */
#define LTQ_EBU_EMU_BC_SETUP (0x1 << 22)
#define LTQ_EBU_EMU_BC_SETUP_VAL(val) (((val) & 0x1) << 22)
#define LTQ_EBU_EMU_BC_SETUP_GET(val) ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1)
#define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22))
/* Variable Waitstate Insertion Control (21:20) */
#define LTQ_EBU_EMU_BC_WAIT (0x3 << 20)
#define LTQ_EBU_EMU_BC_WAIT_VAL(val) (((val) & 0x3) << 20)
#define LTQ_EBU_EMU_BC_WAIT_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3)
#define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20))
/* Active WAIT Level Control (19) */
#define LTQ_EBU_EMU_BC_WINV (0x1 << 19)
#define LTQ_EBU_EMU_BC_WINV_VAL(val) (((val) & 0x1) << 19)
#define LTQ_EBU_EMU_BC_WINV_GET(val) ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1)
#define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19))
/* External Device Data Width Control (17:16) */
#define LTQ_EBU_EMU_BC_PORTW (0x3 << 16)
#define LTQ_EBU_EMU_BC_PORTW_VAL(val) (((val) & 0x3) << 16)
#define LTQ_EBU_EMU_BC_PORTW_GET(val) ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3)
#define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16))
/* Address Latch Enable Function (15:14) */
#define LTQ_EBU_EMU_BC_ALEC (0x3 << 14)
#define LTQ_EBU_EMU_BC_ALEC_VAL(val) (((val) & 0x3) << 14)
#define LTQ_EBU_EMU_BC_ALEC_GET(val) ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3)
#define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14))
/* Byte Control Signal Timing Mode (13:12) */
#define LTQ_EBU_EMU_BC_BCGEN (0x3 << 12)
#define LTQ_EBU_EMU_BC_BCGEN_VAL(val) (((val) & 0x3) << 12)
#define LTQ_EBU_EMU_BC_BCGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3)
#define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12))
/* Write Access Waitstate Control (10:8) */
#define LTQ_EBU_EMU_BC_WAITWRC (0x7 << 8)
#define LTQ_EBU_EMU_BC_WAITWRC_VAL(val) (((val) & 0x7) << 8)
#define LTQ_EBU_EMU_BC_WAITWRC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7)
#define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8))
/* Read Access Waitstate Control (7:6) */
#define LTQ_EBU_EMU_BC_WAITRDC (0x3 << 6)
#define LTQ_EBU_EMU_BC_WAITRDC_VAL(val) (((val) & 0x3) << 6)
#define LTQ_EBU_EMU_BC_WAITRDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3)
#define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6))
/* Hold/Pause Cycle Control (5:4) */
#define LTQ_EBU_EMU_BC_HOLDC (0x3 << 4)
#define LTQ_EBU_EMU_BC_HOLDC_VAL(val) (((val) & 0x3) << 4)
#define LTQ_EBU_EMU_BC_HOLDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3)
#define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4))
/* Recovery Cycles Control (3:2) */
#define LTQ_EBU_EMU_BC_RECOVC (0x3 << 2)
#define LTQ_EBU_EMU_BC_RECOVC_VAL(val) (((val) & 0x3) << 2)
#define LTQ_EBU_EMU_BC_RECOVC_GET(val) ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3)
#define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2))
/* Cycle Multiplier Control (1:0) */
#define LTQ_EBU_EMU_BC_CMULT (0x3)
#define LTQ_EBU_EMU_BC_CMULT_VAL(val) (((val) & 0x3) << 0)
#define LTQ_EBU_EMU_BC_CMULT_GET(val) ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3)
#define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0))
/*******************************************************************************
* PC-Card Control Register
******************************************************************************/
/* External Interrupt Input IREQ (3:1) */
#define LTQ_EBU_PCC_CON_IREQ (0x7 << 1)
#define LTQ_EBU_PCC_CON_IREQ_VAL(val) (((val) & 0x7) << 1)
#define LTQ_EBU_PCC_CON_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7)
#define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1))
/* PC Card ON (0) */
#define LTQ_EBU_PCC_CON_ON (0x1)
#define LTQ_EBU_PCC_CON_ON_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_CON_ON_GET(val) ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1)
#define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0))
/*******************************************************************************
* PCC Status Register
******************************************************************************/
/* Interrupt Request (6) */
#define LTQ_EBU_PCC_STAT_IRQ (0x1 << 6)
#define LTQ_EBU_PCC_STAT_IRQ_GET(val) ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1)
/* PC-Card Overcurrent (5) */
#define LTQ_EBU_PCC_STAT_OC (0x1 << 5)
#define LTQ_EBU_PCC_STAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1)
/* PC-Card Socket Power On (4) */
#define LTQ_EBU_PCC_STAT_SPON (0x1 << 4)
#define LTQ_EBU_PCC_STAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1)
/* Card Detect Status (1:0) */
#define LTQ_EBU_PCC_STAT_CD (0x3)
#define LTQ_EBU_PCC_STAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3)
/*******************************************************************************
* PCC Interrupt Status Register
******************************************************************************/
/* Interrupt Request Active Interrupt (4) */
#define LTQ_EBU_PCC_ISTAT_IREQ (0x1 << 4)
#define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_PCC_ISTAT_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1)
#define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4))
/* Over Current Status Change Interrupt (3) */
#define LTQ_EBU_PCC_ISTAT_OC (0x1 << 3)
#define LTQ_EBU_PCC_ISTAT_OC_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_PCC_ISTAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1)
#define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3))
/* Socket Power on Status Change Interrupt (2) */
#define LTQ_EBU_PCC_ISTAT_SPON (0x1 << 2)
#define LTQ_EBU_PCC_ISTAT_SPON_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_PCC_ISTAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1)
#define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2))
/* Voltage Sense Status Change Interrupt (1) */
#define LTQ_EBU_PCC_ISTAT_VS (0x1 << 1)
#define LTQ_EBU_PCC_ISTAT_VS_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_PCC_ISTAT_VS_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1)
#define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1))
/* Card Detect Status Change Interrupt (0) */
#define LTQ_EBU_PCC_ISTAT_CD (0x1)
#define LTQ_EBU_PCC_ISTAT_CD_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_ISTAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1)
#define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0))
/*******************************************************************************
* PCC Interrupt Enable Register
******************************************************************************/
/* Enable of Interrupt Request IR (4) */
#define LTQ_EBU_PCC_IEN_IR (0x1 << 4)
#define LTQ_EBU_PCC_IEN_IR_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_PCC_IEN_IR_GET(val) ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1)
#define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4))
/* Enable of Interrupt Request OC event (3) */
#define LTQ_EBU_PCC_IEN_OC (0x1 << 3)
#define LTQ_EBU_PCC_IEN_OC_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_PCC_IEN_OC_GET(val) ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1)
#define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3))
/* Enable of Interrupt Request Socket Power On (2) */
#define LTQ_EBU_PCC_IEN_PWRON (0x1 << 2)
#define LTQ_EBU_PCC_IEN_PWRON_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_PCC_IEN_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1)
#define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2))
/* Enable of Interrupt Request Voltage Sense (1) */
#define LTQ_EBU_PCC_IEN_VS (0x1 << 1)
#define LTQ_EBU_PCC_IEN_VS_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_PCC_IEN_VS_GET(val) ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1)
#define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1))
/* Enable of Interrupt Request Card Detect (0) */
#define LTQ_EBU_PCC_IEN_CD (0x1)
#define LTQ_EBU_PCC_IEN_CD_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_IEN_CD_GET(val) ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1)
#define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0))
/*******************************************************************************
* PCC Interrupt Output Status Register
******************************************************************************/
/* Status of Interrupt Request IR (4) */
#define LTQ_EBU_PCC_INT_OUT_IR (0x1 << 4)
#define LTQ_EBU_PCC_INT_OUT_IR_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1)
/* Status of Interrupt Request OC (3) */
#define LTQ_EBU_PCC_INT_OUT_OC (0x1 << 3)
#define LTQ_EBU_PCC_INT_OUT_OC_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1)
/* Status of Interrupt Request Socket Power On (2) */
#define LTQ_EBU_PCC_INT_OUT_PWRON (0x1 << 2)
#define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1)
/* Status of Interrupt Request Voltage Sense (1) */
#define LTQ_EBU_PCC_INT_OUT_VS (0x1 << 1)
#define LTQ_EBU_PCC_INT_OUT_VS_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1)
/* Status of Interrupt Request Card Detect (0) */
#define LTQ_EBU_PCC_INT_OUT_CD (0x1)
#define LTQ_EBU_PCC_INT_OUT_CD_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1)
/*******************************************************************************
* PCC Interrupt Request Set Register
******************************************************************************/
/* Set Interrupt Request IR (4) */
#define LTQ_EBU_PCC_IRS_IR (0x1 << 4)
#define LTQ_EBU_PCC_IRS_IR_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4)
/* Set Interrupt Request OC (3) */
#define LTQ_EBU_PCC_IRS_OC (0x1 << 3)
#define LTQ_EBU_PCC_IRS_OC_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3)
/* Set Interrupt Request Socket Power On (2) */
#define LTQ_EBU_PCC_IRS_PWRON (0x1 << 2)
#define LTQ_EBU_PCC_IRS_PWRON_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2)
/* Set Interrupt Request Voltage Sense (1) */
#define LTQ_EBU_PCC_IRS_VS (0x1 << 1)
#define LTQ_EBU_PCC_IRS_VS_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1)
/* Set Interrupt Request Card Detect (0) */
#define LTQ_EBU_PCC_IRS_CD (0x1)
#define LTQ_EBU_PCC_IRS_CD_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0)
/*******************************************************************************
* NAND Flash Control Register
******************************************************************************/
/* ECC Enabling (31) */
#define LTQ_EBU_NAND_CON_ECC_ON (0x1 << 31)
#define LTQ_EBU_NAND_CON_ECC_ON_VAL(val) (((val) & 0x1) << 31)
#define LTQ_EBU_NAND_CON_ECC_ON_GET(val) ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1)
#define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31))
/* Latch enable (23:18) */
#define LTQ_EBU_NAND_CON_LAT_EN (0x3f << 18)
#define LTQ_EBU_NAND_CON_LAT_EN_VAL(val) (((val) & 0x3f) << 18)
#define LTQ_EBU_NAND_CON_LAT_EN_GET(val) ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f)
#define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18))
/* Output ChipSelect# Selection (11:10) */
#define LTQ_EBU_NAND_CON_OUT_CS_S (0x3 << 10)
#define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val) (((val) & 0x3) << 10)
#define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3)
#define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10))
/* Input ChipSelect# Selection (9:8) */
#define LTQ_EBU_NAND_CON_IN_CS_S (0x3 << 8)
#define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val) (((val) & 0x3) << 8)
#define LTQ_EBU_NAND_CON_IN_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3)
#define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8))
/* Set PRE (7) */
#define LTQ_EBU_NAND_CON_PRE_P (0x1 << 7)
#define LTQ_EBU_NAND_CON_PRE_P_VAL(val) (((val) & 0x1) << 7)
#define LTQ_EBU_NAND_CON_PRE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1)
#define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7))
/* Set WP Active Polarity (6) */
#define LTQ_EBU_NAND_CON_WP_P (0x1 << 6)
#define LTQ_EBU_NAND_CON_WP_P_VAL(val) (((val) & 0x1) << 6)
#define LTQ_EBU_NAND_CON_WP_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1)
#define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6))
/* Set SE Active Polarity (5) */
#define LTQ_EBU_NAND_CON_SE_P (0x1 << 5)
#define LTQ_EBU_NAND_CON_SE_P_VAL(val) (((val) & 0x1) << 5)
#define LTQ_EBU_NAND_CON_SE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1)
#define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5))
/* Set CS Active Polarity (4) */
#define LTQ_EBU_NAND_CON_CS_P (0x1 << 4)
#define LTQ_EBU_NAND_CON_CS_P_VAL(val) (((val) & 0x1) << 4)
#define LTQ_EBU_NAND_CON_CS_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1)
#define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4))
/* Set CLE Active Polarity (3) */
#define LTQ_EBU_NAND_CON_CLE_P (0x1 << 3)
#define LTQ_EBU_NAND_CON_CLE_P_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_NAND_CON_CLE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1)
#define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3))
/* Set ALE Active Polarity (2) */
#define LTQ_EBU_NAND_CON_ALE_P (0x1 << 2)
#define LTQ_EBU_NAND_CON_ALE_P_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_NAND_CON_ALE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1)
#define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2))
/* NAND CS Mux with EBU CS Enable (1) */
#define LTQ_EBU_NAND_CON_CSMUX_E (0x1 << 1)
#define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_NAND_CON_CSMUX_E_GET(val) ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1)
#define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1))
/* NAND FLASH Mode Support (0) */
#define LTQ_EBU_NAND_CON_NANDMODE (0x1)
#define LTQ_EBU_NAND_CON_NANDMODE_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_NAND_CON_NANDMODE_GET(val) ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1)
#define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0))
/*******************************************************************************
* NAND Flash State Register
******************************************************************************/
/* Reserved (31:3) */
#define LTQ_EBU_NAND_WAIT_RES (0x1fffffff << 3)
#define LTQ_EBU_NAND_WAIT_RES_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff)
/* NAND Write Complete (3) */
#define LTQ_EBU_NAND_WAIT_WR_C (0x1 << 3)
#define LTQ_EBU_NAND_WAIT_WR_C_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1)
/* Record the RD Edge (rising ) (2) */
#define LTQ_EBU_NAND_WAIT_RD_EDGE (0x1 << 2)
#define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1)
/* Record the BY# Edge (falling) (1) */
#define LTQ_EBU_NAND_WAIT_BY_EDGE (0x1 << 1)
#define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1)
/* Rd/BY# value (0) */
#define LTQ_EBU_NAND_WAIT_RDBY_VALUE (0x1)
#define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1)
/*******************************************************************************
* NAND ECC Result Register 0
******************************************************************************/
/* Reserved (31:24) */
#define LTQ_EBU_NAND_ECC0_RES (0xff << 24)
#define LTQ_EBU_NAND_ECC0_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff)
/* ECC value (23:16) */
#define LTQ_EBU_NAND_ECC0_ECC_B2 (0xff << 16)
#define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val) (((val) & 0xff) << 16)
#define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16))
/* ECC value (15:8) */
#define LTQ_EBU_NAND_ECC0_ECC_B1 (0xff << 8)
#define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val) (((val) & 0xff) << 8)
#define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8))
/* ECC value (7:0) */
#define LTQ_EBU_NAND_ECC0_ECC_B0 (0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val) (((val) & 0xff) << 0)
#define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff)
#define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0))
/*******************************************************************************
* NAND ECC Address Counter Register
******************************************************************************/
/* Reserved (31:9) */
#define LTQ_EBU_NAND_ECC_AC_RES (0x7fffff << 9)
#define LTQ_EBU_NAND_ECC_AC_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff)
/* ECC address counter (8:0) */
#define LTQ_EBU_NAND_ECC_AC_ECC_AC (0x1ff)
#define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val) (((val) & 0x1ff) << 0)
#define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff)
#define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0))
/*******************************************************************************
* Internal Address Emulation Register
******************************************************************************/
/* Memory Region Base Address (31:12) */
#define LTQ_EBU_EMU_ADDR_BASE (0xfffff << 12)
#define LTQ_EBU_EMU_ADDR_BASE_VAL(val) (((val) & 0xfffff) << 12)
#define LTQ_EBU_EMU_ADDR_BASE_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff)
#define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12))
/* Memory Region Address Mask (7:4) */
#define LTQ_EBU_EMU_ADDR_MASK (0xf << 4)
#define LTQ_EBU_EMU_ADDR_MASK_VAL(val) (((val) & 0xf) << 4)
#define LTQ_EBU_EMU_ADDR_MASK_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf)
#define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4))
/* Memory Region Mirror Segment B Control (1) */
#define LTQ_EBU_EMU_ADDR_MRMB (0x1 << 1)
#define LTQ_EBU_EMU_ADDR_MRMB_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_EMU_ADDR_MRMB_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1)
#define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1))
/* Memory Region Enable Control (0) */
#define LTQ_EBU_EMU_ADDR_MREC (0x1)
#define LTQ_EBU_EMU_ADDR_MREC_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_EMU_ADDR_MREC_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1)
#define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0))
/*******************************************************************************
* nternal Emulator Configuration Register
******************************************************************************/
/* Overlay Memory Control Region 3 (3) */
#define LTQ_EBU_EMU_CON_OVL3 (0x1 << 3)
#define LTQ_EBU_EMU_CON_OVL3_VAL(val) (((val) & 0x1) << 3)
#define LTQ_EBU_EMU_CON_OVL3_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1)
#define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3))
/* Overlay Memory Control Region 2 (2) */
#define LTQ_EBU_EMU_CON_OVL2 (0x1 << 2)
#define LTQ_EBU_EMU_CON_OVL2_VAL(val) (((val) & 0x1) << 2)
#define LTQ_EBU_EMU_CON_OVL2_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1)
#define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2))
/* Overlay Memory Control Region 1 (1) */
#define LTQ_EBU_EMU_CON_OVL1 (0x1 << 1)
#define LTQ_EBU_EMU_CON_OVL1_VAL(val) (((val) & 0x1) << 1)
#define LTQ_EBU_EMU_CON_OVL1_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1)
#define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1))
/* Overlay Memory Control Region 0 (0) */
#define LTQ_EBU_EMU_CON_OVL0 (0x1)
#define LTQ_EBU_EMU_CON_OVL0_VAL(val) (((val) & 0x1) << 0)
#define LTQ_EBU_EMU_CON_OVL0_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1)
#define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0))
#endif /* __LTQ_EBU_H */

2098
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

36
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h Normal file
View File

@@ -0,0 +1,36 @@
/*
* arch/mips/include/asm/mach-lantiq/svip/irq.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2010 Lantiq
*
*/
#ifndef __IRQ_H
#define __IRQ_H
#include <svip_irq.h>
#define NR_IRQS 264
#include_next <irq.h>
/* Functions for EXINT handling */
extern int ifx_enable_external_int(u32 exint, u32 mode);
extern int ifx_disable_external_int(u32 exint);
extern int ifx_external_int_level(u32 exint);
#endif

71
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h Normal file
View File

@@ -0,0 +1,71 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#ifndef _LTQ_SVIP_H__
#define _LTQ_SVIP_H__
#ifdef CONFIG_SOC_SVIP
#include <lantiq.h>
/* Chip IDs */
#define SOC_ID_SVIP 0x169
/* SoC Types */
#define SOC_TYPE_SVIP 0x01
/* ASC0/1 - serial port */
#define LTQ_ASC0_BASE_ADDR 0x14100100
#define LTQ_ASC1_BASE_ADDR 0x14100200
#define LTQ_ASC_SIZE 0x100
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8))
#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2)
#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3)
/* ICU - interrupt control unit */
#define LTQ_ICU_BASE_ADDR 0x14106000
#define LTQ_ICU_BASE_ADDR1 0x14106028
#define LTQ_ICU_BASE_ADDR2 0x1E016000
#define LTQ_ICU_BASE_ADDR3 0x1E016028
#define LTQ_ICU_BASE_ADDR4 0x14106050
#define LTQ_ICU_BASE_ADDR5 0x14106078
#define LTQ_ICU_SIZE 0x100
/* WDT */
#define LTQ_WDT_BASE_ADDR 0x1F8803F0
#define LTQ_WDT_SIZE 0x10
/* Status */
#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500)
#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C))
#define LTQ_EIU_BASE_ADDR 0
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
extern __iomem void *ltq_ebu_membase;
extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen,
bool altsel0, bool altsel1);
extern int ltq_port_get_dir(unsigned int port, unsigned int pin);
extern int ltq_port_get_puden(unsigned int port, unsigned int pin);
extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin);
extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin);
#define ltq_is_ar9() 0
#define ltq_is_vr9() 0
#define ltq_is_falcon() 0
#define BS_FLASH 0
#define LTQ_RST_CAUSE_WDTRST 0x2
#endif /* CONFIG_SOC_SVIP */
#endif /* _LTQ_SVIP_H__ */

242
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h Normal file
View File

@@ -0,0 +1,242 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __MPS_REG_H
#define __MPS_REG_H
#define mbs_r32(reg) ltq_r32(&mbs->reg)
#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg)
#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg)
/** MBS register structure */
struct svip_reg_mbs {
unsigned long reserved0[4];
unsigned long mbsr0; /* 0x0010 */
unsigned long mbsr1; /* 0x0014 */
unsigned long mbsr2; /* 0x0018 */
unsigned long mbsr3; /* 0x001c */
unsigned long mbsr4; /* 0x0020 */
unsigned long mbsr5; /* 0x0024 */
unsigned long mbsr6; /* 0x0028 */
unsigned long mbsr7; /* 0x002c */
unsigned long mbsr8; /* 0x0030 */
unsigned long mbsr9; /* 0x0034 */
unsigned long mbsr10; /* 0x0038 */
unsigned long mbsr11; /* 0x003c */
unsigned long mbsr12; /* 0x0040 */
unsigned long mbsr13; /* 0x0044 */
unsigned long mbsr14; /* 0x0048 */
unsigned long mbsr15; /* 0x004c */
unsigned long mbsr16; /* 0x0050 */
unsigned long mbsr17; /* 0x0054 */
unsigned long mbsr18; /* 0x0058 */
unsigned long mbsr19; /* 0x005c */
unsigned long mbsr20; /* 0x0060 */
unsigned long mbsr21; /* 0x0064 */
unsigned long mbsr22; /* 0x0068 */
unsigned long mbsr23; /* 0x006c */
unsigned long mbsr24; /* 0x0070 */
unsigned long mbsr25; /* 0x0074 */
unsigned long mbsr26; /* 0x0078 */
unsigned long mbsr27; /* 0x007c */
unsigned long mbsr28; /* 0x0080 */
};
/** MPS register structure */
struct svip_reg_mps {
volatile unsigned long mps_swirn0set; /* 0x0000 */
volatile unsigned long mps_swirn0en; /* 0x0004 */
volatile unsigned long mps_swirn0cr; /* 0x0008 */
volatile unsigned long mps_swirn0icr; /* 0x000C */
volatile unsigned long mps_swirn1set; /* 0x0010 */
volatile unsigned long mps_swirn1en; /* 0x0014 */
volatile unsigned long mps_swirn1cr; /* 0x0018 */
volatile unsigned long mps_swirn1icr; /* 0x001C */
volatile unsigned long mps_swirn2set; /* 0x0020 */
volatile unsigned long mps_swirn2en; /* 0x0024 */
volatile unsigned long mps_swirn2cr; /* 0x0028 */
volatile unsigned long mps_swirn2icr; /* 0x002C */
volatile unsigned long mps_swirn3set; /* 0x0030 */
volatile unsigned long mps_swirn3en; /* 0x0034 */
volatile unsigned long mps_swirn3cr; /* 0x0038 */
volatile unsigned long mps_swirn3icr; /* 0x003C */
volatile unsigned long mps_swirn4set; /* 0x0040 */
volatile unsigned long mps_swirn4en; /* 0x0044 */
volatile unsigned long mps_swirn4cr; /* 0x0048 */
volatile unsigned long mps_swirn4icr; /* 0x004C */
volatile unsigned long mps_swirn5set; /* 0x0050 */
volatile unsigned long mps_swirn5en; /* 0x0054 */
volatile unsigned long mps_swirn5cr; /* 0x0058 */
volatile unsigned long mps_swirn5icr; /* 0x005C */
volatile unsigned long mps_swirn6set; /* 0x0060 */
volatile unsigned long mps_swirn6en; /* 0x0064 */
volatile unsigned long mps_swirn6cr; /* 0x0068 */
volatile unsigned long mps_swirn6icr; /* 0x006C */
volatile unsigned long mps_swirn7set; /* 0x0070 */
volatile unsigned long mps_swirn7en; /* 0x0074 */
volatile unsigned long mps_swirn7cr; /* 0x0078 */
volatile unsigned long mps_swirn7icr; /* 0x007C */
volatile unsigned long mps_swirn8set; /* 0x0080 */
volatile unsigned long mps_swirn8en; /* 0x0084 */
volatile unsigned long mps_swirn8cr; /* 0x0088 */
volatile unsigned long mps_swirn8icr; /* 0x008C */
};
/* Software Interrupt */
#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000))
#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004))
#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008))
#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C))
#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010))
#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014))
#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018))
#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C))
#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020))
#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024))
#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028))
#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C))
#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030))
#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034))
#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038))
#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C))
#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040))
#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044))
#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048))
#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C))
#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050))
#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054))
#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058))
#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C))
#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060))
#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064))
#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068))
#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C))
#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070))
#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074))
#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078))
#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C))
#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080))
#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084))
#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C))
#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088))
/*******************************************************************************
* MPS_SWIRNSET Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5)
#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5)
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4)
#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4)
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3)
#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3)
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2)
#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2)
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1)
#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1)
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNSET_IR0 (0x1)
#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0)
#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0)
/*******************************************************************************
* MPS_SWIRNEN Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5)
#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1)
#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5))
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4)
#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1)
#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4))
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3)
#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1)
#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3))
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2)
#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1)
#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2))
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1)
#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1)
#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1))
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNEN_IR0 (0x1)
#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0)
#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1)
#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0))
/*******************************************************************************
* MPS_SWIRNICR Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1)
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1)
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1)
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1)
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1)
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNICR_IR0 (0x1)
#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1)
/*******************************************************************************
* MPS_SWIRNCR Register
******************************************************************************/
/* Software Interrupt Request IR5 (5) */
#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5)
#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1)
/* Software Interrupt Request IR4 (4) */
#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4)
#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1)
/* Software Interrupt Request IR3 (3) */
#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3)
#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1)
/* Software Interrupt Request IR2 (2) */
#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2)
#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1)
/* Software Interrupt Request IR1 (1) */
#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1)
#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1)
/* Software Interrupt Request IR0 (0) */
#define IFX_MPS_SWIRNCR_IR0 (0x1)
#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1)
#endif

3262
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

624
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h Normal file
View File

@@ -0,0 +1,624 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SSC_REG_H
#define __SSC_REG_H
/** SSC register structure */
struct svip_reg_ssc {
volatile unsigned long clc; /* 0x00 */
volatile unsigned long pisel; /* 0x04 */
volatile unsigned long id; /* 0x08 */
volatile unsigned long reserved0; /* 0x0c */
volatile unsigned long mcon; /* 0x10 */
volatile unsigned long state; /* 0x14 */
volatile unsigned long whbstate; /* 0x18 */
volatile unsigned long reserved1; /* 0x1c */
volatile unsigned long tb; /* 0x20 */
volatile unsigned long rb; /* 0x24 */
volatile unsigned long reserved2[2]; /* 0x28 */
volatile unsigned long rxfcon; /* 0x30 */
volatile unsigned long txfcon; /* 0x34 */
volatile unsigned long fstat; /* 0x38 */
volatile unsigned long reserved3; /* 0x3c */
volatile unsigned long br; /* 0x40 */
volatile unsigned long brstat; /* 0x44 */
volatile unsigned long reserved4[6]; /* 0x48 */
volatile unsigned long sfcon; /* 0x60 */
volatile unsigned long sfstat; /* 0x64 */
volatile unsigned long reserved5[2]; /* 0x68 */
volatile unsigned long gpocon; /* 0x70 */
volatile unsigned long gpostat; /* 0x74 */
volatile unsigned long whbgpostat; /* 0x78 */
volatile unsigned long reserved6; /* 0x7c */
volatile unsigned long rxreq; /* 0x80 */
volatile unsigned long rxcnt; /* 0x84 */
volatile unsigned long reserved7[25]; /* 0x88 */
volatile unsigned long dma_con; /* 0xEC */
volatile unsigned long reserved8; /* 0xf0 */
volatile unsigned long irnen; /* 0xF4 */
volatile unsigned long irncr; /* 0xF8 */
volatile unsigned long irnicr; /* 0xFC */
};
/*******************************************************************************
* CLC Register
******************************************************************************/
/* Clock Divider for Sleep Mode (23:16) */
#define SSC_CLC_SMC (0xff << 16)
#define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16)
#define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff)
#define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16))
/* Clock Divider for Normal Run Mode (15:8) */
#define SSC_CLC_RMC (0xff << 8)
#define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8)
#define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff)
#define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8))
/* Fast Shut-Off Enable Bit (5) */
#define SSC_CLC_FSOE (0x1 << 5)
#define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5)
#define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1)
#define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5))
/* Suspend Bit Write Enable for OCDS (4) */
#define SSC_CLC_SBWE (0x1 << 4)
#define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4)
#define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4)
/* External Request Disable (3) */
#define SSC_CLC_EDIS (0x1 << 3)
#define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3)
#define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1)
#define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3))
/* Suspend Enable Bit for OCDS (2) */
#define SSC_CLC_SPEN (0x1 << 2)
#define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2)
#define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1)
#define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2))
/* Disable Status Bit (1) */
#define SSC_CLC_DISS (0x1 << 1)
#define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1)
/* Disable Request Bit (0) */
#define SSC_CLC_DISR (0x1)
#define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0)
#define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1)
#define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0))
/*******************************************************************************
* ID Register
******************************************************************************/
/* Transmit FIFO Size (29:24) */
#define SSC_ID_TXFS (0x3f << 24)
#define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f)
/* Receive FIFO Size (21:16) */
#define SSC_ID_RXFS (0x3f << 16)
#define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f)
/* Module ID (15:8) */
#define SSC_ID_ID (0xff << 8)
#define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff)
/* Configuration (5) */
#define SSC_ID_CFG (0x1 << 5)
#define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1)
/* Revision (4:0) */
#define SSC_ID_REV (0x1f)
#define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f)
/*******************************************************************************
* MCON Register
******************************************************************************/
/* Echo Mode (24) */
#define SSC_MCON_EM (0x1 << 24)
#define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24)
#define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1)
#define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24))
/* Idle Bit Value (23) */
#define SSC_MCON_IDLE (0x1 << 23)
#define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23)
#define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1)
#define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23))
/* Enable Byte Valid Control (22) */
#define SSC_MCON_ENBV (0x1 << 22)
#define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22)
#define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1)
#define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22))
/* Data Width Selection (20:16) */
#define SSC_MCON_BM (0x1f << 16)
#define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16)
#define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f)
#define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16))
/* Receive Underflow Error Enable (12) */
#define SSC_MCON_RUEN (0x1 << 12)
#define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12)
#define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1)
#define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12))
/* Transmit Underflow Error Enable (11) */
#define SSC_MCON_TUEN (0x1 << 11)
#define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11)
#define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1)
#define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11))
/* Abort Error Enable (10) */
#define SSC_MCON_AEN (0x1 << 10)
#define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10)
#define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1)
#define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10))
/* Receive Overflow Error Enable (9) */
#define SSC_MCON_REN (0x1 << 9)
#define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9)
#define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1)
#define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9))
/* Transmit Overflow Error Enable (8) */
#define SSC_MCON_TEN (0x1 << 8)
#define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8)
#define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1)
#define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8))
/* Loop Back Control (7) */
#define SSC_MCON_LB (0x1 << 7)
#define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7)
#define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1)
#define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7))
/* Clock Polarity Control (6) */
#define SSC_MCON_PO (0x1 << 6)
#define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6)
#define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1)
#define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6))
/* Clock Phase Control (5) */
#define SSC_MCON_PH (0x1 << 5)
#define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5)
#define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1)
#define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5))
/* Heading Control (4) */
#define SSC_MCON_HB (0x1 << 4)
#define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4)
#define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1)
#define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4))
/* Chip Select Enable (3) */
#define SSC_MCON_CSBEN (0x1 << 3)
#define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3)
#define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1)
#define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3))
/* Chip Select Invert (2) */
#define SSC_MCON_CSBINV (0x1 << 2)
#define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2)
#define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1)
#define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2))
/* Receive Off (1) */
#define SSC_MCON_RXOFF (0x1 << 1)
#define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1)
#define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1)
#define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1))
/* Transmit Off (0) */
#define SSC_MCON_TXOFF (0x1)
#define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0)
#define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1)
#define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0))
/*******************************************************************************
* STATE Register
******************************************************************************/
/* Receive End-of-Message (31) */
#define SSC_STATE_RXEOM (0x1 << 31)
#define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1)
/* Receive Byte Valid (30:28) */
#define SSC_STATE_RXBV (0x7 << 28)
#define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7)
/* Transmit End-of-Message (27) */
#define SSC_STATE_TXEOM (0x1 << 27)
#define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1)
/* Transmit Byte Valid (26:24) */
#define SSC_STATE_TXBV (0x7 << 24)
#define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7)
/* Bit Count Field (20:16) */
#define SSC_STATE_BC (0x1f << 16)
#define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f)
/* Busy Flag (13) */
#define SSC_STATE_BSY (0x1 << 13)
#define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1)
/* Receive Underflow Error Flag (12) */
#define SSC_STATE_RUE (0x1 << 12)
#define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1)
/* Transmit Underflow Error Flag (11) */
#define SSC_STATE_TUE (0x1 << 11)
#define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1)
/* Abort Error Flag (10) */
#define SSC_STATE_AE (0x1 << 10)
#define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1)
/* Receive Error Flag (9) */
#define SSC_STATE_RE (0x1 << 9)
#define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1)
/* Transmit Error Flag (8) */
#define SSC_STATE_TE (0x1 << 8)
#define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1)
/* Mode Error Flag (7) */
#define SSC_STATE_ME (0x1 << 7)
#define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1)
/* Slave Selected (2) */
#define SSC_STATE_SSEL (0x1 << 2)
#define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1)
/* Master Select Bit (1) */
#define SSC_STATE_MS (0x1 << 1)
#define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1)
/* Enable Bit (0) */
#define SSC_STATE_EN (0x1)
#define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1)
/*******************************************************************************
* WHBSTATE Register
******************************************************************************/
/* Set Transmit Underflow Error Flag Bit (15) */
#define SSC_WHBSTATE_SETTUE (0x1 << 15)
#define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15)
#define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15)
/* Set Abort Error Flag Bit (14) */
#define SSC_WHBSTATE_SETAE (0x1 << 14)
#define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14)
#define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14)
/* Set Receive Error Flag Bit (13) */
#define SSC_WHBSTATE_SETRE (0x1 << 13)
#define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13)
#define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13)
/* Set Transmit Error Flag Bit (12) */
#define SSC_WHBSTATE_SETTE (0x1 << 12)
#define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12)
#define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12)
/* Clear Transmit Underflow Error Flag Bit (11) */
#define SSC_WHBSTATE_CLRTUE (0x1 << 11)
#define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11)
#define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11)
/* Clear Abort Error Flag Bit (10) */
#define SSC_WHBSTATE_CLRAE (0x1 << 10)
#define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10)
#define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10)
/* Clear Receive Error Flag Bit (9) */
#define SSC_WHBSTATE_CLRRE (0x1 << 9)
#define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9)
#define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9)
/* Clear Transmit Error Flag Bit (8) */
#define SSC_WHBSTATE_CLRTE (0x1 << 8)
#define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8)
#define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8)
/* Set Mode Error Flag Bit (7) */
#define SSC_WHBSTATE_SETME (0x1 << 7)
#define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7)
#define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7)
/* Clear Mode Error Flag Bit (6) */
#define SSC_WHBSTATE_CLRME (0x1 << 6)
#define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6)
#define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6)
/* Set Receive Underflow Error Bit (5) */
#define SSC_WHBSTATE_SETRUE (0x1 << 5)
#define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5)
#define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5)
/* Clear Receive Underflow Error Bit (4) */
#define SSC_WHBSTATE_CLRRUE (0x1 << 4)
#define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4)
#define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4)
/* Set Master Select Bit (3) */
#define SSC_WHBSTATE_SETMS (0x1 << 3)
#define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3)
#define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3)
/* Clear Master Select Bit (2) */
#define SSC_WHBSTATE_CLRMS (0x1 << 2)
#define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2)
#define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2)
/* Set Enable Bit (1) */
#define SSC_WHBSTATE_SETEN (0x1 << 1)
#define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1)
#define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1)
/* Clear Enable Bit (0) */
#define SSC_WHBSTATE_CLREN (0x1)
#define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0)
#define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0)
/*******************************************************************************
* TB Register
******************************************************************************/
/* Transmit Data Register Value (31:0) */
#define SSC_TB_TB_VAL (0xFFFFFFFFL)
#define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0)
#define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL)
#define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0))
/*******************************************************************************
* RB Register
******************************************************************************/
/* Receive Data Register Value (31:0) */
#define SSC_RB_RB_VAL (0xFFFFFFFFL)
#define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL)
/*******************************************************************************
* FSTAT Register
******************************************************************************/
/* Transmit FIFO Filling Level (13:8) */
#define SSC_FSTAT_TXFFL (0x3f << 8)
#define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f)
/* Receive FIFO Filling Level (5:0) */
#define SSC_FSTAT_RXFFL (0x3f)
#define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f)
/*******************************************************************************
* PISEL Register
******************************************************************************/
/* Slave Mode Clock Input Select (2) */
#define SSC_PISEL_CIS (0x1 << 2)
#define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2)
#define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1)
#define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2))
/* Slave Mode Receiver Input Select (1) */
#define SSC_PISEL_SIS (0x1 << 1)
#define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1)
#define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1)
#define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1))
/* Master Mode Receiver Input Select (0) */
#define SSC_PISEL_MIS (0x1)
#define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0)
#define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1)
#define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0))
/*******************************************************************************
* RXFCON Register
******************************************************************************/
/* Receive FIFO Interrupt Trigger Level (13:8) */
#define SSC_RXFCON_RXFITL (0x3f << 8)
#define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8)
#define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f)
#define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8))
/* Receive FIFO Flush (1) */
#define SSC_RXFCON_RXFLU (0x1 << 1)
#define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1)
#define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1)
/* Receive FIFO Enable (0) */
#define SSC_RXFCON_RXFEN (0x1)
#define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0)
#define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1)
#define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* TXFCON Register
******************************************************************************/
/* Transmit FIFO Interrupt Trigger Level (13:8) */
#define SSC_TXFCON_TXFITL (0x3f << 8)
#define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8)
#define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f)
#define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8))
/* Transmit FIFO Flush (1) */
#define SSC_TXFCON_TXFLU (0x1 << 1)
#define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1)
#define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1)
/* Transmit FIFO Enable (0) */
#define SSC_TXFCON_TXFEN (0x1)
#define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0)
#define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1)
#define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* BR Register
******************************************************************************/
/* Baudrate Timer Reload Register Value (15:0) */
#define SSC_BR_BR_VAL (0xffff)
#define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0)
#define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff)
#define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0))
/*******************************************************************************
* BRSTAT Register
******************************************************************************/
/* Baudrate Timer Register Value (15:0) */
#define SSC_BRSTAT_BT_VAL (0xffff)
#define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff)
/*******************************************************************************
* SFCON Register
******************************************************************************/
/* Pause Length (31:22) */
#define SSC_SFCON_PLEN (0x3ff << 22)
#define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22)
#define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff)
#define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22))
/* Stop After Pause (20) */
#define SSC_SFCON_STOP (0x1 << 20)
#define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20)
#define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1)
#define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20))
/* Idle Clock Configuration (19:18) */
#define SSC_SFCON_ICLK (0x3 << 18)
#define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18)
#define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3)
#define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18))
/* Idle Data Configuration (17:16) */
#define SSC_SFCON_IDAT (0x3 << 16)
#define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16)
#define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3)
#define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16))
/* Data Length (15:4) */
#define SSC_SFCON_DLEN (0xfff << 4)
#define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4)
#define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff)
#define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4))
/* Enable Interrupt After Pause (3) */
#define SSC_SFCON_IAEN (0x1 << 3)
#define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3)
#define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1)
#define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3))
/* Enable Interrupt Before Pause (2) */
#define SSC_SFCON_IBEN (0x1 << 2)
#define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2)
#define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1)
#define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2))
/* Serial Frame Enable (0) */
#define SSC_SFCON_SFEN (0x1)
#define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0)
#define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1)
#define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0))
/*******************************************************************************
* SFSTAT Register
******************************************************************************/
/* Pause Count (31:22) */
#define SSC_SFSTAT_PCNT (0x3ff << 22)
#define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff)
/* Data Bit Count (15:4) */
#define SSC_SFSTAT_DCNT (0xfff << 4)
#define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff)
/* Pause Busy (1) */
#define SSC_SFSTAT_PBSY (0x1 << 1)
#define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1)
/* Data Busy (0) */
#define SSC_SFSTAT_DBSY (0x1)
#define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1)
/*******************************************************************************
* GPOCON Register
******************************************************************************/
/* Output OUTn Is Chip Select (15:8) */
#define SSC_GPOCON_ISCSBN (0xff << 8)
#define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8)
#define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff)
#define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8))
/* Invert Output OUTn (7:0) */
#define SSC_GPOCON_INVOUTN (0xff)
#define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0)
#define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff)
#define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0))
/*******************************************************************************
* GPOSTAT Register
******************************************************************************/
/* Output Register Bit n (7:0) */
#define SSC_GPOSTAT_OUTN (0xff)
#define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff)
/*******************************************************************************
* WHBGPOSTAT
******************************************************************************/
/* Set Output Register Bit n (15:8) */
#define SSC_WHBGPOSTAT_SETOUTN (0xff << 8)
#define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8)
#define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8)
/* Clear Output Register Bit n (7:0) */
#define SSC_WHBGPOSTAT_CLROUTN (0xff)
#define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0)
#define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0)
/*******************************************************************************
* RXREQ Register
******************************************************************************/
/* Receive Count Value (15:0) */
#define SSC_RXREQ_RXCNT (0xffff)
#define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0)
#define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff)
#define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0))
/*******************************************************************************
* RXCNT Register
******************************************************************************/
/* Receive To Do Value (15:0) */
#define SSC_RXCNT_TODO (0xffff)
#define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff)
/*******************************************************************************
* DMA_CON Register
******************************************************************************/
/* Receive Class (3:2) */
#define SSC_DMA_CON_RXCLS (0x3 << 2)
#define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2)
#define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3)
#define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2))
/* Transmit Path On (1) */
#define SSC_DMA_CON_TXON (0x1 << 1)
#define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1)
#define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1)
#define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1))
/* Receive Path On (0) */
#define SSC_DMA_CON_RXON (0x1)
#define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0)
#define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1)
#define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0))
/*******************************************************************************
* IRNEN Register
******************************************************************************/
/* Frame End Interrupt Request Enable (3) */
#define SSC_IRNEN_F (0x1 << 3)
#define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3)
#define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1)
#define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3))
/* Error Interrupt Request Enable (2) */
#define SSC_IRNEN_E (0x1 << 2)
#define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2)
#define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1)
#define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2))
/* Receive Interrupt Request Enable (1) */
#define SSC_IRNEN_R (0x1 << 1)
#define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1)
#define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1)
#define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1))
/* Transmit Interrupt Request Enable (0) */
#define SSC_IRNEN_T (0x1)
#define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0)
#define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1)
#define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0))
/*******************************************************************************
* IRNICR Register
******************************************************************************/
/* Frame End Interrupt Request (3) */
#define SSC_IRNICR_F (0x1 << 3)
#define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1)
/* Error Interrupt Request (2) */
#define SSC_IRNICR_E (0x1 << 2)
#define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1)
/* Receive Interrupt Request (1) */
#define SSC_IRNICR_R (0x1 << 1)
#define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1)
/* Transmit Interrupt Request (0) */
#define SSC_IRNICR_T (0x1)
#define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1)
/*******************************************************************************
* IRNCR Register
******************************************************************************/
/* Frame End Interrupt Request (3) */
#define SSC_IRNCR_F (0x1 << 3)
#define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1)
/* Error Interrupt Request (2) */
#define SSC_IRNCR_E (0x1 << 2)
#define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1)
/* Receive Interrupt Request (1) */
#define SSC_IRNCR_R (0x1 << 1)
#define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1)
/* Transmit Interrupt Request (0) */
#define SSC_IRNCR_T (0x1)
#define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1)
#endif /* __SSC_H */

130
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h Normal file
View File

@@ -0,0 +1,130 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __STATUS_REG_H
#define __STATUS_REG_H
#define status_r32(reg) ltq_r32(&status->reg)
#define status_w32(val, reg) ltq_w32(val, &status->reg)
#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg)
/** STATUS register structure */
struct svip_reg_status {
unsigned long fuse_deu; /* 0x0000 */
unsigned long fuse_cpu; /* 0x0004 */
unsigned long fuse_pll; /* 0x0008 */
unsigned long chipid; /* 0x000C */
unsigned long config; /* 0x0010 */
unsigned long chip_loc; /* 0x0014 */
unsigned long fuse_spare; /* 0x0018 */
};
/*******************************************************************************
* Fuse for DEU Settings
******************************************************************************/
/* Fuse for Enabling the TRNG (6) */
#define STATUS_FUSE_DEU_TRNG (0x1 << 6)
#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1)
/* Fuse for Enabling the DES Submodule (5) */
#define STATUS_FUSE_DEU_DES (0x1 << 5)
#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1)
/* Fuse for Enabling the 3DES Submodule (4) */
#define STATUS_FUSE_DEU_3DES (0x1 << 4)
#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1)
/* Fuse for Enabling the AES Submodule (3) */
#define STATUS_FUSE_DEU_AES (0x1 << 3)
#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1)
/* Fuse for Enabling the HASH Submodule (2) */
#define STATUS_FUSE_DEU_HASH (0x1 << 2)
#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1)
/* Fuse for Enabling the ARC4 Submodule (1) */
#define STATUS_FUSE_DEU_ARC4 (0x1 << 1)
#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1)
/* Fuse for Enabling the DEU Module (0) */
#define STATUS_FUSE_DEU_DEU (0x1)
#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1)
/*******************************************************************************
* Fuse for CPU Settings
******************************************************************************/
/* Fuse for Enabling CPU5 (5) */
#define STATUS_FUSE_CPU_CPU5 (0x1 << 5)
#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1)
/* Fuse for Enabling the CPU4 (4) */
#define STATUS_FUSE_CPU_CPU4 (0x1 << 4)
#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1)
/* Fuse for Enabling the CPU3 (3) */
#define STATUS_FUSE_CPU_CPU3 (0x1 << 3)
#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1)
/* Fuse for Enabling the CPU2 (2) */
#define STATUS_FUSE_CPU_CPU2 (0x1 << 2)
#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1)
/* Fuse for Enabling the CPU1 (1) */
#define STATUS_FUSE_CPU_CPU1 (0x1 << 1)
#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1)
/* Fuse for Enabling the CPU0 (0) */
#define STATUS_FUSE_CPU_CPU0 (0x1)
#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1)
/*******************************************************************************
* Fuse for PLL Settings
******************************************************************************/
/* Fuse for Enabling PLL (7:0) */
#define STATUS_FUSE_PLL_PLL (0xff)
#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff)
/*******************************************************************************
* Chip Identification Register
******************************************************************************/
/* Chip Version Number (31:28) */
#define STATUS_CHIPID_VERSION (0xf << 28)
#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf)
/* Part Number (27:12) */
#define STATUS_CHIPID_PART_NUMBER (0xffff << 12)
#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff)
/* Manufacturer ID (11:1) */
#define STATUS_CHIPID_MANID (0x7ff << 1)
#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff)
/*******************************************************************************
* Chip Configuration Register
******************************************************************************/
/* Number of Analog Channels (8:5) */
#define STATUS_CONFIG_ANA_CHAN (0xf << 5)
#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf)
/* Clock Mode (4) */
#define STATUS_CONFIG_CLK_MODE (0x1 << 1)
#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1)
/* Subversion Number (3:0) */
#define STATUS_CONFIG_SUB_VERS (0xF)
#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF)
/*******************************************************************************
* Chip Location Register
******************************************************************************/
/* Chip Lot ID (31:16) */
#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16)
#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff)
/* Chip X Coordinate (15:8) */
#define STATUS_CHIP_LOC_CHIP_X (0xff << 8)
#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff)
/* Chip Y Coordinate (7:0) */
#define STATUS_CHIP_LOC_CHIP_Y (0xff)
#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff)
#endif

245
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h Normal file
View File

@@ -0,0 +1,245 @@
/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#ifndef __SVIP_DMA_H
#define __SVIP_DMA_H
#define LTQ_DMA_CH_ON 1
#define LTQ_DMA_CH_OFF 0
#define LTQ_DMA_CH_DEFAULT_WEIGHT 100;
#define DMA_OWN 1
#define CPU_OWN 0
#define DMA_MAJOR 250
/* Descriptors */
#define DMA_DESC_OWN_CPU 0x0
#define DMA_DESC_OWN_DMA 0x80000000
#define DMA_DESC_CPT_SET 0x40000000
#define DMA_DESC_SOP_SET 0x20000000
#define DMA_DESC_EOP_SET 0x10000000
struct rx_desc {
union {
struct {
#ifdef CONFIG_CPU_LITTLE_ENDIAN
volatile u32 data_length:16;
volatile u32 reserve2:7;
volatile u32 byte_offset:2;
volatile u32 reserve1:3;
volatile u32 eop:1;
volatile u32 sop:1;
volatile u32 c:1;
volatile u32 own:1;
#else
volatile u32 own:1;
volatile u32 c:1;
volatile u32 sop:1;
volatile u32 eop:1;
volatile u32 reserve1:3;
volatile u32 byte_offset:2;
volatile u32 reserve2:7;
volatile u32 data_length:16;
#endif
} field;
volatile u32 word;
} status;
volatile u32 data_pointer;
};
struct tx_desc {
union {
struct {
#ifdef CONFIG_CPU_LITTLE_ENDIAN
volatile u32 data_length:16;
volatile u32 reserved:7;
volatile u32 byte_offset:5;
volatile u32 eop:1;
volatile u32 sop:1;
volatile u32 c:1;
volatile u32 own:1;
#else
volatile u32 own:1;
volatile u32 c:1;
volatile u32 sop:1;
volatile u32 eop:1;
volatile u32 byte_offset:5;
volatile u32 reserved:7;
volatile u32 data_length:16;
#endif
} field;
volatile u32 word;
} status;
volatile u32 data_pointer;
};
/* DMA pseudo interrupts notified to switch driver */
#define RCV_INT 0x01
#define TX_BUF_FULL_INT 0x02
#define TRANSMIT_CPT_INT 0x04
#define CHANNEL_CLOSED 0x10
/* Parameters for switch DMA device */
#define DEFAULT_SW_CHANNEL_WEIGHT 3
#define DEFAULT_SW_PORT_WEIGHT 7
#define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SW_TX_CHANNEL_NUM 4
#define DEFAULT_SW_RX_CHANNEL_NUM 4
#define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20
#define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20
/* Parameters for SSC DMA device */
#define DEFAULT_SSC_CHANNEL_WEIGHT 3
#define DEFAULT_SSC_PORT_WEIGHT 7
#define DEFAULT_SSC_TX_CHANNEL_CLASS 3
#define DEFAULT_SSC_RX_CHANNEL_CLASS 0
#define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
#define DEFAULT_SSC0_TX_CHANNEL_NUM 1
#define DEFAULT_SSC0_RX_CHANNEL_NUM 1
#define DEFAULT_SSC1_TX_CHANNEL_NUM 1
#define DEFAULT_SSC1_RX_CHANNEL_NUM 1
#define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10
#define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10
/* Parameters for memory DMA device */
#define DEFAULT_MEM_CHANNEL_WEIGHT 3
#define DEFAULT_MEM_PORT_WEIGHT 7
#define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_MEM_TX_CHANNEL_NUM 1
#define DEFAULT_MEM_RX_CHANNEL_NUM 1
#define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2
#define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2
/* Parameters for DEU DMA device */
#define DEFAULT_DEU_CHANNEL_WEIGHT 1
#define DEFAULT_DEU_PORT_WEIGHT 1
#define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
#define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20
#define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20
#define DMA_DESCR_NUM 30 /* number of descriptors per channel */
enum dma_dir_t {
DIR_RX = 0,
DIR_TX = 1,
};
struct dma_device_info;
struct dma_channel_info {
/*Pointer to the peripheral device who is using this channel*/
/*const*/ struct dma_device_info *dma_dev;
/*direction*/
const enum dma_dir_t dir; /*RX or TX*/
/*class for this channel for QoS*/
int pri;
/*irq number*/
const int irq;
/*relative channel number*/
const int rel_chan_no;
/*absolute channel number*/
int abs_chan_no;
/*specify byte_offset*/
int byte_offset;
int tx_weight;
/*descriptor parameter*/
int desc_base;
int desc_len;
int curr_desc;
int prev_desc;/*only used if it is a tx channel*/
/*weight setting for WFQ algorithm*/
int weight;
int default_weight;
int packet_size;
/*status of this channel*/
int control; /*on or off*/
int xfer_cnt;
int dur; /*descriptor underrun*/
/**optional information for the upper layer devices*/
void *opt[DMA_DESCR_NUM];
/*channel operations*/
int (*open)(struct dma_channel_info *ch);
int (*close)(struct dma_channel_info *ch);
int (*reset)(struct dma_channel_info *ch);
void (*enable_irq)(struct dma_channel_info *ch);
void (*disable_irq)(struct dma_channel_info *ch);
};
struct dma_device_info {
/*device name of this peripheral*/
const char device_name[16];
const int max_rx_chan_num;
const int max_tx_chan_num;
int drop_enable;
int reserved;
int tx_burst_len;
int rx_burst_len;
int tx_weight;
int current_tx_chan;
int current_rx_chan;
int num_tx_chan;
int num_rx_chan;
int tx_endianness_mode;
int rx_endianness_mode;
struct dma_channel_info *tx_chan[4];
struct dma_channel_info *rx_chan[4];
/*functions, optional*/
u8 *(*buffer_alloc)(int len,int *offset, void **opt);
void (*buffer_free)(u8 *dataptr, void *opt);
int (*intr_handler)(struct dma_device_info *dma_dev, int status);
/* used by peripheral driver only */
void *priv;
};
struct dma_device_info *dma_device_reserve(char *dev_name);
int dma_device_release(struct dma_device_info *dma_dev);
int dma_device_register(struct dma_device_info *dma_dev);
int dma_device_unregister(struct dma_device_info *dma_dev);
int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt);
int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr,
int len, void *opt);
#endif

35
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2010 Lantiq
*/
#ifndef __SVIP_IRQ_H
#define __SVIP_IRQ_H
#define IM_NUM 6
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160)
#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2)
#endif

467
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h Normal file
View File

@@ -0,0 +1,467 @@
/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#ifndef __SVIP_MUX_H
#define __SVIP_MUX_H
#define LTQ_MUX_P0_PINS 20
#define LTQ_MUX_P1_PINS 20
#define LTQ_MUX_P2_PINS 19
#define LTQ_MUX_P3_PINS 20
#define LTQ_MUX_P4_PINS 24
struct ltq_mux_pin {
int dirin;
int puen;
int altsel0;
int altsel1;
};
struct ltq_mux_settings {
const struct ltq_mux_pin *mux_p0;
const struct ltq_mux_pin *mux_p1;
const struct ltq_mux_pin *mux_p2;
const struct ltq_mux_pin *mux_p3;
const struct ltq_mux_pin *mux_p4;
};
#define LTQ_MUX_P0_19_EXINT16 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_18_EJ_BRKIN { 1, 0, 0, 0 }
#define LTQ_MUX_P0_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_17_EXINT10 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_17 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_17_ASC1_RXD { 1, 0, 1, 0 }
#define LTQ_MUX_P0_16_EXINT9 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_16 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_16_ASC1_TXD { 0, 0, 1, 0 }
#define LTQ_MUX_P0_15_EXINT8 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_15 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_15_ASC0_RXD { 1, 0, 1, 0 }
#define LTQ_MUX_P0_14_EXINT7 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_14 { 0, 0, 0, 0 }
#define LTQ_MUX_P0_14_ASC0_TXD { 1, 0, 1, 0 }
#define LTQ_MUX_P0_13_SSC0_CS7 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_13_EXINT6 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_13 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_13_SSC1_CS7 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_13_SSC1_INT { 0, 0, 1, 1 }
#define LTQ_MUX_P0_12_SSC0_CS6 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_12_EXINT5 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_12 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_12_SSC1_CS6 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_11_SSC0_CS5 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_11_EXINT4 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_11 { 1, 0, 0, 0 }
#define LTQ_MUX_P0_11_SSC1_CS5 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_10_SSC0_CS4 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_10_EXINT3 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_10_SSC1_CS4 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_9_SSC0_CS3 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_9_EXINT2 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_9_SSC1_CS3 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_8_SSC0_CS2 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_8_EXINT1 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_8_SSC1_CS2 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_7_SSC0_CS1 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_7_EXINT0 { 1, 0, 1, 0 }
#define LTQ_MUX_P0_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_7_SSC1_CS1 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_7_SSC1_CS0 { 1, 0, 0, 1 }
#define LTQ_MUX_P0_7_SSC2_CS0 { 1, 0, 1, 1 }
#define LTQ_MUX_P0_6_SSC0_CS0 { 0, 1, 0, 0 }
#define LTQ_MUX_P0_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_6_SSC1_CS0 { 0, 0, 0, 1 }
#define LTQ_MUX_P0_5_SSC1_SCLK { 0, 0, 0, 0 }
#define LTQ_MUX_P0_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_5_SSC2_CLK { 1, 0, 0, 1 }
#define LTQ_MUX_P0_4_SSC1_MRST { 1, 0, 0, 0 }
#define LTQ_MUX_P0_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_4_SSC2_MRST { 0, 0, 0, 1 }
#define LTQ_MUX_P0_3_SSC1_MTSR { 0, 0, 0, 0 }
#define LTQ_MUX_P0_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_3_SSC2_MTSR { 0, 0, 0, 1 }
#define LTQ_MUX_P0_2_SSC0_SCLK { 0, 0, 0, 0 }
#define LTQ_MUX_P0_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_1_SSC0_MRST { 1, 0, 0, 0 }
#define LTQ_MUX_P0_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P0_0_SSC0_MTSR { 0, 0, 0, 0 }
#define LTQ_MUX_P0_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P0_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_19_PCM3_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_19_EXINT15 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_18_PCM3_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_18_EXINT11 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_17_PCM3_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_17_EXINT12 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_16_PCM3_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_16_EXINT13 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_15_PCM3_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_15_EXINT14 { 1, 0, 1, 0 }
#define LTQ_MUX_P1_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_14_PCM2_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_13_PCM2_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_12_PCM2_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_11_PCM2_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_10_PCM2_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_9_PCM1_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_9_IN { 0, 0, 1, 0 }
#define LTQ_MUX_P1_8_PCM1_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_7_PCM1_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_6_PCM1_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_5_PCM1_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_4_PCM0_TC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P1_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_3_PCM0_FSC { 0, 0, 0, 0 }
#define LTQ_MUX_P1_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_2_PCM0_PCL { 0, 0, 0, 0 }
#define LTQ_MUX_P1_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_1_PCM0_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P1_0_PCM0_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P1_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P1_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_18_EBU_BC1 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_17_EBU_BC0 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_17_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_16_EBU_RDBY { 1, 0, 0, 0 }
#define LTQ_MUX_P2_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_16_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_15_EBU_WAIT { 1, 0, 0, 0 }
#define LTQ_MUX_P2_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_15_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_14_EBU_ALE { 0, 0, 0, 0 }
#define LTQ_MUX_P2_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_13_EBU_WR { 0, 0, 0, 0 }
#define LTQ_MUX_P2_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_12_EBU_RD { 0, 0, 0, 0 }
#define LTQ_MUX_P2_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_11_EBU_A11 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_10_EBU_A10 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_9_EBU_A9 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_9_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_8_EBU_A8 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_7_EBU_A7 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_6_EBU_A6 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_5_EBU_A5 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_4_EBU_A4 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_3_EBU_A3 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_2_EBU_A2 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_1_EBU_A1 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P2_0_EBU_A0 { 0, 0, 0, 0 }
#define LTQ_MUX_P2_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P2_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_19_EBU_CS3 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_19_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_18_EBU_CS2 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_17_EBU_CS1 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_17_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_16_EBU_CS0 { 0, 0, 0, 0 }
#define LTQ_MUX_P3_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_16_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_15_EBU_AD15 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_15_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_14_EBU_AD14 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_13_EBU_AD13 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_12_EBU_AD12 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_11_EBU_AD11 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_10_EBU_AD10 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_9_EBU_AD9 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_9_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_8_EBU_AD8 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_7_EBU_AD7 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_6_EBU_AD6 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_5_EBU_AD5 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_4_EBU_AD4 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_3_EBU_AD3 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_2_EBU_AD2 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_1_EBU_AD1 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P3_0_EBU_AD0 { 1, 0, 0, 0 }
#define LTQ_MUX_P3_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P3_0_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_23_SSLIC7_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_23 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_23_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_22_SSLIC7_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_22 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_22_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_21_SSLIC7_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_21 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_21_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_20_SSLIC6_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_20 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_20_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_19_SSLIC6_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_19 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_19_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_18_SSLIC6_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_18 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_18_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_17_SSLIC5_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_17 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_17_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_16_SSLIC5_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_16 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_16_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_15_SSLIC5_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_15 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_15_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_14_SSLIC4_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_14 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_14_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_13_SSLIC4_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_13 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_13_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_12_SSLIC4_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_12 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_12_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_11_SSLIC3_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_11 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_11_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_10_SSLIC3_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_10 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_10_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_9_SSLIC3_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_9 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_9_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_8_SSLIC2_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_8 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_8_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_7_SSLIC2_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_7 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_7_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_6_SSLIC2_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_6 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_6_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_5_SSLIC1_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_5 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_5_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_4_SSLIC1_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_4 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_4_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_3_SSLIC1_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_3 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_3_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_2_SSLIC0_CLK { 0, 0, 0, 0 }
#define LTQ_MUX_P4_2 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_2_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_1_SSLIC0_RX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_1 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_1_IN { 1, 0, 1, 0 }
#define LTQ_MUX_P4_0_SSLIC0_TX { 0, 0, 0, 0 }
#define LTQ_MUX_P4_0 { 0, 0, 1, 0 }
#define LTQ_MUX_P4_0_IN { 1, 0, 1, 0 }
#endif

23
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h Normal file
View File

@@ -0,0 +1,23 @@
/************************************************************************
*
* Copyright (c) 2007
* Infineon Technologies AG
* St. Martin Strasse 53; 81669 Muenchen; Germany
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
************************************************************************/
#ifndef __SVIP_PMS_H
#define __SVIP_PMS_H
void svip_sys1_clk_enable(u32 mask);
int svip_sys1_clk_is_enabled(u32 mask);
void svip_sys2_clk_enable(u32 mask);
int svip_sys2_clk_is_enabled(u32 mask);
#endif

165
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h Normal file
View File

@@ -0,0 +1,165 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SYS0_REG_H
#define __SYS0_REG_H
#define sys0_r32(reg) ltq_r32(&sys0->reg)
#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg)
#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg)
/** SYS0 register structure */
struct svip_reg_sys0 {
unsigned long sr; /* 0x0000 */
unsigned long bcr; /* 0x0004 */
unsigned long pll1cr; /* 0x0008 */
unsigned long pll2cr; /* 0x000c */
unsigned long tscr; /* 0x0010 */
unsigned long phyclkr; /* 0x0014 */
};
/*******************************************************************************
* SYS0 Status Register
******************************************************************************/
/* Endian select pin (31) */
#define SYS0_SR_ESEL (0x1 << 31)
#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1)
/* Boot mode pins (27:24) */
#define SYS0_SR_BMODE (0xf << 24)
#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf)
/* PLL2 Lock (18) */
#define SYS0_SR_PLL2LOCK (0x1 << 18)
#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1)
/* PLL1 Lock (17) */
#define SYS0_SR_PLL1LOCK (0x1 << 17)
#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1)
/* Discrete Timing Oscillator Lock (16) */
#define SYS0_SR_DTOLOCK (0x1 << 16)
#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1)
/* Hardware Reset Indication (1) */
#define SYS0_SR_HRSTIN (0x1 << 1)
#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1)
#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1)
#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1))
/* Power-on Reset Indication (0) */
#define SYS0_SR_POR (0x1 << 0)
#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0)
#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1)
#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0))
/*******************************************************************************
* SYS0 Boot Control Register
******************************************************************************/
/* Configuration of Boot Source for CPU5 (25) */
#define SYS0_BCR_BMODECPU5 (0x1 << 25)
#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25)
#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1)
#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25))
/* Configuration of Boot Source for CPU4 (24) */
#define SYS0_BCR_BMODECPU4 (0x1 << 24)
#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24)
#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1)
#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24))
/* Configuration of Boot Source for CPU3 (23) */
#define SYS0_BCR_BMODECPU3 (0x1 << 23)
#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23)
#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1)
#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23))
/* Configuration of Boot Source for CPU2 (22) */
#define SYS0_BCR_BMODECPU2 (0x1 << 22)
#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22)
#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1)
#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22))
/* Configuration of Boot Source for CPU1 (21) */
#define SYS0_BCR_BMODECPU1 (0x1 << 21)
#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21)
#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1)
#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21))
/* Configuration of Boot Source for CPU0 (20:16) */
#define SYS0_BCR_BMODECPU0 (0x1f << 16)
#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16)
#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f)
#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16))
/* Configuration of Endianess for CPU5 (5) */
#define SYS0_BCR_ESELCPU5 (0x1 << 5)
#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5)
#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1)
#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5))
/* Configuration of Endianess for CPU4 (4) */
#define SYS0_BCR_ESELCPU4 (0x1 << 4)
#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4)
#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1)
#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4))
/* Configuration of Endianess for CPU3 (3) */
#define SYS0_BCR_ESELCPU3 (0x1 << 3)
#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3)
#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1)
#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3))
/* Configuration of Endianess for CPU2 (2) */
#define SYS0_BCR_ESELCPU2 (0x1 << 2)
#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2)
#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1)
#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2))
/* Configuration of Endianess for CPU1 (1) */
#define SYS0_BCR_ESELCPU1 (0x1 << 1)
#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1)
#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1)
#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1))
/* Configuration of Endianess for CPU0 (0) */
#define SYS0_BCR_ESELCPU0 (0x1)
#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0)
#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1)
#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0))
/*******************************************************************************
* PLL1 Control Register
******************************************************************************/
/* PLL1 Bypass Enable (31) */
#define SYS0_PLL1CR_OSCBYP (0x1 << 31)
#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31)
#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1)
#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31))
/* PLL1 Divider Value (1:0) */
#define SYS0_PLL1CR_PLLDIV (0x3)
#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0)
#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3)
#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0))
/*******************************************************************************
* PLL2 Control Register
******************************************************************************/
/* PLL2 clear deepsleep (31) */
#define SYS0_PLL2CR_CLRDS (0x1 << 31)
#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31)
#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1)
#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31))
/* PLL2 set deepsleep (30) */
#define SYS0_PLL2CR_SETDS (0x1 << 30)
#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30)
#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1)
#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30))
/* PLL2 Fractional division enable (16) */
#define SYS0_PLL2CR_FRACTEN (0x1 << 16)
#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16)
#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1)
#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16))
/* PLL2 Fractional division value (9:0) */
#define SYS0_FRACTVAL (0x3f)
#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0)
#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f)
#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0))
#endif

370
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h Normal file
View File

@@ -0,0 +1,370 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SYS1_REG_H
#define __SYS1_REG_H
#define sys1_r32(reg) ltq_r32(&sys1->reg)
#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg)
#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg)
/** SYS1 register structure */
struct svip_reg_sys1 {
unsigned long clksr; /* 0x0000 */
unsigned long clkenr; /* 0x0004 */
unsigned long clkclr; /* 0x0008 */
unsigned long reserved0[1];
unsigned long l2ccr; /* 0x0010 */
unsigned long fpicr; /* 0x0014 */
unsigned long wdtcr; /* 0x0018 */
unsigned long reserved1[1];
unsigned long cpucr[6]; /* 0x0020 */
unsigned long reserved2[2];
unsigned long rsr; /* 0x0040 */
unsigned long rreqr; /* 0x0044 */
unsigned long rrlsr; /* 0x0048 */
unsigned long rbtr; /* 0x004c */
unsigned long irncr; /* 0x0050 */
unsigned long irnicr; /* 0x0054 */
unsigned long irnen; /* 0x0058 */
unsigned long reserved3[1];
unsigned long cpursr[6]; /* 0x0060 */
unsigned long reserved4[2];
unsigned long cpusrssr[6]; /* 0x0080 */
unsigned long reserved5[2];
unsigned long cpuwrssr[6]; /* 0x00a0 */
};
/*******************************************************************************
* SYS1 Clock Status Register
******************************************************************************/
/* (r) Clock Enable for L2C */
#define SYS1_CLKSR_L2C (0x1 << 31)
/* (r) Clock Enable for DDR2 */
#define SYS1_CLKSR_DDR2 (0x1 << 30)
/* (r) Clock Enable for SMI2 */
#define SYS1_CLKSR_SMI2 (0x1 << 29)
/* (r) Clock Enable for SMI1 */
#define SYS1_CLKSR_SMI1 (0x1 << 28)
/* (r) Clock Enable for SMI0 */
#define SYS1_CLKSR_SMI0 (0x1 << 27)
/* (r) Clock Enable for FMI0 */
#define SYS1_CLKSR_FMI0 (0x1 << 26)
/* (r) Clock Enable for PORT0 */
#define SYS1_CLKSR_PORT0 (0x1 << 0)
/* (r) Clock Enable for PCM3 */
#define SYS1_CLKSR_PCM3 (0x1 << 19)
/* (r) Clock Enable for PCM2 */
#define SYS1_CLKSR_PCM2 (0x1 << 18)
/* (r) Clock Enable for PCM1 */
#define SYS1_CLKSR_PCM1 (0x1 << 17)
/* (r) Clock Enable for PCM0 */
#define SYS1_CLKSR_PCM0 (0x1 << 16)
/* (r) Clock Enable for ASC1 */
#define SYS1_CLKSR_ASC1 (0x1 << 15)
/* (r) Clock Enable for ASC0 */
#define SYS1_CLKSR_ASC0 (0x1 << 14)
/* (r) Clock Enable for SSC2 */
#define SYS1_CLKSR_SSC2 (0x1 << 13)
/* (r) Clock Enable for SSC1 */
#define SYS1_CLKSR_SSC1 (0x1 << 12)
/* (r) Clock Enable for SSC0 */
#define SYS1_CLKSR_SSC0 (0x1 << 11)
/* (r) Clock Enable for GPTC */
#define SYS1_CLKSR_GPTC (0x1 << 10)
/* (r) Clock Enable for DMA */
#define SYS1_CLKSR_DMA (0x1 << 9)
/* (r) Clock Enable for FSCT */
#define SYS1_CLKSR_FSCT (0x1 << 8)
/* (r) Clock Enable for ETHSW */
#define SYS1_CLKSR_ETHSW (0x1 << 7)
/* (r) Clock Enable for EBU */
#define SYS1_CLKSR_EBU (0x1 << 6)
/* (r) Clock Enable for TRNG */
#define SYS1_CLKSR_TRNG (0x1 << 5)
/* (r) Clock Enable for DEU */
#define SYS1_CLKSR_DEU (0x1 << 4)
/* (r) Clock Enable for PORT3 */
#define SYS1_CLKSR_PORT3 (0x1 << 3)
/* (r) Clock Enable for PORT2 */
#define SYS1_CLKSR_PORT2 (0x1 << 2)
/* (r) Clock Enable for PORT1 */
#define SYS1_CLKSR_PORT1 (0x1 << 1)
/*******************************************************************************
* SYS1 Clock Enable Register
******************************************************************************/
/* (w) Clock Enable Request for L2C */
#define SYS1_CLKENR_L2C (0x1 << 31)
/* (w) Clock Enable Request for DDR2 */
#define SYS1_CLKENR_DDR2 (0x1 << 30)
/* (w) Clock Enable Request for SMI2 */
#define SYS1_CLKENR_SMI2 (0x1 << 29)
/* (w) Clock Enable Request for SMI1 */
#define SYS1_CLKENR_SMI1 (0x1 << 28)
/* (w) Clock Enable Request for SMI0 */
#define SYS1_CLKENR_SMI0 (0x1 << 27)
/* (w) Clock Enable Request for FMI0 */
#define SYS1_CLKENR_FMI0 (0x1 << 26)
/* (w) Clock Enable Request for PORT0 */
#define SYS1_CLKENR_PORT0 (0x1 << 0)
/* (w) Clock Enable Request for PCM3 */
#define SYS1_CLKENR_PCM3 (0x1 << 19)
/* (w) Clock Enable Request for PCM2 */
#define SYS1_CLKENR_PCM2 (0x1 << 18)
/* (w) Clock Enable Request for PCM1 */
#define SYS1_CLKENR_PCM1 (0x1 << 17)
/* (w) Clock Enable Request for PCM0 */
#define SYS1_CLKENR_PCM0 (0x1 << 16)
/* (w) Clock Enable Request for ASC1 */
#define SYS1_CLKENR_ASC1 (0x1 << 15)
/* (w) Clock Enable Request for ASC0 */
#define SYS1_CLKENR_ASC0 (0x1 << 14)
/* (w) Clock Enable Request for SSC2 */
#define SYS1_CLKENR_SSC2 (0x1 << 13)
/* (w) Clock Enable Request for SSC1 */
#define SYS1_CLKENR_SSC1 (0x1 << 12)
/* (w) Clock Enable Request for SSC0 */
#define SYS1_CLKENR_SSC0 (0x1 << 11)
/* (w) Clock Enable Request for GPTC */
#define SYS1_CLKENR_GPTC (0x1 << 10)
/* (w) Clock Enable Request for DMA */
#define SYS1_CLKENR_DMA (0x1 << 9)
/* (w) Clock Enable Request for FSCT */
#define SYS1_CLKENR_FSCT (0x1 << 8)
/* (w) Clock Enable Request for ETHSW */
#define SYS1_CLKENR_ETHSW (0x1 << 7)
/* (w) Clock Enable Request for EBU */
#define SYS1_CLKENR_EBU (0x1 << 6)
/* (w) Clock Enable Request for TRNG */
#define SYS1_CLKENR_TRNG (0x1 << 5)
/* (w) Clock Enable Request for DEU */
#define SYS1_CLKENR_DEU (0x1 << 4)
/* (w) Clock Enable Request for PORT3 */
#define SYS1_CLKENR_PORT3 (0x1 << 3)
/* (w) Clock Enable Request for PORT2 */
#define SYS1_CLKENR_PORT2 (0x1 << 2)
/* (w) Clock Enable Request for PORT1 */
#define SYS1_CLKENR_PORT1 (0x1 << 1)
/*******************************************************************************
* SYS1 Clock Clear Register
******************************************************************************/
/* (w) Clock Disable Request for L2C */
#define SYS1_CLKCLR_L2C (0x1 << 31)
/* (w) Clock Disable Request for DDR2 */
#define SYS1_CLKCLR_DDR2 (0x1 << 30)
/* (w) Clock Disable Request for SMI2 */
#define SYS1_CLKCLR_SMI2 (0x1 << 29)
/* (w) Clock Disable Request for SMI1 */
#define SYS1_CLKCLR_SMI1 (0x1 << 28)
/* (w) Clock Disable Request for SMI0 */
#define SYS1_CLKCLR_SMI0 (0x1 << 27)
/* (w) Clock Disable Request for FMI0 */
#define SYS1_CLKCLR_FMI0 (0x1 << 26)
/* (w) Clock Disable Request for PORT0 */
#define SYS1_CLKCLR_PORT0 (0x1 << 0)
/* (w) Clock Disable Request for PCM3 */
#define SYS1_CLKCLR_PCM3 (0x1 << 19)
/* (w) Clock Disable Request for PCM2 */
#define SYS1_CLKCLR_PCM2 (0x1 << 18)
/* (w) Clock Disable Request for PCM1 */
#define SYS1_CLKCLR_PCM1 (0x1 << 17)
/* (w) Clock Disable Request for PCM0 */
#define SYS1_CLKCLR_PCM0 (0x1 << 16)
/* (w) Clock Disable Request for ASC1 */
#define SYS1_CLKCLR_ASC1 (0x1 << 15)
/* (w) Clock Disable Request for ASC0 */
#define SYS1_CLKCLR_ASC0 (0x1 << 14)
/* (w) Clock Disable Request for SSC2 */
#define SYS1_CLKCLR_SSC2 (0x1 << 13)
/* (w) Clock Disable Request for SSC1 */
#define SYS1_CLKCLR_SSC1 (0x1 << 12)
/* (w) Clock Disable Request for SSC0 */
#define SYS1_CLKCLR_SSC0 (0x1 << 11)
/* (w) Clock Disable Request for GPTC */
#define SYS1_CLKCLR_GPTC (0x1 << 10)
/* (w) Clock Disable Request for DMA */
#define SYS1_CLKCLR_DMA (0x1 << 9)
/* (w) Clock Disable Request for FSCT */
#define SYS1_CLKCLR_FSCT (0x1 << 8)
/* (w) Clock Disable Request for ETHSW */
#define SYS1_CLKCLR_ETHSW (0x1 << 7)
/* (w) Clock Disable Request for EBU */
#define SYS1_CLKCLR_EBU (0x1 << 6)
/* (w) Clock Disable Request for TRNG */
#define SYS1_CLKCLR_TRNG (0x1 << 5)
/* (w) Clock Disable Request for DEU */
#define SYS1_CLKCLR_DEU (0x1 << 4)
/* (w) Clock Disable Request for PORT3 */
#define SYS1_CLKCLR_PORT3 (0x1 << 3)
/* (w) Clock Disable Request for PORT2 */
#define SYS1_CLKCLR_PORT2 (0x1 << 2)
/* (w) Clock Disable Request for PORT1 */
#define SYS1_CLKCLR_PORT1 (0x1 << 1)
/*******************************************************************************
* SYS1 FPI Control Register
******************************************************************************/
/* FPI Bus Clock divider (0) */
#define SYS1_FPICR_FPIDIV (0x1)
#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0)
#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1)
#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0))
/*******************************************************************************
* SYS1 Clock Control Register for CPUn
******************************************************************************/
/* Enable bit for clock of CPUn (1) */
#define SYS1_CPUCR_CPUCLKEN (0x1 << 1)
#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1)
#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1)
#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1))
/* Divider factor for clock of CPUn (0) */
#define SYS1_CPUCR_CPUDIV (0x1)
#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0)
#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1)
#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0))
/*******************************************************************************
* SYS1 Reset Request Register
******************************************************************************/
/* HRSTOUT Reset Request (18) */
#define SYS1_RREQ_HRSTOUT (0x1 << 18)
#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18)
#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18))
/* FBS0 Reset Request (17) */
#define SYS1_RREQ_FBS0 (0x1 << 17)
#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17)
#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17))
/* SUBSYS Reset Request (16) */
#define SYS1_RREQ_SUBSYS (0x1 << 16)
#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16)
#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16))
/* Watchdog5 Reset Request (13) */
#define SYS1_RREQ_WDT5 (0x1 << 13)
#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13)
#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13))
/* Watchdog4 Reset Request (12) */
#define SYS1_RREQ_WDT4 (0x1 << 12)
#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12)
#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12))
/* Watchdog3 Reset Request (11) */
#define SYS1_RREQ_WDT3 (0x1 << 11)
#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11)
#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11))
/* Watchdog2 Reset Request (10) */
#define SYS1_RREQ_WDT2 (0x1 << 10)
#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10)
#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10))
/* Watchdog1 Reset Request (9) */
#define SYS1_RREQ_WDT1 (0x1 << 9)
#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9)
#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9))
/* Watchdog0 Reset Request (8) */
#define SYS1_RREQ_WDT0 (0x1 << 8)
#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8)
#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8))
/* CPU5 Reset Request (5) */
#define SYS1_RREQ_CPU5 (0x1 << 5)
#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5)
#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5))
/* CPU4 Reset Request (4) */
#define SYS1_RREQ_CPU4 (0x1 << 4)
#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4)
#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4))
/* CPU3 Reset Request (3) */
#define SYS1_RREQ_CPU3 (0x1 << 3)
#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3)
#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3))
/* CPU2 Reset Request (2) */
#define SYS1_RREQ_CPU2 (0x1 << 2)
#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2)
#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2))
/* CPU1 Reset Request (1) */
#define SYS1_RREQ_CPU1 (0x1 << 1)
#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1)
#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1))
/* CPU0 Reset Request (0) */
#define SYS1_RREQ_CPU0 (0x1)
#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0)
#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0))
/*******************************************************************************
* SYS1 Reset Release Register
******************************************************************************/
/* HRSTOUT Reset Release (18) */
#define SYS1_RRLSR_HRSTOUT (0x1 << 18)
#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18)
#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18))
/* FBS0 Reset Release (17) */
#define SYS1_RRLSR_FBS0 (0x1 << 17)
#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17)
#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17))
/* SUBSYS Reset Release (16) */
#define SYS1_RRLSR_SUBSYS (0x1 << 16)
#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16)
#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16))
/* Watchdog5 Reset Release (13) */
#define SYS1_RRLSR_WDT5 (0x1 << 13)
#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13)
#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13))
/* Watchdog4 Reset Release (12) */
#define SYS1_RRLSR_WDT4 (0x1 << 12)
#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12)
#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12))
/* Watchdog3 Reset Release (11) */
#define SYS1_RRLSR_WDT3 (0x1 << 11)
#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11)
#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11))
/* Watchdog2 Reset Release (10) */
#define SYS1_RRLSR_WDT2 (0x1 << 10)
#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10)
#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10))
/* Watchdog1 Reset Release (9) */
#define SYS1_RRLSR_WDT1 (0x1 << 9)
#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9)
#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9))
/* Watchdog0 Reset Release (8) */
#define SYS1_RRLSR_WDT0 (0x1 << 8)
#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8)
#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8))
/* CPU5 Reset Release (5) */
#define SYS1_RRLSR_CPU5 (0x1 << 5)
#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5)
#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5))
/* CPU4 Reset Release (4) */
#define SYS1_RRLSR_CPU4 (0x1 << 4)
#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4)
#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4))
/* CPU3 Reset Release (3) */
#define SYS1_RRLSR_CPU3 (0x1 << 3)
#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3)
#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3))
/* CPU2 Reset Release (2) */
#define SYS1_RRLSR_CPU2 (0x1 << 2)
#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2)
#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2))
/* CPU1 Reset Release (1) */
#define SYS1_RRLSR_CPU1 (0x1 << 1)
#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1)
#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1))
/* CPU0 Reset Release (0) */
#define SYS1_RRLSR_CPU0 (0x1)
#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0)
#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0))
#endif

494
target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h Normal file
View File

@@ -0,0 +1,494 @@
/******************************************************************************
Copyright (c) 2007
Infineon Technologies AG
St. Martin Strasse 53; 81669 Munich, Germany
Any use of this Software is subject to the conclusion of a respective
License Agreement. Without such a License Agreement no rights to the
Software are granted.
******************************************************************************/
#ifndef __SYS2_REG_H
#define __SYS2_REG_H
#define sys2_r32(reg) ltq_r32(&sys2->reg)
#define sys2_w32(val, reg) ltq_w32(val, &sys2->reg)
#define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg)
/** SYS2 register structure */
struct svip_reg_sys2 {
volatile unsigned long clksr; /* 0x0000 */
volatile unsigned long clkenr; /* 0x0004 */
volatile unsigned long clkclr; /* 0x0008 */
volatile unsigned long reserved0[1];
volatile unsigned long rsr; /* 0x0010 */
volatile unsigned long rreqr; /* 0x0014 */
volatile unsigned long rrlsr; /* 0x0018 */
};
/*******************************************************************************
* SYS2 Clock Status Register
******************************************************************************/
/* Clock Enable for PORT4 */
#define SYS2_CLKSR_PORT4 (0x1 << 27)
#define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27)
#define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27)
/* Clock Enable for HWSYNC */
#define SYS2_CLKSR_HWSYNC (0x1 << 26)
#define SYS2_CLKSR_HWSYNC_VAL(val) (((val) &
#define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26)
/* Clock Enable for MBS */
#define SYS2_CLKSR_MBS (0x1 << 25)
#define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25)
#define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25)
/* Clock Enable for SWINT */
#define SYS2_CLKSR_SWINT (0x1 << 24)
#define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24)
#define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24)
/* Clock Enable for HWACC3 */
#define SYS2_CLKSR_HWACC3 (0x1 << 19)
#define SYS2_CLKSR_HWACC3_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19)
/* Clock Enable for HWACC2 */
#define SYS2_CLKSR_HWACC2 (0x1 << 18)
#define SYS2_CLKSR_HWACC2_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18)
/* Clock Enable for HWACC1 */
#define SYS2_CLKSR_HWACC1 (0x1 << 17)
#define SYS2_CLKSR_HWACC1_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17)
/* Clock Enable for HWACC0 */
#define SYS2_CLKSR_HWACC0 (0x1 << 16)
#define SYS2_CLKSR_HWACC0_VAL(val) (((val) &
#define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16)
/* Clock Enable for SIF7 */
#define SYS2_CLKSR_SIF7 (0x1 << 15)
#define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15)
#define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15)
/* Clock Enable for SIF6 */
#define SYS2_CLKSR_SIF6 (0x1 << 14)
#define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14)
#define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14)
/* Clock Enable for SIF5 */
#define SYS2_CLKSR_SIF5 (0x1 << 13)
#define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13)
#define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13)
/* Clock Enable for SIF4 */
#define SYS2_CLKSR_SIF4 (0x1 << 12)
#define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12)
#define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12)
/* Clock Enable for SIF3 */
#define SYS2_CLKSR_SIF3 (0x1 << 11)
#define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11)
/* Clock Enable for SIF2 */
#define SYS2_CLKSR_SIF2 (0x1 << 10)
#define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10)
/* Clock Enable for SIF1 */
#define SYS2_CLKSR_SIF1 (0x1 << 9)
#define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9)
/* Clock Enable for SIF0 */
#define SYS2_CLKSR_SIF0 (0x1 << 8)
#define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8)
/* Clock Enable for DFEV7 */
#define SYS2_CLKSR_DFEV7 (0x1 << 7)
#define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7)
/* Clock Enable for DFEV6 */
#define SYS2_CLKSR_DFEV6 (0x1 << 6)
#define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6)
/* Clock Enable for DFEV5 */
#define SYS2_CLKSR_DFEV5 (0x1 << 5)
#define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5)
/* Clock Enable for DFEV4 */
#define SYS2_CLKSR_DFEV4 (0x1 << 4)
#define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4)
/* Clock Enable for DFEV3 */
#define SYS2_CLKSR_DFEV3 (0x1 << 3)
#define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3)
/* Clock Enable for DFEV2 */
#define SYS2_CLKSR_DFEV2 (0x1 << 2)
#define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2)
/* Clock Enable for DFEV1 */
#define SYS2_CLKSR_DFEV1 (0x1 << 1)
#define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1)
/* Clock Enable for DFEV0 */
#define SYS2_CLKSR_DFEV0 (0x1)
#define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0)
/*******************************************************************************
* SYS2 Clock Enable Register
******************************************************************************/
/* Clock Enable Request for PORT4 */
#define SYS2_CLKENR_PORT4 (0x1 << 27)
#define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27)
#define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27))
/* Clock Enable Request for HWSYNC */
#define SYS2_CLKENR_HWSYNC (0x1 << 26)
#define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26)
#define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26))
/* Clock Enable Request for MBS */
#define SYS2_CLKENR_MBS (0x1 << 25)
#define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25)
#define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25))
/* Clock Enable Request for SWINT */
#define SYS2_CLKENR_SWINT (0x1 << 24)
#define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24)
#define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24))
/* Clock Enable Request for HWACC3 */
#define SYS2_CLKENR_HWACC3 (0x1 << 19)
#define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19)
#define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19))
/* Clock Enable Request for HWACC2 */
#define SYS2_CLKENR_HWACC2 (0x1 << 18)
#define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18)
#define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18))
/* Clock Enable Request for HWACC1 */
#define SYS2_CLKENR_HWACC1 (0x1 << 17)
#define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17)
#define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17))
/* Clock Enable Request for HWACC0 */
#define SYS2_CLKENR_HWACC0 (0x1 << 16)
#define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16)
#define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16))
/* Clock Enable Request for SIF7 */
#define SYS2_CLKENR_SIF7 (0x1 << 15)
#define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15)
#define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15))
/* Clock Enable Request for SIF6 */
#define SYS2_CLKENR_SIF6 (0x1 << 14)
#define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14)
#define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14))
/* Clock Enable Request for SIF5 */
#define SYS2_CLKENR_SIF5 (0x1 << 13)
#define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13)
#define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13))
/* Clock Enable Request for SIF4 */
#define SYS2_CLKENR_SIF4 (0x1 << 12)
#define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12)
#define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12))
/* Clock Enable Request for SIF3 */
#define SYS2_CLKENR_SIF3 (0x1 << 11)
#define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11))
/* Clock Enable Request for SIF2 */
#define SYS2_CLKENR_SIF2 (0x1 << 10)
#define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10))
/* Clock Enable Request for SIF1 */
#define SYS2_CLKENR_SIF1 (0x1 << 9)
#define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9))
/* Clock Enable Request for SIF0 */
#define SYS2_CLKENR_SIF0 (0x1 << 8)
#define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8))
/* Clock Enable Request for DFEV7 */
#define SYS2_CLKENR_DFEV7 (0x1 << 7)
#define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7))
/* Clock Enable Request for DFEV6 */
#define SYS2_CLKENR_DFEV6 (0x1 << 6)
#define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6))
/* Clock Enable Request for DFEV5 */
#define SYS2_CLKENR_DFEV5 (0x1 << 5)
#define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5))
/* Clock Enable Request for DFEV4 */
#define SYS2_CLKENR_DFEV4 (0x1 << 4)
#define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4))
/* Clock Enable Request for DFEV3 */
#define SYS2_CLKENR_DFEV3 (0x1 << 3)
#define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3))
/* Clock Enable Request for DFEV2 */
#define SYS2_CLKENR_DFEV2 (0x1 << 2)
#define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2))
/* Clock Enable Request for DFEV1 */
#define SYS2_CLKENR_DFEV1 (0x1 << 1)
#define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1))
/* Clock Enable Request for DFEV0 */
#define SYS2_CLKENR_DFEV0 (0x1)
#define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1)))
/*******************************************************************************
* SYS2 Clock Clear Register
******************************************************************************/
/* Clock Disable Request for PORT4 */
#define SYS2_CLKCLR_PORT4 (0x1 << 27)
#define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27)
#define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27))
/* Clock Disable Request for HWSYNC */
#define SYS2_CLKCLR_HWSYNC (0x1 << 26)
#define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26)
#define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26))
/* Clock Disable Request for MBS */
#define SYS2_CLKCLR_MBS (0x1 << 25)
#define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25)
#define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25))
/* Clock Disable Request for SWINT */
#define SYS2_CLKCLR_SWINT (0x1 << 24)
#define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24)
#define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24))
/* Clock Disable Request for HWACC3 */
#define SYS2_CLKCLR_HWACC3 (0x1 << 19)
#define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19)
#define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19))
/* Clock Disable Request for HWACC2 */
#define SYS2_CLKCLR_HWACC2 (0x1 << 18)
#define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18)
#define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18))
/* Clock Disable Request for HWACC1 */
#define SYS2_CLKCLR_HWACC1 (0x1 << 17)
#define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17)
#define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17))
/* Clock Disable Request for HWACC0 */
#define SYS2_CLKCLR_HWACC0 (0x1 << 16)
#define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16)
#define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16))
/* Clock Disable Request for SIF7 */
#define SYS2_CLKCLR_SIF7 (0x1 << 15)
#define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15)
#define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15))
/* Clock Disable Request for SIF6 */
#define SYS2_CLKCLR_SIF6 (0x1 << 14)
#define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14)
#define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14))
/* Clock Disable Request for SIF5 */
#define SYS2_CLKCLR_SIF5 (0x1 << 13)
#define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13)
#define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13))
/* Clock Disable Request for SIF4 */
#define SYS2_CLKCLR_SIF4 (0x1 << 12)
#define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12)
#define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12))
/* Clock Disable Request for SIF3 */
#define SYS2_CLKCLR_SIF3 (0x1 << 11)
#define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11))
/* Clock Disable Request for SIF2 */
#define SYS2_CLKCLR_SIF2 (0x1 << 10)
#define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10))
/* Clock Disable Request for SIF1 */
#define SYS2_CLKCLR_SIF1 (0x1 << 9)
#define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9))
/* Clock Disable Request for SIF0 */
#define SYS2_CLKCLR_SIF0 (0x1 << 8)
#define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8))
/* Clock Disable Request for DFEV7 */
#define SYS2_CLKCLR_DFEV7 (0x1 << 7)
#define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7))
/* Clock Disable Request for DFEV6 */
#define SYS2_CLKCLR_DFEV6 (0x1 << 6)
#define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6))
/* Clock Disable Request for DFEV5 */
#define SYS2_CLKCLR_DFEV5 (0x1 << 5)
#define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5))
/* Clock Disable Request for DFEV4 */
#define SYS2_CLKCLR_DFEV4 (0x1 << 4)
#define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4))
/* Clock Disable Request for DFEV3 */
#define SYS2_CLKCLR_DFEV3 (0x1 << 3)
#define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3))
/* Clock Disable Request for DFEV2 */
#define SYS2_CLKCLR_DFEV2 (0x1 << 2)
#define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2))
/* Clock Disable Request for DFEV1 */
#define SYS2_CLKCLR_DFEV1 (0x1 << 1)
#define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1))
/* Clock Disable Request for DFEV0 */
#define SYS2_CLKCLR_DFEV0 (0x1)
#define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1)))
/*******************************************************************************
* SYS2 Reset Status Register
******************************************************************************/
/* HWACC3 Reset */
#define SYS2_RSR_HWACC3 (0x1 << 11)
#define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11)
/* HWACC2 Reset */
#define SYS2_RSR_HWACC2 (0x1 << 10)
#define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10)
/* HWACC1 Reset */
#define SYS2_RSR_HWACC1 (0x1 << 9)
#define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9)
/* HWACC0 Reset */
#define SYS2_RSR_HWACC0 (0x1 << 8)
#define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8)
/* DFEV7 Reset */
#define SYS2_RSR_DFEV7 (0x1 << 7)
#define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7)
/* DFEV6 Reset */
#define SYS2_RSR_DFEV6 (0x1 << 6)
#define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6)
/* DFEV5 Reset */
#define SYS2_RSR_DFEV5 (0x1 << 5)
#define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5)
/* DFEV4 Reset */
#define SYS2_RSR_DFEV4 (0x1 << 4)
#define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4)
/* DFEV3 Reset */
#define SYS2_RSR_DFEV3 (0x1 << 3)
#define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3)
/* DFEV2 Reset */
#define SYS2_RSR_DFEV2 (0x1 << 2)
#define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2)
/* DFEV1 Reset */
#define SYS2_RSR_DFEV1 (0x1 << 1)
#define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1)
/* DFEV0 Reset */
#define SYS2_RSR_DFEV0 (0x1)
#define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0)
/******************************************************************************
* SYS2 Reset Request Register
******************************************************************************/
/* HWACC3 Reset Request */
#define SYS2_RREQR_HWACC3 (0x1 << 11)
#define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11))
/* HWACC2 Reset Request */
#define SYS2_RREQR_HWACC2 (0x1 << 10)
#define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10))
/* HWACC1 Reset Request */
#define SYS2_RREQR_HWACC1 (0x1 << 9)
#define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9))
/* HWACC0 Reset Request */
#define SYS2_RREQR_HWACC0 (0x1 << 8)
#define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8))
/* DFEV7 Reset Request */
#define SYS2_RREQR_DFEV7 (0x1 << 7)
#define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7))
/* DFEV6 Reset Request */
#define SYS2_RREQR_DFEV6 (0x1 << 6)
#define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6))
/* DFEV5 Reset Request */
#define SYS2_RREQR_DFEV5 (0x1 << 5)
#define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5))
/* DFEV4 Reset Request */
#define SYS2_RREQR_DFEV4 (0x1 << 4)
#define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4))
/* DFEV3 Reset Request */
#define SYS2_RREQR_DFEV3 (0x1 << 3)
#define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3))
/* DFEV2 Reset Request */
#define SYS2_RREQR_DFEV2 (0x1 << 2)
#define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2))
/* DFEV1 Reset Request */
#define SYS2_RREQR_DFEV1 (0x1 << 1)
#define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1))
/* DFEV0 Reset Request */
#define SYS2_RREQR_DFEV0 (0x1)
#define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1)))
/*******************************************************************************
* SYS2 Reset Release Register
******************************************************************************/
/* HWACC3 Reset Release */
#define SYS2_RRLSR_HWACC3 (0x1 << 11)
#define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11)
#define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11))
/* HWACC2 Reset Release */
#define SYS2_RRLSR_HWACC2 (0x1 << 10)
#define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10)
#define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10))
/* HWACC1 Reset Release */
#define SYS2_RRLSR_HWACC1 (0x1 << 9)
#define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9)
#define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9))
/* HWACC0 Reset Release */
#define SYS2_RRLSR_HWACC0 (0x1 << 8)
#define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8)
#define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8))
/* DFEV7 Reset Release */
#define SYS2_RRLSR_DFEV7 (0x1 << 7)
#define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7)
#define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7))
/* DFEV6 Reset Release */
#define SYS2_RRLSR_DFEV6 (0x1 << 6)
#define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6)
#define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6))
/* DFEV5 Reset Release */
#define SYS2_RRLSR_DFEV5 (0x1 << 5)
#define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5)
#define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5))
/* DFEV4 Reset Release */
#define SYS2_RRLSR_DFEV4 (0x1 << 4)
#define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4)
#define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4))
/* DFEV3 Reset Release */
#define SYS2_RRLSR_DFEV3 (0x1 << 3)
#define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3)
#define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3))
/* DFEV2 Reset Release */
#define SYS2_RRLSR_DFEV2 (0x1 << 2)
#define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2)
#define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2))
/* DFEV1 Reset Release */
#define SYS2_RRLSR_DFEV1 (0x1 << 1)
#define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1)
#define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1))
/* DFEV0 Reset Release */
#define SYS2_RRLSR_DFEV0 (0x1)
#define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1))
#define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1)))
#endif /* __SYS2_H */