mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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[ifxmips] adds dsl support, thank you infineon/lantiq
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@18259 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
43
package/ifxmips-dsl-api/patches/100-dsl_compat.patch
Normal file
43
package/ifxmips-dsl-api/patches/100-dsl_compat.patch
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@@ -0,0 +1,43 @@
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Index: drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_device_danube.h
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/include/drv_dsl_cpe_device_danube.h 2009-05-12 20:02:16.000000000 +0200
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+++ drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_device_danube.h 2009-11-01 00:57:23.000000000 +0100
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@@ -24,7 +24,7 @@
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#include "drv_dsl_cpe_simulator_danube.h"
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#else
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/* Include for the low level driver interface header file */
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-#include "asm/ifx/ifx_mei_bsp.h"
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+#include "mei/ifxmips_mei_interface.h"
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#endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
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#define DSL_MAX_LINE_NUMBER 1
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Index: drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/common/drv_dsl_cpe_os_linux.c 2009-11-01 01:00:08.000000000 +0100
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+++ drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c 2009-11-01 01:03:51.000000000 +0100
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@@ -11,6 +11,7 @@
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#ifdef __LINUX__
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#define DSL_INTERN
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+#include <linux/device.h>
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#include "drv_dsl_cpe_api.h"
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#include "drv_dsl_cpe_api_ioctl.h"
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@@ -1058,6 +1059,7 @@
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/* Entry point of driver */
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int __init DSL_ModuleInit(void)
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{
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+ struct class *dsl_class;
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DSL_int_t i;
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printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
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@@ -1104,7 +1106,8 @@
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}
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DSL_DRV_DevNodeInit();
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-
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+ dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
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+ device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
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return 0;
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}
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95
package/ifxmips-dsl-api/patches/200-mei_compat.patch
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95
package/ifxmips-dsl-api/patches/200-mei_compat.patch
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@@ -0,0 +1,95 @@
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Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_mei.c
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_mei.c 2009-10-31 23:30:20.000000000 +0100
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+++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_mei.c 2009-11-01 04:41:58.000000000 +0100
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@@ -41,18 +41,19 @@
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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+#include <linux/device.h>
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#include <asm/uaccess.h>
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#include <asm/hardirq.h>
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx/irq.h>
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-#include <asm/ifx/ifx_gpio.h>
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-//#include <asm/ifx/ifx_led.h>
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-#include <asm/ifx/ifx_pmu.h>
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-#include <asm/ifx/ifx_atm.h>
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+
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+#include <ifxmips.h>
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+#include <ifxmips_irq.h>
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+#include <ifxmips_gpio.h>
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+#include <ifxmips_pmu.h>
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+#include "ifxmips_atm.h"
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#define IFX_MEI_BSP
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#include "ifxmips_mei_interface.h"
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-#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ
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+/*#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ
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#define IFXMIPS_RCU_RST_REQ_ARC_JTAG IFX_RCU_RST_REQ_ARC_JTAG
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#define IFXMIPS_RCU_RST_REQ_DFE IFX_RCU_RST_REQ_DFE
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#define IFXMIPS_RCU_RST_REQ_AFE IFX_RCU_RST_REQ_AFE
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@@ -76,7 +77,7 @@
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#define ifxmips_r32(reg) __raw_readl(reg)
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#define ifxmips_w32(val, reg) __raw_writel(val, reg)
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#define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
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-
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+*/
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#define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
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#define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
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@@ -173,7 +174,8 @@
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extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
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#define MEI_MASK_AND_ACK_IRQ ifxmips_mask_and_ack_irq
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-static int dev_major = 105;
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+#define MEI_MAJOR 105
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+static int dev_major = MEI_MAJOR;
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static struct file_operations bsp_mei_operations = {
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owner:THIS_MODULE,
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@@ -2294,10 +2296,10 @@
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IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]);
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return -1;
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}
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- if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
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+ /*if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
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IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]);
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return -1;
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- }
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+ }*/
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// IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP]));
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return 0;
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}
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@@ -2922,6 +2924,7 @@
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IFX_MEI_ModuleInit (void)
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{
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int i = 0;
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+ static struct class *dsl_class;
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printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
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@@ -2935,14 +2938,15 @@
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IFX_MEI_InitProcFS (i);
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#endif
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}
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- for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
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+ for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
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dsl_bsp_event_callback[i].function = NULL;
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#ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK
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printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__);
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DFE_Loopback_Test ();
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#endif
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-
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+ dsl_class = class_create(THIS_MODULE, "ifx_mei");
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+ device_create(dsl_class, NULL, MKDEV(MEI_MAJOR, 0), NULL, "ifx_mei");
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return 0;
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}
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@@ -2996,3 +3000,5 @@
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module_init (IFX_MEI_ModuleInit);
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module_exit (IFX_MEI_ModuleExit);
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+
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+MODULE_LICENSE("Dual BSD/GPL");
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168
package/ifxmips-dsl-api/patches/300-atm_compat.patch
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168
package/ifxmips-dsl-api/patches/300-atm_compat.patch
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@@ -0,0 +1,168 @@
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Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.c
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_core.c 2009-11-01 14:29:05.000000000 +0100
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+++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.c 2009-11-01 16:07:46.000000000 +0100
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@@ -58,9 +58,8 @@
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/*
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* Chip Specific Head File
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*/
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-#include <asm/ifx/ifx_types.h>
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx/common_routines.h>
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+#include <ifxmips.h>
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+#include <ifxmips_cgu.h>
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#include "ifxmips_atm_core.h"
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@@ -1146,7 +1145,7 @@
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static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
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{
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- unsigned int qsb_clk = ifx_get_fpi_hz();
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+ unsigned int qsb_clk = ifxmips_get_fpi_hz();
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unsigned int qsb_qid = queue + FIRST_QSB_QID;
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union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
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union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
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@@ -1318,7 +1317,7 @@
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static void qsb_global_set(void)
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{
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- unsigned int qsb_clk = ifx_get_fpi_hz();
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+ unsigned int qsb_clk = ifxmips_get_fpi_hz();
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int i;
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unsigned int tmp1, tmp2, tmp3;
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@@ -2505,3 +2504,4 @@
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module_init(ifx_atm_init);
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module_exit(ifx_atm_exit);
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+MODULE_LICENSE("Dual BSD/GPL");
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Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_common.h
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_ppe_common.h 2009-11-01 14:30:55.000000000 +0100
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+++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_common.h 2009-11-01 15:58:50.000000000 +0100
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@@ -1,9 +1,10 @@
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#ifndef IFXMIPS_ATM_PPE_COMMON_H
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#define IFXMIPS_ATM_PPE_COMMON_H
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-
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-
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-#if defined(CONFIG_DANUBE)
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+#if defined(CONFIG_IFXMIPS)
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+ #include "ifxmips_atm_ppe_danube.h"
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+ #define CONFIG_DANUBE
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+#elif defined(CONFIG_DANUBE)
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#include "ifxmips_atm_ppe_danube.h"
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#elif defined(CONFIG_AMAZON_SE)
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#include "ifxmips_atm_ppe_amazon_se.h"
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@@ -16,7 +17,6 @@
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#endif
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-
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/*
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* Code/Data Memory (CDM) Interface Configuration Register
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*/
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Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.h
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_core.h 2009-11-01 14:30:55.000000000 +0100
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+++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_core.h 2009-11-01 15:58:50.000000000 +0100
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@@ -25,8 +25,8 @@
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#define IFXMIPS_ATM_CORE_H
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-
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-#include <asm/ifx/ifx_atm.h>
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+#include "ifxmips_compat.h"
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+#include "ifx_atm.h"
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#include "ifxmips_atm_ppe_common.h"
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#include "ifxmips_atm_fw_regs_common.h"
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Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_compat.h
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_compat.h 2009-11-01 15:58:50.000000000 +0100
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@@ -0,0 +1,43 @@
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+#ifndef _IFXMIPS_COMPAT_H__
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+#define _IFXMIPS_COMPAT_H__
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+
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+#define IFX_SUCCESS 0
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+#define IFX_ERROR (-1)
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+
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+#define ATM_VBR_NRT ATM_VBR
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+#define ATM_VBR_RT 6
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+#define ATM_UBR_PLUS 7
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+#define ATM_GFR 8
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+
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+#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x)))
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+
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+#define SET_BITS(x, msb, lsb, value) \
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+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
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+
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+
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+#define IFX_PMU_ENABLE 1
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+#define IFX_PMU_DISABLE 0
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+
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+#define IFX_PMU_MODULE_DSL_DFE (1 << 9)
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+#define IFX_PMU_MODULE_AHBS (1 << 13)
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+#define IFX_PMU_MODULE_PPE_QSB (1 << 18)
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+#define IFX_PMU_MODULE_PPE_SLL01 (1 << 19)
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+#define IFX_PMU_MODULE_PPE_TC (1 << 21)
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+#define IFX_PMU_MODULE_PPE_EMA (1 << 22)
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+#define IFX_PMU_MODULE_PPE_TOP (1 << 29)
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+
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+#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) ifxmips_pmu_enable(b); else ifxmips_pmu_disable(b);}
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+
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+#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
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+#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x))
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+#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x))
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+#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x))
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+#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x))
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+#define PPE_TPE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x))
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+#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x))
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+
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+#define IFX_REG_W32(_v, _r) __raw_writel((_v), (_r))
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+
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+#define CONFIG_IFXMIPS_DSL_CPE_MEI y
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+
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+#endif
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Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_danube.h
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_ppe_danube.h 2009-11-01 14:30:55.000000000 +0100
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+++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_ppe_danube.h 2009-11-01 15:58:50.000000000 +0100
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@@ -1,7 +1,7 @@
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#ifndef IFXMIPS_ATM_PPE_DANUBE_H
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#define IFXMIPS_ATM_PPE_DANUBE_H
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-
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+#include <ifxmips_irq.h>
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/*
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* FPI Configuration Bus Register and Memory Address Mapping
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@@ -93,7 +93,7 @@
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/*
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* Mailbox IGU1 Interrupt
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*/
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-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
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+#define PPE_MAILBOX_IGU1_INT IFXMIPS_PPE_MBOX_INT
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Index: drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_danube.c
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===================================================================
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--- drv_dsl_cpe_api-3.24.4.4.orig/src/mei/ifxmips_atm_danube.c 2009-11-01 14:29:18.000000000 +0100
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+++ drv_dsl_cpe_api-3.24.4.4/src/mei/ifxmips_atm_danube.c 2009-11-01 15:58:50.000000000 +0100
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@@ -45,10 +45,9 @@
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/*
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* Chip Specific Head File
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*/
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-#include <asm/ifx/ifx_types.h>
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx/common_routines.h>
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-#include <asm/ifx/ifx_pmu.h>
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+#include <ifxmips.h>
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+#include <ifxmips_pmu.h>
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+#include "ifxmips_compat.h"
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#include "ifxmips_atm_core.h"
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#include "ifxmips_atm_fw_danube.h"
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