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brcm47xx: update bcm5354 support patch
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30423 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
hauke
parent
37d47ead81
commit
d4a8a448fa
@ -1,42 +1,145 @@
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--- a/drivers/ssb/driver_chipcommon.c
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From 6d174f732e198aae8583cc5414b11b988bfd37a9 Mon Sep 17 00:00:00 2001
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+++ b/drivers/ssb/driver_chipcommon.c
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From: Hauke Mehrtens <hauke@hauke-m.de>
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@@ -318,6 +318,8 @@ void ssb_chipco_resume(struct ssb_chipco
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Date: Mon, 30 Jan 2012 22:44:15 +0100
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void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
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Subject: [PATCH 4/4] ssb: add support for bcm5354
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u32 *plltype, u32 *n, u32 *m)
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{
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This patch adds support the the BCM5354 SoC.
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+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
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It has a PMU and a constant not configurable clock.
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+ return;
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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---
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switch (*plltype) {
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drivers/ssb/driver_chipcommon_pmu.c | 48 +++++++++++++++++++++++++++++++---
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@@ -341,6 +343,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
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drivers/ssb/driver_mipscore.c | 3 ++
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void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
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drivers/ssb/main.c | 3 ++
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u32 *plltype, u32 *n, u32 *m)
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drivers/ssb/ssb_private.h | 4 +++
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{
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4 files changed, 53 insertions(+), 5 deletions(-)
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+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
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+ return;
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diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
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*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
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index e5a2e0e..b58fef7 100644
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*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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switch (*plltype) {
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -13,6 +13,9 @@
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#include <linux/ssb/ssb_driver_chipcommon.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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+#ifdef CONFIG_BCM47XX
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+#include <asm/mach-bcm47xx/nvram.h>
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+#endif
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#include "ssb_private.h"
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@@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
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u32 pmuctl, tmp, pllctl;
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unsigned int i;
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- if ((bus->chip_id == 0x5354) && !crystalfreq) {
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- /* The 5354 crystal freq is 25MHz */
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- crystalfreq = 25000;
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- }
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if (crystalfreq)
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e = pmu0_plltab_find_entry(crystalfreq);
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if (!e)
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@@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
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u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
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if (bus->bustype == SSB_BUSTYPE_SSB) {
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- /* TODO: The user may override the crystal frequency. */
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+#ifdef CONFIG_BCM47XX
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+ char buf[20];
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+ if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
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+ crystalfreq = simple_strtoul(buf, NULL, 0);
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+#endif
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}
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switch (bus->chip_id) {
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@@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
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ssb_pmu1_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4328:
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+ ssb_pmu0_pllinit_r0(cc, crystalfreq);
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+ break;
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case 0x5354:
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+ if (crystalfreq == 0)
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+ crystalfreq = 25000;
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ssb_pmu0_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4322:
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@@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
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EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
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EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
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+
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+u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
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+ return 240000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU cpu clock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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+
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+u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ return 120000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU controlclock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c
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index ced5015..d784ec8 100644
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--- a/drivers/ssb/driver_mipscore.c
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -241,6 +241,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
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@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
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struct ssb_bus *bus = mcore->dev->bus;
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u32 pll_type, n, m, rate = 0;
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if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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rate = 200000000;
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+ return ssb_pmu_get_cpu_clock(&bus->chipco);
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+ } else if (bus->chip_id == 0x5354) {
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+
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+ rate = 240000000;
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if (bus->extif.dev) {
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} else {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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rate = ssb_calc_clock_rate(pll_type, n, m);
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} else if (bus->chipco.dev) {
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}
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diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
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index bb6317f..d109cf0 100644
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--- a/drivers/ssb/main.c
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -1105,6 +1105,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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@@ -1094,6 +1094,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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u32 plltype;
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u32 clkctl_n, clkctl_m;
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_controlclock(&bus->chipco);
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+
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if (ssb_extif_available(&bus->extif))
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ssb_extif_get_clockcontrol(&bus->extif, &plltype,
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&clkctl_n, &clkctl_m);
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diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h
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index 7765301..a305550 100644
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--- a/drivers/ssb/ssb_private.h
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+++ b/drivers/ssb/ssb_private.h
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@@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_exit(void)
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}
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#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
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+/* driver_chipcommon_pmu.c */
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+extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
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+extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
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+
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#endif /* LINUX_SSB_PRIVATE_H_ */
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--
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1.7.5.4
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if (bus->chip_id == 0x5365) {
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rate = 100000000;
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+ } else if (bus->chip_id == 0x5354) {
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+ rate = 120000000;
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} else {
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rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
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if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
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