mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-27 17:13:11 +02:00
cleanup ifxmips and add support for both ttyS
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11578 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
parent
49c631ff53
commit
e0fb3b6396
@ -26,6 +26,18 @@ static char buf[1024];
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unsigned int *prom_cp1_base = NULL;
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unsigned int prom_cp1_size = 0;
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static inline u32
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asc_r32(unsigned long r)
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{
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return ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF + r));
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}
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static inline void
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asc_w32(u32 v, unsigned long r)
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{
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ifxmips_w32(v, (u32*)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF + r));
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}
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void
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prom_free_prom_memory(void)
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{
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@ -34,11 +46,15 @@ prom_free_prom_memory(void)
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void
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prom_putchar(char c)
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{
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while((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
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unsigned long flags;
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local_irq_save(flags);
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while((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
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if(c == '\n')
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ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
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ifxmips_w32(c, IFXMIPS_ASC1_TBUF);
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asc_w32('\r', IFXMIPS_ASC_TBUF);
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asc_w32(c, IFXMIPS_ASC_TBUF);
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local_irq_restore(flags);
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}
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void
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@ -147,7 +147,7 @@ ifxmips_led_probe(struct platform_device *dev)
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struct ifxmips_led *tmp = kzalloc(sizeof(struct ifxmips_led), GFP_KERNEL);
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tmp->cdev.brightness_set = ifxmips_ledapi_set;
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tmp->cdev.name = kmalloc(sizeof("ifxmips:led:00"), GFP_KERNEL);
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sprintf(tmp->cdev.name, "ifxmips:led:%02d", i);
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sprintf((char*)tmp->cdev.name, "ifxmips:led:%02d", i);
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tmp->cdev.default_trigger = NULL;
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tmp->bit = i;
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led_classdev_register(&dev->dev, &tmp->cdev);
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@ -1,6 +1,4 @@
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/*
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* Driver for IFXMIPSASC serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -60,7 +58,7 @@
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static void ifxmipsasc_tx_chars(struct uart_port *port);
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extern void prom_printf(const char * fmt, ...);
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static struct uart_port ifxmipsasc_port;
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static struct uart_port ifxmipsasc_port[2];
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static struct uart_driver ifxmipsasc_reg;
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static unsigned int uartclk = 0;
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extern unsigned int ifxmips_get_fpi_hz(void);
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@ -68,7 +66,6 @@ extern unsigned int ifxmips_get_fpi_hz(void);
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static void
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ifxmipsasc_stop_tx(struct uart_port *port)
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{
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/* fifo underrun shuts up after firing once */
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return;
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}
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@ -76,26 +73,21 @@ static void
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ifxmipsasc_start_tx(struct uart_port *port)
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{
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unsigned long flags;
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local_irq_save(flags);
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ifxmipsasc_tx_chars(port);
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local_irq_restore(flags);
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return;
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}
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static void
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ifxmipsasc_stop_rx(struct uart_port *port)
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{
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/* clear the RX enable bit */
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ifxmips_w32(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
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ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
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}
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static void
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ifxmipsasc_enable_ms(struct uart_port *port)
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{
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/* no modem signals */
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return;
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}
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static void
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@ -104,12 +96,12 @@ ifxmipsasc_rx_chars (struct uart_port *port)
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struct tty_struct *tty = port->info->tty;
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unsigned int ch = 0, rsr = 0, fifocnt;
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fifocnt = ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
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fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
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while(fifocnt--)
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{
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u8 flag = TTY_NORMAL;
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ch = ifxmips_r32(IFXMIPS_ASC1_RBUF);
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rsr = (ifxmips_r32(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
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ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF);
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rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
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tty_flip_buffer_push(tty);
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port->icount.rx++;
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@ -117,17 +109,21 @@ ifxmipsasc_rx_chars (struct uart_port *port)
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* Note that the error handling code is
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* out of the main execution path
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*/
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if (rsr & ASCSTATE_ANY) {
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if (rsr & ASCSTATE_PE) {
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if(rsr & ASCSTATE_ANY)
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{
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if(rsr & ASCSTATE_PE)
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{
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port->icount.parity++;
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
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} else if (rsr & ASCSTATE_FE) {
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE);
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} else if(rsr & ASCSTATE_FE)
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{
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port->icount.frame++;
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE);
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}
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if (rsr & ASCSTATE_ROE) {
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if(rsr & ASCSTATE_ROE)
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{
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port->icount.overrun++;
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
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}
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rsr &= port->read_status_mask;
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@ -151,7 +147,6 @@ ifxmipsasc_rx_chars (struct uart_port *port)
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}
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if(ch != 0)
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tty_flip_buffer_push(tty);
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return;
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}
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@ -161,16 +156,18 @@ ifxmipsasc_tx_chars (struct uart_port *port)
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{
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struct circ_buf *xmit = &port->info->xmit;
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if (uart_tx_stopped(port)) {
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if(uart_tx_stopped(port))
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{
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ifxmipsasc_stop_tx(port);
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return;
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}
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while(((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
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while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
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>> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
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{
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if (port->x_char) {
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ifxmips_w32(port->x_char, IFXMIPS_ASC1_TBUF);
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if(port->x_char)
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{
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ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
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port->icount.tx++;
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port->x_char = 0;
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continue;
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@ -179,7 +176,7 @@ ifxmipsasc_tx_chars (struct uart_port *port)
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if(uart_circ_empty(xmit))
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break;
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ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
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ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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@ -189,32 +186,32 @@ ifxmipsasc_tx_chars (struct uart_port *port)
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}
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static irqreturn_t
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ifxmipsasc_tx_int (int irq, void *port)
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ifxmipsasc_tx_int(int irq, void *_port)
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{
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ifxmips_w32(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
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struct uart_port *port = (struct uart_port*) _port;
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ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
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ifxmipsasc_start_tx(port);
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ifxmips_mask_and_ack_irq(irq);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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ifxmipsasc_er_int (int irq, void *port)
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ifxmipsasc_er_int(int irq, void *_port)
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{
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struct uart_port *port = (struct uart_port*) _port;
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/* clear any pending interrupts */
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
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ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE |
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ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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ifxmipsasc_rx_int (int irq, void *port)
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ifxmipsasc_rx_int(int irq, void *_port)
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{
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ifxmips_w32(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
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struct uart_port *port = (struct uart_port*)_port;
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ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
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ifxmipsasc_rx_chars((struct uart_port*)port);
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ifxmips_mask_and_ack_irq(irq);
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return IRQ_HANDLED;
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}
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@ -222,9 +219,7 @@ static unsigned int
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ifxmipsasc_tx_empty(struct uart_port *port)
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{
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int status;
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status = ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
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status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
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return status ? 0 : TIOCSER_TEMT;
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}
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@ -237,32 +232,11 @@ ifxmipsasc_get_mctrl (struct uart_port *port)
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static void
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ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl)
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{
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return;
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}
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static void
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ifxmipsasc_break_ctl(struct uart_port *port, int break_state)
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{
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return;
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}
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static void
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ifxmipsasc1_hw_init (void)
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{
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/* this setup was probably already done in ROM/u-boot but we do it again*/
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/* TODO: GPIO pins are multifunction */
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
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ifxmips_w32((ifxmips_r32(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
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ifxmips_w32(0, IFXMIPS_ASC1_PISEL);
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ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
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ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
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ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
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ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
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wmb ();
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/*framing, overrun, enable */
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
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IFXMIPS_ASC1_CON);
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}
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static int
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@ -271,67 +245,67 @@ ifxmipsasc_startup (struct uart_port *port)
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unsigned long flags;
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int retval;
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/* this assumes: CON.BRS = CON.FDE = 0 */
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if(uartclk == 0)
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uartclk = ifxmips_get_fpi_hz();
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ifxmipsasc_port.uartclk = uartclk;
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port->uartclk = uartclk;
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ifxmipsasc1_hw_init();
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
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ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
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ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
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ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
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ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
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wmb ();
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
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local_irq_save(flags);
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retval = request_irq(IFXMIPSASC1_RIR, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
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if (retval){
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retval = request_irq(port->irq, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
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if(retval)
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{
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printk("failed to request ifxmipsasc_rx_int\n");
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return retval;
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}
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retval = request_irq(IFXMIPSASC1_TIR, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
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if (retval){
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retval = request_irq(port->irq + 2, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
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if(retval)
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{
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printk("failed to request ifxmipsasc_tx_int\n");
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goto err1;
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}
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retval = request_irq(IFXMIPSASC1_EIR, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
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if (retval){
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retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
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if(retval)
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{
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printk("failed to request ifxmipsasc_er_int\n");
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goto err2;
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}
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ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
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IFXMIPS_ASC1_IRNREN);
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ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN);
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local_irq_restore(flags);
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return 0;
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err2:
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free_irq(IFXMIPSASC1_TIR, port);
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free_irq(port->irq + 2, port);
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err1:
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free_irq(IFXMIPSASC1_RIR, port);
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free_irq(port->irq, port);
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local_irq_restore(flags);
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return retval;
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}
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static void
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ifxmipsasc_shutdown(struct uart_port *port)
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{
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free_irq(IFXMIPSASC1_RIR, port);
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free_irq(IFXMIPSASC1_TIR, port);
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free_irq(IFXMIPSASC1_EIR, port);
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/*
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* disable the baudrate generator to disable the ASC
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*/
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ifxmips_w32(0, IFXMIPS_ASC1_CON);
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free_irq(port->irq, port);
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free_irq(port->irq + 2, port);
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free_irq(port->irq + 3, port);
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/* flush and then disable the fifos */
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
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ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
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ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON);
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON);
|
||||
}
|
||||
|
||||
static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
|
||||
@ -346,8 +320,8 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
|
||||
cflag = new->c_cflag;
|
||||
iflag = new->c_iflag;
|
||||
|
||||
/* byte size and parity */
|
||||
switch (cflag & CSIZE) {
|
||||
switch(cflag & CSIZE)
|
||||
{
|
||||
case CS7:
|
||||
con = ASCCON_M_7ASYNC;
|
||||
break;
|
||||
@ -362,7 +336,8 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
|
||||
if(cflag & CSTOPB)
|
||||
con |= ASCCON_STP;
|
||||
|
||||
if (cflag & PARENB) {
|
||||
if(cflag & PARENB)
|
||||
{
|
||||
if(!(cflag & PARODD))
|
||||
con &= ~ASCCON_ODD;
|
||||
else
|
||||
@ -377,7 +352,8 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
|
||||
if(iflag & IGNPAR)
|
||||
port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
|
||||
|
||||
if (iflag & IGNBRK) {
|
||||
if(iflag & IGNBRK)
|
||||
{
|
||||
/*
|
||||
* If we're ignoring parity and break indicators,
|
||||
* ignore overruns too (for real raw support).
|
||||
@ -395,7 +371,7 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
|
||||
local_irq_save(flags);
|
||||
|
||||
/* set up CON */
|
||||
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON);
|
||||
|
||||
/* Set baud rate - take a divider of 2 into account */
|
||||
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
|
||||
@ -403,22 +379,22 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
|
||||
quot = quot / 2 - 1;
|
||||
|
||||
/* disable the baudrate generator */
|
||||
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON);
|
||||
|
||||
/* make sure the fractional divider is off */
|
||||
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON);
|
||||
|
||||
/* set up to use divisor of 2 */
|
||||
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON);
|
||||
|
||||
/* now we can write the new baudrate into the register */
|
||||
ifxmips_w32(quot, IFXMIPS_ASC1_BG);
|
||||
ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG);
|
||||
|
||||
/* turn the baudrate generator back on */
|
||||
ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
|
||||
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON);
|
||||
|
||||
/* enable rx */
|
||||
ifxmips_w32(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
|
||||
ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
@ -432,7 +408,6 @@ ifxmipsasc_type (struct uart_port *port)
|
||||
static void
|
||||
ifxmipsasc_release_port(struct uart_port *port)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static int
|
||||
@ -444,7 +419,8 @@ ifxmipsasc_request_port (struct uart_port *port)
|
||||
static void
|
||||
ifxmipsasc_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
if (flags & UART_CONFIG_TYPE) {
|
||||
if(flags & UART_CONFIG_TYPE)
|
||||
{
|
||||
port->type = PORT_IFXMIPSASC;
|
||||
ifxmipsasc_request_port(port);
|
||||
}
|
||||
@ -463,7 +439,8 @@ ifxmipsasc_verify_port (struct uart_port *port, struct serial_struct *ser)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct uart_ops ifxmipsasc_pops = {
|
||||
static struct uart_ops ifxmipsasc_pops =
|
||||
{
|
||||
.tx_empty = ifxmipsasc_tx_empty,
|
||||
.set_mctrl = ifxmipsasc_set_mctrl,
|
||||
.get_mctrl = ifxmipsasc_get_mctrl,
|
||||
@ -482,17 +459,29 @@ static struct uart_ops ifxmipsasc_pops = {
|
||||
.verify_port = ifxmipsasc_verify_port,
|
||||
};
|
||||
|
||||
static struct uart_port ifxmipsasc_port = {
|
||||
membase: (void *)IFXMIPS_ASC1_BASE_ADDR,
|
||||
mapbase: IFXMIPS_ASC1_BASE_ADDR,
|
||||
static struct uart_port ifxmipsasc_port[2] =
|
||||
{
|
||||
{
|
||||
membase: (void *)IFXMIPS_ASC_BASE_ADDR,
|
||||
mapbase: IFXMIPS_ASC_BASE_ADDR,
|
||||
iotype: SERIAL_IO_MEM,
|
||||
irq: IFXMIPSASC1_RIR,
|
||||
irq: IFXMIPSASC_RIR(0),
|
||||
uartclk: 0,
|
||||
fifosize: 16,
|
||||
unused: {IFXMIPSASC1_TIR, IFXMIPSASC1_EIR},
|
||||
type: PORT_IFXMIPSASC,
|
||||
ops: &ifxmipsasc_pops,
|
||||
flags: ASYNC_BOOT_AUTOCONF,
|
||||
}, {
|
||||
membase: (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF),
|
||||
mapbase: IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF,
|
||||
iotype: SERIAL_IO_MEM,
|
||||
irq: IFXMIPSASC_RIR(1),
|
||||
uartclk: 0,
|
||||
fifosize: 16,
|
||||
type: PORT_IFXMIPSASC,
|
||||
ops: &ifxmipsasc_pops,
|
||||
flags: ASYNC_BOOT_AUTOCONF,
|
||||
}
|
||||
};
|
||||
|
||||
static void
|
||||
@ -507,25 +496,23 @@ ifxmipsasc_console_write (struct console *co, const char *s, u_int count)
|
||||
/* wait until the FIFO is not full */
|
||||
do
|
||||
{
|
||||
fifocnt = (ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
|
||||
fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (co->index * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
|
||||
>> ASCFSTAT_TXFFLOFF;
|
||||
}while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
|
||||
|
||||
if(s[i] == '\0')
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if(s[i] == '\n')
|
||||
{
|
||||
ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
|
||||
ifxmips_w32('\r', (u32*)(IFXMIPS_ASC_BASE_ADDR + (co->index * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
|
||||
do
|
||||
{
|
||||
fifocnt = (ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
|
||||
fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (co->index * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
|
||||
>> ASCFSTAT_TXFFLOFF;
|
||||
} while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
|
||||
}
|
||||
ifxmips_w32(s[i], IFXMIPS_ASC1_TBUF);
|
||||
ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (co->index * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
@ -543,44 +530,55 @@ ifxmipsasc_console_setup (struct console *co, char *options)
|
||||
if(uartclk == 0)
|
||||
uartclk = ifxmips_get_fpi_hz();
|
||||
co->index = 0;
|
||||
port = &ifxmipsasc_port;
|
||||
ifxmipsasc_port.uartclk = uartclk;
|
||||
ifxmipsasc_port.type = PORT_IFXMIPSASC;
|
||||
port = &ifxmipsasc_port[co->index];
|
||||
ifxmipsasc_port[co->index].uartclk = uartclk;
|
||||
ifxmipsasc_port[co->index].type = PORT_IFXMIPSASC;
|
||||
|
||||
if (options){
|
||||
if(options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
}
|
||||
|
||||
return uart_set_options(port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct uart_driver ifxmipsasc_reg;
|
||||
static struct console ifxmipsasc_console = {
|
||||
static struct console ifxmipsasc_console[2] =
|
||||
{
|
||||
{
|
||||
name: "ttyS",
|
||||
write: ifxmipsasc_console_write,
|
||||
device: uart_console_device,
|
||||
setup: ifxmipsasc_console_setup,
|
||||
flags: CON_PRINTBUFFER,
|
||||
index: -1,
|
||||
index: 0,
|
||||
data: &ifxmipsasc_reg,
|
||||
}, {
|
||||
name: "ttyS",
|
||||
write: ifxmipsasc_console_write,
|
||||
device: uart_console_device,
|
||||
setup: ifxmipsasc_console_setup,
|
||||
flags: CON_PRINTBUFFER,
|
||||
index: 1,
|
||||
data: &ifxmipsasc_reg,
|
||||
}
|
||||
};
|
||||
|
||||
static int __init
|
||||
ifxmipsasc_console_init(void)
|
||||
{
|
||||
register_console(&ifxmipsasc_console);
|
||||
register_console(&ifxmipsasc_console[0]);
|
||||
register_console(&ifxmipsasc_console[1]);
|
||||
return 0;
|
||||
}
|
||||
console_initcall(ifxmipsasc_console_init);
|
||||
|
||||
static struct uart_driver ifxmipsasc_reg = {
|
||||
static struct uart_driver ifxmipsasc_reg =
|
||||
{
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = "serial",
|
||||
.dev_name = "ttyS",
|
||||
.major = TTY_MAJOR,
|
||||
.minor = 64,
|
||||
.nr = 1,
|
||||
.cons = &ifxmipsasc_console,
|
||||
.nr = 2,
|
||||
.cons = ifxmipsasc_console,
|
||||
};
|
||||
|
||||
static int __init
|
||||
@ -589,7 +587,8 @@ ifxmipsasc_init (void)
|
||||
unsigned char res;
|
||||
|
||||
uart_register_driver(&ifxmipsasc_reg);
|
||||
res = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port);
|
||||
res = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]);
|
||||
res = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
@ -38,17 +38,31 @@
|
||||
|
||||
/*------------ ASC1 */
|
||||
|
||||
#define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
|
||||
#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400)
|
||||
#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400)
|
||||
|
||||
/* FIFO status register */
|
||||
#define IFXMIPS_ASC1_FSTAT ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
#define IFXMIPS_ASC_FSTAT 0x0048
|
||||
#define IFXMIPS_ASC_TBUF 0x0020
|
||||
#define IFXMIPS_ASC_WHBSTATE 0x0018
|
||||
#define IFXMIPS_ASC_RBUF 0x0024
|
||||
#define IFXMIPS_ASC_STATE 0x0014
|
||||
#define IFXMIPS_ASC_IRNCR 0x00F8
|
||||
#define IFXMIPS_ASC_CLC 0x0000
|
||||
#define IFXMIPS_ASC_PISEL 0x0004
|
||||
#define IFXMIPS_ASC_TXFCON 0x0044
|
||||
#define IFXMIPS_ASC_RXFCON 0x0040
|
||||
#define IFXMIPS_ASC_CON 0x0010
|
||||
#define IFXMIPS_ASC_BG 0x0050
|
||||
#define IFXMIPS_ASC_IRNREN 0x00F4
|
||||
|
||||
/* ASC1 transmit buffer */
|
||||
#define IFXMIPS_ASC1_TBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
|
||||
|
||||
/* channel operating modes */
|
||||
#define IFXMIPS_ASC_CLC_DISS 0x2
|
||||
#define ASC_IRNREN_RX_BUF 0x8
|
||||
#define ASC_IRNREN_TX_BUF 0x4
|
||||
#define ASC_IRNREN_ERR 0x2
|
||||
#define ASC_IRNREN_TX 0x1
|
||||
#define ASC_IRNCR_TIR 0x4
|
||||
#define ASC_IRNCR_RIR 0x2
|
||||
#define ASC_IRNCR_EIR 0x4
|
||||
#define ASCOPT_CSIZE 0x3
|
||||
#define ASCOPT_CS7 0x1
|
||||
#define ASCOPT_CS8 0x2
|
||||
@ -56,50 +70,9 @@
|
||||
#define ASCOPT_STOPB 0x8
|
||||
#define ASCOPT_PARODD 0x0
|
||||
#define ASCOPT_CREAD 0x20
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
/* hardware modified control register */
|
||||
#define IFXMIPS_ASC1_WHBSTATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
|
||||
|
||||
/* receive buffer register */
|
||||
#define IFXMIPS_ASC1_RBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
|
||||
|
||||
/* status register */
|
||||
#define IFXMIPS_ASC1_STATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
|
||||
|
||||
/* interrupt control */
|
||||
#define IFXMIPS_ASC1_IRNCR ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
|
||||
|
||||
#define ASC_IRNCR_TIR 0x4
|
||||
#define ASC_IRNCR_RIR 0x2
|
||||
#define ASC_IRNCR_EIR 0x4
|
||||
|
||||
/* clock control */
|
||||
#define IFXMIPS_ASC1_CLC ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
|
||||
|
||||
#define IFXMIPS_ASC1_CLC_DISS 0x2
|
||||
|
||||
/* port input select register */
|
||||
#define IFXMIPS_ASC1_PISEL ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
|
||||
|
||||
/* tx fifo */
|
||||
#define IFXMIPS_ASC1_TXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
|
||||
|
||||
/* rx fifo */
|
||||
#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
|
||||
|
||||
/* control */
|
||||
#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
|
||||
|
||||
/* timer reload */
|
||||
#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
|
||||
|
||||
/* int enable */
|
||||
#define IFXMIPS_ASC1_IRNREN ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
|
||||
|
||||
#define ASC_IRNREN_RX_BUF 0x8
|
||||
#define ASC_IRNREN_TX_BUF 0x4
|
||||
#define ASC_IRNREN_ERR 0x2
|
||||
#define ASC_IRNREN_TX 0x1
|
||||
|
||||
|
||||
/*------------ RCU */
|
||||
|
||||
@ -28,9 +28,9 @@
|
||||
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
|
||||
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
|
||||
|
||||
#define IFXMIPSASC1_TIR (INT_NUM_IM3_IRL0 + 7)
|
||||
#define IFXMIPSASC1_RIR (INT_NUM_IM3_IRL0 + 9)
|
||||
#define IFXMIPSASC1_EIR (INT_NUM_IM3_IRL0 + 10)
|
||||
#define IFXMIPSASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7))
|
||||
#define IFXMIPSASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2)
|
||||
#define IFXMIPSASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3)
|
||||
|
||||
#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
|
||||
#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
|
||||
|
||||
@ -20,8 +20,8 @@
|
||||
#ifndef _IFXPROM_H__
|
||||
#define _IFXPROM_H__
|
||||
|
||||
void prom_printf(const char * fmt, ...);
|
||||
u32 *prom_get_cp1_base(void);
|
||||
u32 prom_get_cp1_size(void);
|
||||
extern void prom_printf(const char * fmt, ...);
|
||||
extern u32 *prom_get_cp1_base(void);
|
||||
extern u32 prom_get_cp1_size(void);
|
||||
|
||||
#endif
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
*
|
||||
* Copyright (C) 2005 infineon
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef IFXMIPS_WDT_H
|
||||
|
||||
@ -1,4 +1,6 @@
|
||||
/*
|
||||
* include/asm-mips/mach-ifxmips/gpio.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
@ -14,81 +16,63 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _IFXMIPS_GPIO_H_
|
||||
#define _IFXMIPS_GPIO_H_
|
||||
|
||||
#include <asm/ifxmips/ifxmips.h>
|
||||
#include <asm/ifxmips/ifxmips_gpio.h>
|
||||
|
||||
static inline int
|
||||
gpio_direction_input(unsigned gpio)
|
||||
{
|
||||
static inline int gpio_direction_input(unsigned gpio) {
|
||||
ifxmips_port_set_dir_in(0, gpio);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
gpio_direction_output(unsigned gpio, int value)
|
||||
{
|
||||
static inline int gpio_direction_output(unsigned gpio, int value) {
|
||||
ifxmips_port_set_dir_out(0, gpio);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
gpio_get_value(unsigned gpio)
|
||||
{
|
||||
static inline int gpio_get_value(unsigned gpio) {
|
||||
ifxmips_port_get_input(0, gpio);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
gpio_set_value(unsigned gpio, int value)
|
||||
{
|
||||
static inline void gpio_set_value(unsigned gpio, int value) {
|
||||
ifxmips_port_set_output(0, gpio);
|
||||
}
|
||||
|
||||
static inline int
|
||||
gpio_request(unsigned gpio, const char *label)
|
||||
{
|
||||
static inline int gpio_request(unsigned gpio, const char *label) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
gpio_free(unsigned gpio)
|
||||
{
|
||||
static inline void gpio_free(unsigned gpio) {
|
||||
}
|
||||
|
||||
static inline int
|
||||
gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
static inline int gpio_to_irq(unsigned gpio) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
irq_to_gpio(unsigned irq)
|
||||
{
|
||||
static inline int irq_to_gpio(unsigned irq) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
gpio_cansleep(unsigned gpio)
|
||||
{
|
||||
static inline int gpio_cansleep(unsigned gpio) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
gpio_get_value_cansleep(unsigned gpio)
|
||||
{
|
||||
static inline int gpio_get_value_cansleep(unsigned gpio) {
|
||||
might_sleep();
|
||||
return gpio_get_value(gpio);
|
||||
}
|
||||
|
||||
static inline void
|
||||
gpio_set_value_cansleep(unsigned gpio, int value)
|
||||
{
|
||||
static inline void gpio_set_value_cansleep(unsigned gpio, int value) {
|
||||
might_sleep();
|
||||
gpio_set_value(gpio, value);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -1,4 +1,6 @@
|
||||
/*
|
||||
* include/asm-mips/mach-ifxmips/irq.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
@ -14,6 +16,7 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __IFXMIPS_IRQ_H
|
||||
|
||||
@ -1,21 +1,9 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MIPS_MACH_IFXMIPS_WAR_H
|
||||
#define __ASM_MIPS_MACH_IFXMIPS_WAR_H
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user