From e23045f2079900b98a20feaea6238ccdef429e58 Mon Sep 17 00:00:00 2001 From: juhosg Date: Sat, 17 Apr 2010 09:43:16 +0000 Subject: [PATCH] backfire: ar71xx: nuke clocksource init patches, it is not required since 2.6.27 (backport of r20764) git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@20954 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../902-mips_clocksource_init_war.patch | 56 ------------------- 1 file changed, 56 deletions(-) delete mode 100644 target/linux/ar71xx/patches-2.6.32/902-mips_clocksource_init_war.patch diff --git a/target/linux/ar71xx/patches-2.6.32/902-mips_clocksource_init_war.patch b/target/linux/ar71xx/patches-2.6.32/902-mips_clocksource_init_war.patch deleted file mode 100644 index 894eed1e5..000000000 --- a/target/linux/ar71xx/patches-2.6.32/902-mips_clocksource_init_war.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -16,6 +16,22 @@ - #include - - /* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ -+/* - * The SMTC Kernel for the 34K, 1004K, et. al. replaces several - * of these routines with SMTC-specific variants. - */ -@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } -@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void) - return (read_c0_cause() >> cp0_compare_irq) & 0x100; - } - --/* -- * Compare interrupt can be routed and latched outside the core, -- * so a single execution hazard barrier may not be enough to give -- * it time to clear as seen in the Cause register. 4 time the -- * pipeline depth seems reasonably conservative, and empirically -- * works better in configurations with high CPU/bus clock ratios. -- */ -- --#define compare_change_hazard() \ -- do { \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- } while (0) -- - int c0_compare_int_usable(void) - { - unsigned int delta;