mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-28 15:58:25 +02:00
Merge branch 'xburst' of git@projects.qi-hardware.com:openwrt-xburst into xburst
This commit is contained in:
Mirko Vogt
commit
e3d5315aa1
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 platform timer support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
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#ifndef __ASM_MACH_JZ4740_TIMER
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#define __ASM_MACH_JZ4740_TIMER
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void jz4740_timer_enable_watchdog(void);
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void jz4740_timer_disable_watchdog(void);
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#endif
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@ -15,7 +15,7 @@
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#ifndef __ASM_JZ4740_CLOCK_H__
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#define __ASM_JZ4740_CLOCK_H__
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#include <asm/mach-jz4740/ops.h>
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#include <asm/mach-jz4740/regs.h>
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#ifndef JZ_EXTAL
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//#define JZ_EXTAL 3686400 /* 3.6864 MHz */
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@ -25,6 +25,135 @@
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#define JZ_EXTAL2 32768 /* 32.768 KHz */
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#endif
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/***************************************************************************
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* CPM
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***************************************************************************/
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#define __cpm_get_pllm() \
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((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
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#define __cpm_get_plln() \
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((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
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#define __cpm_get_pllod() \
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((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
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#define __cpm_get_cdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
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#define __cpm_get_hdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
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#define __cpm_get_pdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
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#define __cpm_get_mdiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
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#define __cpm_get_ldiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
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#define __cpm_get_udiv() \
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((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
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#define __cpm_get_i2sdiv() \
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((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
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#define __cpm_get_pixdiv() \
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((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
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#define __cpm_get_mscdiv() \
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((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
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#define __cpm_get_uhcdiv() \
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((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
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#define __cpm_get_ssidiv() \
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((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
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#define __cpm_set_cdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
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#define __cpm_set_hdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
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#define __cpm_set_pdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
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#define __cpm_set_mdiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
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#define __cpm_set_ldiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
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#define __cpm_set_udiv(v) \
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(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
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#define __cpm_set_i2sdiv(v) \
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(REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
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#define __cpm_set_pixdiv(v) \
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(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
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#define __cpm_set_mscdiv(v) \
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(REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
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#define __cpm_set_uhcdiv(v) \
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(REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT)))
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#define __cpm_ssiclk_select_exclk() \
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(REG_CPM_SSICDR &= ~CPM_SSICDR_SCS)
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#define __cpm_ssiclk_select_pllout() \
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(REG_CPM_SSICDR |= CPM_SSICDR_SCS)
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#define __cpm_set_ssidiv(v) \
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(REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
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#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
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#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
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#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
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#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
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#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
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#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
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#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
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#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
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#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
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#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
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#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
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#define __cpm_get_cclk_doze_duty() \
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((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
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#define __cpm_set_cclk_doze_duty(v) \
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(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
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#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
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#define __cpm_idle_mode() \
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(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
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#define __cpm_sleep_mode() \
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(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
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#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
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#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
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#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
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#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
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#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
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#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
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#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
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#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
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#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
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#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
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#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
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#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
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#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
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#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
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#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
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#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
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#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
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#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
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#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
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#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
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#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
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#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
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#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
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#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
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#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
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#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
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#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
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#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
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#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
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#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
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#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
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#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
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#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
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#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
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#define __cpm_get_o1st() \
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((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
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#define __cpm_set_o1st(v) \
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(REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
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#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
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#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
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/*
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* JZ4740 clocks structure
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*/
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@ -25,6 +25,7 @@ enum jz_gpio_function {
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JZ_GPIO_FUNC3,
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};
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/*
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Usually a driver for a SoC component has to request several gpio pins and
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configure them as funcion pins.
|
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@ -68,6 +69,11 @@ void jz_gpio_enable_pullup(unsigned gpio);
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void jz_gpio_disable_pullup(unsigned gpio);
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int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
|
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int jz_gpio_port_direction_input(int port, uint32_t mask);
|
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int jz_gpio_port_direction_output(int port, uint32_t mask);
|
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void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
|
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uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
|
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|
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#include <asm/mach-generic/gpio.h>
|
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#define JZ_GPIO_PORTA(x) (x + 32 * 0)
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@ -4,7 +4,7 @@
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#define MIPS_CPU_IRQ_BASE 0
|
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#define JZ_IRQ_BASE 8
|
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|
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// 1st-level interrupts
|
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/* 1st-level interrupts */
|
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#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
|
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#define JZ_IRQ_I2C JZ_IRQ(1)
|
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#define JZ_IRQ_UHC JZ_IRQ(3)
|
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|
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@ -16,7 +16,6 @@
|
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#define __ASM_JZ4740_H__
|
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|
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#include <asm/mach-jz4740/regs.h>
|
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#include <asm/mach-jz4740/ops.h>
|
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#include <asm/mach-jz4740/dma.h>
|
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|
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/*------------------------------------------------------------------
|
||||
@ -34,7 +33,6 @@
|
||||
* Follows are related to platform definitions
|
||||
*/
|
||||
|
||||
#include <asm/mach-jz4740/clock.h>
|
||||
#include <asm/mach-jz4740/serial.h>
|
||||
|
||||
#endif /* __ASM_JZ4740_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 platform timer support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_JZ4740_TIMER
|
||||
#define __ASM_MACH_JZ4740_TIMER
|
||||
|
||||
void jz4740_timer_enable_watchdog(void);
|
||||
void jz4740_timer_disable_watchdog(void);
|
||||
|
||||
#endif
|
||||
@ -524,9 +524,11 @@ static struct divided_clk jz_clk_i2s = {
|
||||
.name = "i2s",
|
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.parent = &jz_clk_ext.clk,
|
||||
.gate_bit = JZ_CLOCK_GATE_AIC,
|
||||
.set_parent = jz_clk_i2s_set_parent,
|
||||
.set_rate = jz_clk_divided_set_rate,
|
||||
.get_rate = jz_clk_divided_get_rate,
|
||||
.enable = jz_clk_enable_gating,
|
||||
.disable = jz_clk_disable_gating,
|
||||
.set_parent = jz_clk_i2s_set_parent,
|
||||
},
|
||||
.reg = JZ_REG_CLOCK_I2S,
|
||||
.mask = JZ_CLOCK_I2S_DIV_MASK,
|
||||
|
||||
@ -18,10 +18,9 @@
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/mach-jz4740/dma.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
|
||||
#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
|
||||
#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ74xx platform GPIO support
|
||||
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 platform GPIO support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
@ -22,13 +22,9 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
|
||||
#define JZ_GPIO_BASE_A (32*0)
|
||||
#define JZ_GPIO_BASE_B (32*1)
|
||||
#define JZ_GPIO_BASE_C (32*2)
|
||||
@ -183,7 +179,6 @@ void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
|
||||
|
||||
|
||||
void jz_gpio_enable_pullup(unsigned gpio)
|
||||
{
|
||||
jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
|
||||
@ -258,24 +253,7 @@ EXPORT_SYMBOL(jz_gpio_port_get_value);
|
||||
#define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
|
||||
#define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
|
||||
|
||||
|
||||
#define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
|
||||
#define IRQ_TO_PIN_REG(irq) IRQ_TO_REG(irq, 0x00)
|
||||
#define IRQ_TO_MASK_REG(irq) IRQ_TO_REG(irq, 0x20)
|
||||
#define IRQ_TO_MASK_SET_REG(irq) IRQ_TO_REG(irq, 0x24)
|
||||
#define IRQ_TO_MASK_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x28)
|
||||
#define IRQ_TO_SELECT_REG(irq) IRQ_TO_REG(irq, 0x50)
|
||||
#define IRQ_TO_SELECT_SET_REG(irq) IRQ_TO_REG(irq, 0x54)
|
||||
#define IRQ_TO_SELECT_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x58)
|
||||
#define IRQ_TO_DIRECTION_REG(irq) IRQ_TO_REG(irq, 0x60)
|
||||
#define IRQ_TO_DIRECTION_SET_REG(irq) IRQ_TO_REG(irq, 0x64)
|
||||
#define IRQ_TO_DIRECTION_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x68)
|
||||
#define IRQ_TO_TRIGGER_REG(irq) IRQ_TO_REG(irq, 0x70)
|
||||
#define IRQ_TO_TRIGGER_SET_REG(irq) IRQ_TO_REG(irq, 0x74)
|
||||
#define IRQ_TO_TRIGGER_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x78)
|
||||
#define IRQ_TO_FLAG_REG(irq) IRQ_TO_REG(irq, 0x80)
|
||||
#define IRQ_TO_FLAG_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x14)
|
||||
|
||||
|
||||
static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
|
||||
@ -1,18 +1,17 @@
|
||||
/*
|
||||
* linux/arch/mips/jz4740/irq.c
|
||||
*
|
||||
* JZ4740 interrupt routines.
|
||||
*
|
||||
* Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
|
||||
* Author: <lhhuang@ingenic.cn>
|
||||
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 platform IRQ support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <asm/mach-jz4740/irq.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
@ -78,7 +77,6 @@ static struct irq_chip intc_irq_type = {
|
||||
.mask = intc_irq_mask,
|
||||
.unmask = intc_irq_unmask,
|
||||
.ack = intc_irq_ack,
|
||||
.end = intc_irq_end,
|
||||
.set_wake = intc_irq_set_wake,
|
||||
};
|
||||
|
||||
@ -130,7 +128,6 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
void jz4740_intc_suspend(void)
|
||||
{
|
||||
jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
|
||||
printk("intc wakeup: %d\n", jz_intc_wakeup);
|
||||
writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
|
||||
}
|
||||
|
||||
|
||||
@ -31,7 +31,6 @@
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include <asm/mach-jz4740/clock.h>
|
||||
#include <asm/mach-jz4740/ops.h>
|
||||
|
||||
//#define DEBUG 1
|
||||
#undef DEBUG
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include <asm/mach-jz4740/timer.h>
|
||||
#include <asm/mach-jz4740/jz4740.h>
|
||||
|
||||
void jz_restart(char *command)
|
||||
@ -26,7 +27,7 @@ void jz_restart(char *command)
|
||||
REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
|
||||
REG_WDT_TCNT = 0;
|
||||
REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */
|
||||
REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */
|
||||
jz4740_timer_enable_watchdog();
|
||||
REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */
|
||||
while (1);
|
||||
}
|
||||
|
||||
@ -23,7 +23,6 @@
|
||||
#include <linux/string.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/serial.h>
|
||||
@ -38,7 +37,6 @@
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include <asm/mach-jz4740/ops.h>
|
||||
#include <asm/mach-jz4740/clock.h>
|
||||
#include <asm/mach-jz4740/serial.h>
|
||||
|
||||
@ -49,17 +47,6 @@ extern void jz_halt(void);
|
||||
extern void jz_power_off(void);
|
||||
extern void jz_time_init(void);
|
||||
|
||||
static void __init sysclocks_setup(void)
|
||||
{
|
||||
#if 0
|
||||
printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n",
|
||||
(jz_clocks.cclk + 500000) / 1000000,
|
||||
(jz_clocks.hclk + 500000) / 1000000,
|
||||
(jz_clocks.pclk + 500000) / 1000000,
|
||||
(jz_clocks.mclk + 500000) / 1000000);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init soc_cpm_setup(void)
|
||||
{
|
||||
/* Enable CKO to external memory */
|
||||
@ -67,34 +54,8 @@ static void __init soc_cpm_setup(void)
|
||||
|
||||
/* CPU enters IDLE mode when executing 'wait' instruction */
|
||||
__cpm_idle_mode();
|
||||
|
||||
/* Setup system clocks */
|
||||
sysclocks_setup();
|
||||
}
|
||||
|
||||
static void __init soc_harb_setup(void)
|
||||
{
|
||||
// __harb_set_priority(0x00); /* CIM>LCD>DMA>ETH>PCI>USB>CBB */
|
||||
// __harb_set_priority(0x03); /* LCD>CIM>DMA>ETH>PCI>USB>CBB */
|
||||
// __harb_set_priority(0x0a); /* ETH>LCD>CIM>DMA>PCI>USB>CBB */
|
||||
}
|
||||
|
||||
static void __init soc_emc_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void __init soc_dmac_setup(void)
|
||||
{
|
||||
__dmac_enable_module();
|
||||
}
|
||||
|
||||
static void __init jz_soc_setup(void)
|
||||
{
|
||||
soc_cpm_setup();
|
||||
soc_harb_setup();
|
||||
soc_emc_setup();
|
||||
soc_dmac_setup();
|
||||
}
|
||||
|
||||
static void __init jz_serial_setup(void)
|
||||
{
|
||||
@ -140,7 +101,7 @@ void __init plat_mem_setup(void)
|
||||
_machine_restart = jz_restart;
|
||||
_machine_halt = jz_halt;
|
||||
pm_power_off = jz_power_off;
|
||||
jz_soc_setup();
|
||||
soc_cpm_setup();
|
||||
jz_serial_setup();
|
||||
}
|
||||
|
||||
|
||||
@ -1,160 +1,263 @@
|
||||
/*
|
||||
* linux/arch/mips/jz4740/time.c
|
||||
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
* JZ4740 platform timer support
|
||||
*
|
||||
* Setting up the clock on the JZ4740 boards.
|
||||
*
|
||||
* Copyright (C) 2008 Ingenic Semiconductor Inc.
|
||||
* Author: <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include <asm/mach-jz4740/irq.h>
|
||||
#include <asm/mach-jz4740/jz4740.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
/* This is for machines which generate the exact clock. */
|
||||
#define JZ_REG_TIMER_STOP 0x1C
|
||||
#define JZ_REG_TIMER_STOP_SET 0x2C
|
||||
#define JZ_REG_TIMER_STOP_CLEAR 0x3C
|
||||
#define JZ_REG_TIMER_ENABLE 0x10
|
||||
#define JZ_REG_TIMER_ENABLE_SET 0x14
|
||||
#define JZ_REG_TIMER_ENABLE_CLEAR 0x18
|
||||
#define JZ_REG_TIMER_FLAG 0x20
|
||||
#define JZ_REG_TIMER_FLAG_SET 0x24
|
||||
#define JZ_REG_TIMER_FLAG_CLEAR 0x28
|
||||
#define JZ_REG_TIMER_MASK 0x30
|
||||
#define JZ_REG_TIMER_MASK_SET 0x34
|
||||
#define JZ_REG_TIMER_MASK_CLEAR 0x38
|
||||
|
||||
#define JZ_TIMER_CHAN 0
|
||||
#define JZ_TIMER_IRQ JZ_IRQ_TCU0
|
||||
#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
|
||||
#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
|
||||
#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
|
||||
#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
|
||||
|
||||
#define JZ_TIMER_CLOCK (JZ_EXTAL>>4) /* Jz timer clock frequency */
|
||||
#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
|
||||
#define JZ_TIMER_IRQ_FULL(x) BIT(x)
|
||||
|
||||
static struct clocksource clocksource_jz; /* Jz clock source */
|
||||
static struct clock_event_device jz_clockevent_device; /* Jz clock event */
|
||||
#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
|
||||
#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
|
||||
#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
|
||||
#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
|
||||
#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
|
||||
#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
|
||||
#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
|
||||
#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
|
||||
#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
|
||||
#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
|
||||
|
||||
void (*jz_timer_callback)(void);
|
||||
#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
|
||||
#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
|
||||
#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
|
||||
|
||||
static irqreturn_t jz_timer_interrupt(int irq, void *dev_id)
|
||||
static void __iomem *jz4740_timer_base;
|
||||
static uint16_t jz4740_clocksource_counter;
|
||||
static uint16_t jz4740_jiffies_per_tick;
|
||||
|
||||
void jz4740_timer_enable_watchdog(void)
|
||||
{
|
||||
struct clock_event_device *cd = dev_id;
|
||||
writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
|
||||
}
|
||||
|
||||
REG_TCU_TFCR = 1 << JZ_TIMER_CHAN; /* ACK timer */
|
||||
void jz4740_timer_disable_watchdog(void)
|
||||
{
|
||||
writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
|
||||
}
|
||||
|
||||
if (jz_timer_callback)
|
||||
jz_timer_callback();
|
||||
static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
|
||||
{
|
||||
writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
|
||||
}
|
||||
|
||||
static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
|
||||
{
|
||||
writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
|
||||
}
|
||||
|
||||
static void jz4740_init_timer(void)
|
||||
{
|
||||
uint16_t val = 0;
|
||||
val |= JZ_TIMER_CTRL_PRESCALE_16;
|
||||
val |= JZ_TIMER_CTRL_SRC_EXT;
|
||||
|
||||
writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
|
||||
writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
|
||||
writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
|
||||
writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
|
||||
}
|
||||
|
||||
static void jz4740_timer_enable(unsigned int timer)
|
||||
{
|
||||
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
|
||||
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
|
||||
}
|
||||
|
||||
static void jz4740_timer_disable(unsigned int timer)
|
||||
{
|
||||
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
|
||||
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
|
||||
}
|
||||
|
||||
static void jz4740_timer_irq_full_enable(unsigned int timer)
|
||||
{
|
||||
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
|
||||
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
|
||||
}
|
||||
|
||||
static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
|
||||
{
|
||||
return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
|
||||
JZ_TIMER_IRQ_FULL(timer));
|
||||
}
|
||||
|
||||
static void jz4740_timer_irq_full_disable(unsigned int timer)
|
||||
{
|
||||
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
|
||||
}
|
||||
|
||||
static void jz4740_timer_irq_half_enable(unsigned int timer)
|
||||
{
|
||||
writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
|
||||
writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
|
||||
}
|
||||
|
||||
static void jz4740_timer_irq_half_disable(unsigned int timer)
|
||||
{
|
||||
writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
|
||||
}
|
||||
|
||||
static cycle_t jz4740_clocksource_read(struct clocksource *cs)
|
||||
{
|
||||
uint16_t val;
|
||||
val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
|
||||
return val;
|
||||
}
|
||||
|
||||
static struct clocksource jz4740_clocksource = {
|
||||
.name = "jz4740-timer",
|
||||
.rating = 200,
|
||||
.read = jz4740_clocksource_read,
|
||||
.mask = CLOCKSOURCE_MASK(16),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
|
||||
{
|
||||
struct clock_event_device *cd = devid;
|
||||
|
||||
writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
|
||||
|
||||
if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
|
||||
jz4740_timer_disable(0);
|
||||
cd->event_handler(cd);
|
||||
} else {
|
||||
cd->event_handler(cd);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction jz_irqaction = {
|
||||
.handler = jz_timer_interrupt,
|
||||
.flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
|
||||
.name = "jz-timerirq",
|
||||
};
|
||||
|
||||
|
||||
cycle_t jz_get_cycles(void)
|
||||
{
|
||||
/* convert jiffes to jz timer cycles */
|
||||
return (cycle_t)( jiffies*((JZ_TIMER_CLOCK)/HZ) + REG_TCU_TCNT(JZ_TIMER_CHAN));
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_jz = {
|
||||
.name = "jz_clocksource",
|
||||
.rating = 300,
|
||||
.read = jz_get_cycles,
|
||||
.mask = 0xFFFF,
|
||||
.shift = 10,
|
||||
.flags = CLOCK_SOURCE_WATCHDOG,
|
||||
};
|
||||
|
||||
static int __init jz_clocksource_init(void)
|
||||
{
|
||||
clocksource_jz.mult = clocksource_hz2mult(JZ_TIMER_CLOCK, clocksource_jz.shift);
|
||||
clocksource_register(&clocksource_jz);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz_set_next_event(unsigned long evt,
|
||||
struct clock_event_device *unused)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *cd)
|
||||
{
|
||||
switch(mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
|
||||
writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
jz4740_timer_irq_full_enable(0);
|
||||
jz4740_timer_enable(0);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
jz4740_timer_disable(0);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static struct clock_event_device jz_clockevent_device = {
|
||||
.name = "jz-clockenvent",
|
||||
static int jz4740_clockevent_set_next(unsigned long evt, struct
|
||||
clock_event_device *cd)
|
||||
{
|
||||
writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
|
||||
writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
|
||||
jz4740_timer_enable(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clock_event_device jz4740_clockevent = {
|
||||
.name = "jz4740-timer",
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC,
|
||||
// .features = CLOCK_EVT_FEAT_ONESHOT, /* Jz4740 not support dynamic clock now */
|
||||
|
||||
/* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
|
||||
.mult = 1,
|
||||
.rating = 300,
|
||||
.irq = JZ_TIMER_IRQ,
|
||||
.set_mode = jz_set_mode,
|
||||
.set_next_event = jz_set_next_event,
|
||||
.set_next_event = jz4740_clockevent_set_next,
|
||||
.set_mode = jz4740_clockevent_set_mode,
|
||||
.rating = 200,
|
||||
.irq = JZ_IRQ_TCU0,
|
||||
};
|
||||
|
||||
static void __init jz_clockevent_init(void)
|
||||
{
|
||||
struct clock_event_device *cd = &jz_clockevent_device;
|
||||
unsigned int cpu = smp_processor_id();
|
||||
|
||||
cd->cpumask = cpumask_of(cpu);
|
||||
clockevents_register_device(cd);
|
||||
}
|
||||
|
||||
static void __init jz_timer_setup(void)
|
||||
{
|
||||
jz_clocksource_init(); /* init jz clock source */
|
||||
jz_clockevent_init(); /* init jz clock event */
|
||||
|
||||
/*
|
||||
* Make irqs happen for the system timer
|
||||
*/
|
||||
jz_irqaction.dev_id = &jz_clockevent_device;
|
||||
setup_irq(JZ_TIMER_IRQ, &jz_irqaction);
|
||||
}
|
||||
static struct irqaction jz_irqaction = {
|
||||
.handler = jz4740_clockevent_irq,
|
||||
.flags = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
|
||||
.name = "jz4740-timerirq",
|
||||
.dev_id = &jz4740_clockevent,
|
||||
};
|
||||
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
unsigned int latch;
|
||||
/* Init timer */
|
||||
latch = ( JZ_TIMER_CLOCK + (HZ>>1)) / HZ;
|
||||
int ret;
|
||||
uint32_t clk_rate;
|
||||
struct clk *ext_clk;
|
||||
|
||||
REG_TCU_TCSR(JZ_TIMER_CHAN) = TCU_TCSR_PRESCALE16 | TCU_TCSR_EXT_EN;
|
||||
REG_TCU_TCNT(JZ_TIMER_CHAN) = 0;
|
||||
REG_TCU_TDHR(JZ_TIMER_CHAN) = 0;
|
||||
REG_TCU_TDFR(JZ_TIMER_CHAN) = latch;
|
||||
jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
|
||||
|
||||
REG_TCU_TMSR = (1 << (JZ_TIMER_CHAN + 16)); /* mask half irq */
|
||||
REG_TCU_TMCR = (1 << JZ_TIMER_CHAN); /* unmask full irq */
|
||||
REG_TCU_TSCR = (1 << JZ_TIMER_CHAN); /* enable timer clock */
|
||||
REG_TCU_TESR = (1 << JZ_TIMER_CHAN); /* start counting up */
|
||||
|
||||
jz_timer_setup();
|
||||
if (!jz4740_timer_base) {
|
||||
printk(KERN_ERR "Failed to ioremap timer registers");
|
||||
return;
|
||||
}
|
||||
|
||||
/*ext_clk = clk_get(NULL, "ext");
|
||||
clk_rate = clk_get_rate(ext_clk) >> 4;
|
||||
clk_put(ext_clk);*/
|
||||
|
||||
|
||||
clk_rate = JZ_EXTAL >> 4;
|
||||
|
||||
jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
|
||||
|
||||
clockevent_set_clock(&jz4740_clockevent, clk_rate);
|
||||
jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
|
||||
jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
|
||||
jz4740_clockevent.cpumask = cpumask_of(0);
|
||||
|
||||
clockevents_register_device(&jz4740_clockevent);
|
||||
|
||||
clocksource_set_clock(&jz4740_clocksource, clk_rate);
|
||||
ret = clocksource_register(&jz4740_clocksource);
|
||||
|
||||
if (ret)
|
||||
printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
|
||||
|
||||
setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
|
||||
|
||||
jz4740_init_timer();
|
||||
writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
|
||||
jz4740_timer_irq_half_disable(0);
|
||||
jz4740_timer_irq_full_enable(0);
|
||||
jz4740_timer_enable(0);
|
||||
|
||||
jz4740_timer_irq_half_disable(1);
|
||||
jz4740_timer_irq_full_disable(1);
|
||||
|
||||
jz4740_timer_enable(1);
|
||||
}
|
||||
|
||||
73
target/linux/xburst/files-2.6.31/drivers/usb/gadget/jz4740_udc.c
Executable file → Normal file
73
target/linux/xburst/files-2.6.31/drivers/usb/gadget/jz4740_udc.c
Executable file → Normal file
@ -37,7 +37,6 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include <asm/mach-jz4740/clock.h>
|
||||
|
||||
#include "jz4740_udc.h"
|
||||
@ -76,6 +75,78 @@
|
||||
#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
|
||||
#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
|
||||
|
||||
/* Power register bit masks */
|
||||
#define USB_POWER_SUSPENDM 0x01
|
||||
#define USB_POWER_RESUME 0x04
|
||||
#define USB_POWER_HSMODE 0x10
|
||||
#define USB_POWER_HSENAB 0x20
|
||||
#define USB_POWER_SOFTCONN 0x40
|
||||
|
||||
/* Interrupt register bit masks */
|
||||
#define USB_INTR_SUSPEND 0x01
|
||||
#define USB_INTR_RESUME 0x02
|
||||
#define USB_INTR_RESET 0x04
|
||||
|
||||
#define USB_INTR_EP0 0x0001
|
||||
#define USB_INTR_INEP1 0x0002
|
||||
#define USB_INTR_INEP2 0x0004
|
||||
#define USB_INTR_OUTEP1 0x0002
|
||||
|
||||
/* CSR0 bit masks */
|
||||
#define USB_CSR0_OUTPKTRDY 0x01
|
||||
#define USB_CSR0_INPKTRDY 0x02
|
||||
#define USB_CSR0_SENTSTALL 0x04
|
||||
#define USB_CSR0_DATAEND 0x08
|
||||
#define USB_CSR0_SETUPEND 0x10
|
||||
#define USB_CSR0_SENDSTALL 0x20
|
||||
#define USB_CSR0_SVDOUTPKTRDY 0x40
|
||||
#define USB_CSR0_SVDSETUPEND 0x80
|
||||
|
||||
/* Endpoint CSR register bits */
|
||||
#define USB_INCSRH_AUTOSET 0x80
|
||||
#define USB_INCSRH_ISO 0x40
|
||||
#define USB_INCSRH_MODE 0x20
|
||||
#define USB_INCSRH_DMAREQENAB 0x10
|
||||
#define USB_INCSRH_DMAREQMODE 0x04
|
||||
#define USB_INCSR_CDT 0x40
|
||||
#define USB_INCSR_SENTSTALL 0x20
|
||||
#define USB_INCSR_SENDSTALL 0x10
|
||||
#define USB_INCSR_FF 0x08
|
||||
#define USB_INCSR_UNDERRUN 0x04
|
||||
#define USB_INCSR_FFNOTEMPT 0x02
|
||||
#define USB_INCSR_INPKTRDY 0x01
|
||||
#define USB_OUTCSRH_AUTOCLR 0x80
|
||||
#define USB_OUTCSRH_ISO 0x40
|
||||
#define USB_OUTCSRH_DMAREQENAB 0x20
|
||||
#define USB_OUTCSRH_DNYT 0x10
|
||||
#define USB_OUTCSRH_DMAREQMODE 0x08
|
||||
#define USB_OUTCSR_CDT 0x80
|
||||
#define USB_OUTCSR_SENTSTALL 0x40
|
||||
#define USB_OUTCSR_SENDSTALL 0x20
|
||||
#define USB_OUTCSR_FF 0x10
|
||||
#define USB_OUTCSR_DATAERR 0x08
|
||||
#define USB_OUTCSR_OVERRUN 0x04
|
||||
#define USB_OUTCSR_FFFULL 0x02
|
||||
#define USB_OUTCSR_OUTPKTRDY 0x01
|
||||
|
||||
/* Testmode register bits */
|
||||
#define USB_TEST_SE0NAK 0x01
|
||||
#define USB_TEST_J 0x02
|
||||
#define USB_TEST_K 0x04
|
||||
#define USB_TEST_PACKET 0x08
|
||||
|
||||
/* DMA control bits */
|
||||
#define USB_CNTL_ENA 0x01
|
||||
#define USB_CNTL_DIR_IN 0x02
|
||||
#define USB_CNTL_MODE_1 0x04
|
||||
#define USB_CNTL_INTR_EN 0x08
|
||||
#define USB_CNTL_EP(n) ((n) << 4)
|
||||
#define USB_CNTL_BURST_0 (0 << 9)
|
||||
#define USB_CNTL_BURST_4 (1 << 9)
|
||||
#define USB_CNTL_BURST_8 (2 << 9)
|
||||
#define USB_CNTL_BURST_16 (3 << 9)
|
||||
|
||||
|
||||
#ifndef DEBUG
|
||||
# define DEBUG(fmt,args...) do {} while(0)
|
||||
#endif
|
||||
|
||||
0
target/linux/xburst/files-2.6.31/drivers/usb/gadget/jz4740_udc.h
Executable file → Normal file
0
target/linux/xburst/files-2.6.31/drivers/usb/gadget/jz4740_udc.h
Executable file → Normal file
@ -1,282 +1,552 @@
|
||||
/*
|
||||
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Jiejing Zhang(kzjeef(at)gmail.com) 2009: Make jz soc sound card
|
||||
* loaded by soc-core.
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/initval.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dapm.h>
|
||||
#include <sound/initval.h>
|
||||
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include <asm/mach-jz4740/ops.h>
|
||||
|
||||
#include "jz4740-pcm.h"
|
||||
#include "jz4740-i2s.h"
|
||||
#include "jz4740-pcm.h"
|
||||
|
||||
static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
|
||||
#define JZ_REG_AIC_CONF 0x00
|
||||
#define JZ_REG_AIC_CTRL 0x04
|
||||
#define JZ_REG_AIC_I2S_FMT 0x10
|
||||
#define JZ_REG_AIC_FIFO_STATUS 0x14
|
||||
#define JZ_REG_AIC_I2S_STATUS 0x1c
|
||||
#define JZ_REG_AIC_CLK_DIV 0x30
|
||||
#define JZ_REG_AIC_FIFO 0x34
|
||||
|
||||
#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
|
||||
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
|
||||
#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
|
||||
#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
|
||||
#define JZ_AIC_CONF_I2S BIT(4)
|
||||
#define JZ_AIC_CONF_RESET BIT(3)
|
||||
#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
|
||||
#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
|
||||
#define JZ_AIC_CONF_ENABLE BIT(0)
|
||||
|
||||
#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
|
||||
#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
|
||||
|
||||
#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
|
||||
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
|
||||
#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
|
||||
#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
|
||||
#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
|
||||
#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
|
||||
#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
|
||||
#define JZ_AIC_CTRL_FLUSH BIT(8)
|
||||
#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
|
||||
#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
|
||||
#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
|
||||
#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
|
||||
#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
|
||||
#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
|
||||
#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
|
||||
|
||||
#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
|
||||
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
|
||||
|
||||
#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
|
||||
#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
|
||||
#define JZ_AIC_I2S_FMT_MSB BIT(0)
|
||||
|
||||
#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
|
||||
|
||||
#define JZ_AIC_CLK_DIV_MASK 0xf
|
||||
|
||||
struct jz4740_i2s {
|
||||
struct resource *mem;
|
||||
void __iomem *base;
|
||||
dma_addr_t phys_base;
|
||||
|
||||
struct clk *clk;
|
||||
|
||||
struct jz4740_pcm_config pcm_config;
|
||||
};
|
||||
|
||||
static struct jz4740_dma_config jz4740_i2s_dma_playback_config = {
|
||||
.src_width = JZ4740_DMA_WIDTH_16BIT,
|
||||
.dst_width = JZ4740_DMA_WIDTH_32BIT,
|
||||
.transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
|
||||
.request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT,
|
||||
.flags = JZ4740_DMA_SRC_AUTOINC,
|
||||
.mode = JZ4740_DMA_MODE_SINGLE,
|
||||
};
|
||||
|
||||
static struct jz4740_dma_config jz4740_i2s_dma_capture_config = {
|
||||
.src_width = JZ4740_DMA_WIDTH_32BIT,
|
||||
.dst_width = JZ4740_DMA_WIDTH_16BIT,
|
||||
.transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
|
||||
.request_type = JZ4740_DMA_TYPE_AIC_RECEIVE,
|
||||
.flags = JZ4740_DMA_DST_AUTOINC,
|
||||
.mode = JZ4740_DMA_MODE_SINGLE,
|
||||
};
|
||||
|
||||
|
||||
static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, unsigned int reg)
|
||||
{
|
||||
/*struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;*/
|
||||
return readl(i2s->base + reg);
|
||||
}
|
||||
|
||||
static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, unsigned
|
||||
int reg, uint32_t value)
|
||||
{
|
||||
writel(value, i2s->base + reg);
|
||||
}
|
||||
|
||||
static inline struct jz4740_i2s *jz4740_dai_to_i2s(struct snd_soc_dai *dai)
|
||||
{
|
||||
return dai->private_data;
|
||||
}
|
||||
|
||||
static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct
|
||||
snd_soc_dai *dai)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
uint32_t conf, ctrl;
|
||||
|
||||
if (dai->active)
|
||||
return 0;
|
||||
|
||||
conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
|
||||
ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
|
||||
|
||||
conf |= JZ_AIC_CONF_ENABLE;
|
||||
ctrl |= JZ_AIC_CTRL_FLUSH;
|
||||
|
||||
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
|
||||
clk_enable(i2s->clk);
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
|
||||
unsigned int fmt)
|
||||
static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct
|
||||
snd_soc_dai *dai)
|
||||
{
|
||||
/* interface format */
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
/* 1 : ac97 , 0 : i2s */
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
uint32_t conf;
|
||||
|
||||
if (dai->active)
|
||||
return;
|
||||
|
||||
conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
|
||||
conf &= ~JZ_AIC_CONF_ENABLE;
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
|
||||
|
||||
clk_disable(i2s->clk);
|
||||
}
|
||||
|
||||
|
||||
static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
|
||||
|
||||
uint32_t ctrl;
|
||||
uint32_t mask;
|
||||
|
||||
if (playback) {
|
||||
mask = JZ_AIC_CTRL_ENABLE_PLAYBACK |
|
||||
JZ_AIC_CTRL_ENABLE_TX_DMA;
|
||||
} else {
|
||||
mask = JZ_AIC_CTRL_ENABLE_CAPTURE |
|
||||
JZ_AIC_CTRL_ENABLE_RX_DMA;
|
||||
}
|
||||
|
||||
ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
ctrl |= mask;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_LEFT_J:
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
ctrl &= ~mask;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL,ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai,
|
||||
unsigned int fmt)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
|
||||
uint32_t format = 0;
|
||||
uint32_t conf;
|
||||
|
||||
conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
|
||||
|
||||
conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBS_CFS:
|
||||
/* 0 : slave */
|
||||
conf |= JZ_AIC_CONF_BIT_CLK_MASTER |
|
||||
JZ_AIC_CONF_SYNC_CLK_MASTER;
|
||||
format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBM_CFS:
|
||||
/* 1 : master */
|
||||
conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBS_CFM:
|
||||
conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBM_CFM:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_MSB:
|
||||
format |= JZ_AIC_I2S_FMT_MSB;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
||||
case SND_SOC_DAIFMT_NB_NF:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set Jz4740 Clock source
|
||||
*/
|
||||
static int jz4740_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
|
||||
int clk_id, unsigned int freq, int dir)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz4740_snd_tx_ctrl(int on)
|
||||
{
|
||||
if (on) {
|
||||
/* enable replay */
|
||||
__i2s_enable_transmit_dma();
|
||||
__i2s_enable_replay();
|
||||
__i2s_enable();
|
||||
|
||||
} else {
|
||||
/* disable replay & capture */
|
||||
__i2s_disable_replay();
|
||||
__i2s_disable_record();
|
||||
__i2s_disable_receive_dma();
|
||||
__i2s_disable_transmit_dma();
|
||||
__i2s_disable();
|
||||
}
|
||||
}
|
||||
|
||||
static void jz4740_snd_rx_ctrl(int on)
|
||||
{
|
||||
if (on) {
|
||||
/* enable capture */
|
||||
__i2s_enable_receive_dma();
|
||||
__i2s_enable_record();
|
||||
__i2s_enable();
|
||||
|
||||
} else {
|
||||
/* disable replay & capture */
|
||||
__i2s_disable_replay();
|
||||
__i2s_disable_record();
|
||||
__i2s_disable_receive_dma();
|
||||
__i2s_disable_transmit_dma();
|
||||
__i2s_disable();
|
||||
}
|
||||
}
|
||||
|
||||
static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
|
||||
/* int channels = params_channels(params); */
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
|
||||
int sample_size;
|
||||
enum jz4740_dma_width dma_width;
|
||||
uint32_t ctrl;
|
||||
|
||||
jz4740_snd_rx_ctrl(0);
|
||||
jz4740_snd_rx_ctrl(0);
|
||||
ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S8:
|
||||
__i2s_set_transmit_trigger(4);
|
||||
__i2s_set_receive_trigger(3);
|
||||
__i2s_set_oss_sample_size(8);
|
||||
__i2s_set_iss_sample_size(8);
|
||||
sample_size = 0;
|
||||
dma_width = JZ4740_DMA_WIDTH_8BIT;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
/* playback sample:16 bits, burst:16 bytes */
|
||||
__i2s_set_transmit_trigger(4);
|
||||
/* capture sample:16 bits, burst:16 bytes */
|
||||
__i2s_set_receive_trigger(3);
|
||||
__i2s_set_oss_sample_size(16);
|
||||
__i2s_set_iss_sample_size(16);
|
||||
case SNDRV_PCM_FORMAT_S16:
|
||||
sample_size = 1;
|
||||
dma_width = JZ4740_DMA_WIDTH_16BIT;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (playback) {
|
||||
ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
|
||||
ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
|
||||
} else {
|
||||
ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
|
||||
ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
|
||||
}
|
||||
|
||||
switch (params_channels(params)) {
|
||||
case 2:
|
||||
break;
|
||||
case 1:
|
||||
if (playback) {
|
||||
ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
|
||||
|
||||
/* This is quite ugly, but apperently it's offical method for passing dma
|
||||
* config to the pcm module */
|
||||
if (playback) {
|
||||
jz4740_i2s_dma_playback_config.src_width = dma_width;
|
||||
i2s->pcm_config.dma_config = &jz4740_i2s_dma_playback_config;
|
||||
} else {
|
||||
jz4740_i2s_dma_capture_config.dst_width = dma_width;
|
||||
i2s->pcm_config.dma_config = &jz4740_i2s_dma_capture_config;
|
||||
}
|
||||
i2s->pcm_config.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
|
||||
|
||||
dai->dma_data = &i2s->pcm_config;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_i2s_set_clkdiv(struct snd_soc_dai *dai,
|
||||
int div_id, int div)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
|
||||
switch (div_id) {
|
||||
case JZ4740_I2S_BIT_CLK:
|
||||
if (div & 1 || div > 16)
|
||||
return -EINVAL;
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div - 1);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
|
||||
static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
|
||||
unsigned int freq, int dir)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
int ret = 0;
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
||||
jz4740_snd_rx_ctrl(1);
|
||||
else
|
||||
jz4740_snd_tx_ctrl(1);
|
||||
struct clk *parent;
|
||||
|
||||
switch (clk_id) {
|
||||
case JZ4740_I2S_CLKSRC_EXT:
|
||||
parent = clk_get(NULL, "ext");
|
||||
clk_set_parent(i2s->clk, parent);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
||||
jz4740_snd_rx_ctrl(0);
|
||||
else
|
||||
jz4740_snd_tx_ctrl(0);
|
||||
case JZ4740_I2S_CLKSRC_PLL:
|
||||
parent = clk_get(NULL, "pll half");
|
||||
clk_set_parent(i2s->clk, parent);
|
||||
ret = clk_set_rate(i2s->clk, freq);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
return -EINVAL;
|
||||
}
|
||||
clk_put(parent);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
|
||||
{
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
} else {
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
|
||||
{
|
||||
__i2s_internal_codec();
|
||||
__i2s_as_slave();
|
||||
__i2s_select_i2s();
|
||||
__aic_select_i2s();
|
||||
mdelay(2);
|
||||
|
||||
__i2s_disable();
|
||||
__i2s_reset();
|
||||
mdelay(2);
|
||||
|
||||
__i2s_disable();
|
||||
__i2s_internal_codec();
|
||||
__i2s_as_slave();
|
||||
__i2s_select_i2s();
|
||||
__aic_select_i2s();
|
||||
__i2s_set_oss_sample_size(16);
|
||||
__i2s_set_iss_sample_size(16);
|
||||
__aic_play_lastsample();
|
||||
|
||||
__i2s_disable_record();
|
||||
__i2s_disable_replay();
|
||||
__i2s_disable_loopback();
|
||||
__i2s_set_transmit_trigger(7);
|
||||
__i2s_set_receive_trigger(7);
|
||||
|
||||
jz4740_snd_tx_ctrl(0);
|
||||
jz4740_snd_rx_ctrl(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
uint32_t conf;
|
||||
|
||||
if (!dai->active)
|
||||
return 0;
|
||||
|
||||
conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
|
||||
conf &= ~JZ_AIC_CONF_ENABLE;
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
|
||||
|
||||
clk_disable(i2s->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_i2s_resume(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
uint32_t conf;
|
||||
|
||||
if (!dai->active)
|
||||
return 0;
|
||||
|
||||
clk_enable(i2s->clk);
|
||||
|
||||
conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
|
||||
conf |= JZ_AIC_CONF_ENABLE;
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
#define jz4740_i2s_suspend NULL
|
||||
#define jz4740_i2s_resume NULL
|
||||
#endif
|
||||
|
||||
#define JZ4740_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
|
||||
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
|
||||
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
|
||||
SNDRV_PCM_RATE_48000)
|
||||
static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
|
||||
{
|
||||
struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
|
||||
uint32_t conf;
|
||||
|
||||
struct snd_soc_dai_ops snd_jz4740_i2s_dai_ops = {
|
||||
conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
|
||||
(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
|
||||
JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
|
||||
JZ_AIC_CONF_I2S |
|
||||
JZ_AIC_CONF_INTERNAL_CODEC;
|
||||
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
|
||||
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
|
||||
.startup = jz4740_i2s_startup,
|
||||
.shutdown = jz4740_i2s_shutdown,
|
||||
.trigger = jz4740_i2s_trigger,
|
||||
.hw_params = jz4740_i2s_hw_params,
|
||||
.set_fmt = jz4740_i2s_set_dai_fmt,
|
||||
.set_sysclk = jz4740_i2s_set_dai_sysclk,
|
||||
.set_fmt = jz4740_i2s_set_fmt,
|
||||
.set_clkdiv = jz4740_i2s_set_clkdiv,
|
||||
.set_sysclk = jz4740_i2s_set_sysclk,
|
||||
};
|
||||
|
||||
#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
|
||||
SNDRV_PCM_FMTBIT_S16_LE)
|
||||
|
||||
struct snd_soc_dai jz4740_i2s_dai = {
|
||||
.name = "jz4740-i2s",
|
||||
.id = 0,
|
||||
.probe = jz4740_i2s_probe,
|
||||
.suspend = jz4740_i2s_suspend,
|
||||
.resume = jz4740_i2s_resume,
|
||||
.playback = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = JZ4740_I2S_RATES,
|
||||
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
|
||||
.rates = SNDRV_PCM_RATE_8000_44100,
|
||||
.formats = JZ4740_I2S_FMTS,
|
||||
},
|
||||
.capture = {
|
||||
.channels_min = 1,
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = JZ4740_I2S_RATES,
|
||||
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
|
||||
.rates = SNDRV_PCM_RATE_8000_44100,
|
||||
.formats = JZ4740_I2S_FMTS,
|
||||
},
|
||||
.ops = &snd_jz4740_i2s_dai_ops,
|
||||
.symmetric_rates = 1,
|
||||
.ops = &jz4740_i2s_dai_ops,
|
||||
.suspend = jz4740_i2s_suspend,
|
||||
.resume = jz4740_i2s_resume,
|
||||
};
|
||||
|
||||
EXPORT_SYMBOL_GPL(jz4740_i2s_dai);
|
||||
static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct jz4740_i2s *i2s;
|
||||
int ret;
|
||||
|
||||
i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
|
||||
|
||||
if (!i2s)
|
||||
return -ENOMEM;
|
||||
|
||||
i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
if (!i2s->mem) {
|
||||
ret = -ENOENT;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
|
||||
pdev->name);
|
||||
|
||||
if (!i2s->mem) {
|
||||
ret = -EBUSY;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
|
||||
|
||||
if (!i2s->base) {
|
||||
ret = -EBUSY;
|
||||
goto err_release_mem_region;
|
||||
}
|
||||
|
||||
i2s->phys_base = i2s->mem->start;
|
||||
|
||||
jz4740_i2s_dai.private_data = i2s;
|
||||
|
||||
ret = snd_soc_register_dai(&jz4740_i2s_dai);
|
||||
|
||||
i2s->clk = clk_get(&pdev->dev, "i2s");
|
||||
|
||||
if (IS_ERR(i2s->clk)) {
|
||||
ret = PTR_ERR(i2s->clk);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, i2s);
|
||||
|
||||
return 0;
|
||||
|
||||
err_iounmap:
|
||||
iounmap(i2s->base);
|
||||
err_release_mem_region:
|
||||
release_mem_region(i2s->mem->start, resource_size(i2s->mem));
|
||||
err_free:
|
||||
kfree(i2s);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct jz4740_i2s *i2s = platform_get_drvdata(pdev);
|
||||
|
||||
snd_soc_unregister_dai(&jz4740_i2s_dai);
|
||||
|
||||
clk_put(i2s->clk);
|
||||
|
||||
iounmap(i2s->base);
|
||||
release_mem_region(i2s->mem->start, resource_size(i2s->mem));
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
kfree(i2s);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver jz4740_i2s_driver = {
|
||||
.probe = jz4740_i2s_dev_probe,
|
||||
.remove = __devexit_p(jz4740_i2s_dev_remove),
|
||||
.driver = {
|
||||
.name = "jz4740-i2s",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init jz4740_i2s_init(void)
|
||||
{
|
||||
return snd_soc_register_dai(&jz4740_i2s_dai);
|
||||
return platform_driver_register(&jz4740_i2s_driver);
|
||||
}
|
||||
module_init(jz4740_i2s_init);
|
||||
|
||||
static void __exit jz4740_i2s_exit(void)
|
||||
{
|
||||
snd_soc_unregister_dai(&jz4740_i2s_dai);
|
||||
platform_driver_unregister(&jz4740_i2s_driver);
|
||||
}
|
||||
|
||||
module_init(jz4740_i2s_init);
|
||||
module_exit(jz4740_i2s_exit);
|
||||
|
||||
/* Module information */
|
||||
MODULE_AUTHOR("Richard, cjfeng@ingenic.cn, www.ingenic.cn");
|
||||
MODULE_DESCRIPTION("jz4740 I2S SoC Interface");
|
||||
MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
|
||||
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:jz4740-i2s");
|
||||
|
||||
@ -7,11 +7,11 @@
|
||||
#ifndef _JZ4740_I2S_H
|
||||
#define _JZ4740_I2S_H
|
||||
|
||||
/* jz4740 DAI ID's */
|
||||
#define JZ4740_DAI_I2S 0
|
||||
/* I2S clock source */
|
||||
#define JZ4740_I2S_CLKSRC_EXT 0
|
||||
#define JZ4740_I2S_CLKSRC_PLL 1
|
||||
|
||||
/* I2S clock */
|
||||
#define JZ4740_I2S_SYSCLK 0
|
||||
#define JZ4740_I2S_BIT_CLK 0
|
||||
|
||||
extern struct snd_soc_dai jz4740_i2s_dai;
|
||||
|
||||
|
||||
@ -24,7 +24,6 @@
|
||||
#include <sound/soc.h>
|
||||
|
||||
#include <asm/mach-jz4740/dma.h>
|
||||
#include <asm/mach-jz4740/regs.h>
|
||||
#include "jz4740-pcm.h"
|
||||
|
||||
struct jz4740_runtime_data {
|
||||
@ -32,25 +31,10 @@ struct jz4740_runtime_data {
|
||||
dma_addr_t dma_start;
|
||||
dma_addr_t dma_pos;
|
||||
dma_addr_t dma_end;
|
||||
|
||||
struct jz4740_dma_chan *dma;
|
||||
};
|
||||
|
||||
static struct jz4740_dma_config jz4740_pcm_dma_playback_config = {
|
||||
.src_width = JZ4740_DMA_WIDTH_16BIT,
|
||||
.dst_width = JZ4740_DMA_WIDTH_32BIT,
|
||||
.transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
|
||||
.request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT,
|
||||
.flags = JZ4740_DMA_SRC_AUTOINC,
|
||||
.mode = JZ4740_DMA_MODE_SINGLE,
|
||||
};
|
||||
|
||||
static struct jz4740_dma_config jz4740_pcm_dma_capture_config = {
|
||||
.src_width = JZ4740_DMA_WIDTH_32BIT,
|
||||
.dst_width = JZ4740_DMA_WIDTH_16BIT,
|
||||
.transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE,
|
||||
.request_type = JZ4740_DMA_TYPE_AIC_RECEIVE,
|
||||
.flags = JZ4740_DMA_DST_AUTOINC,
|
||||
.mode = JZ4740_DMA_MODE_SINGLE,
|
||||
dma_addr_t fifo_addr;
|
||||
};
|
||||
|
||||
/* identify hardware playback capabilities */
|
||||
@ -85,9 +69,9 @@ static void jz4740_pcm_start_transfer(struct jz4740_runtime_data *prtd, int stre
|
||||
|
||||
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
jz4740_dma_set_src_addr(prtd->dma, prtd->dma_pos);
|
||||
jz4740_dma_set_dst_addr(prtd->dma, CPHYSADDR(AIC_DR));
|
||||
jz4740_dma_set_dst_addr(prtd->dma, prtd->fifo_addr);
|
||||
} else {
|
||||
jz4740_dma_set_src_addr(prtd->dma, CPHYSADDR(AIC_DR));
|
||||
jz4740_dma_set_src_addr(prtd->dma, prtd->fifo_addr);
|
||||
jz4740_dma_set_dst_addr(prtd->dma, prtd->dma_pos);
|
||||
}
|
||||
|
||||
@ -117,53 +101,31 @@ static int jz4740_pcm_hw_params(struct snd_pcm_substream *substream,
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct jz4740_runtime_data *prtd = runtime->private_data;
|
||||
unsigned int size = params_buffer_bytes(params);
|
||||
struct jz4740_dma_config *dma_config;
|
||||
enum jz4740_dma_width width;
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S8:
|
||||
width = JZ4740_DMA_WIDTH_8BIT;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
width = JZ4740_DMA_WIDTH_16BIT;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct jz4740_pcm_config *config;
|
||||
|
||||
config = rtd->dai->cpu_dai->dma_data;
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
dma_config = &jz4740_pcm_dma_playback_config;
|
||||
dma_config->src_width = width;
|
||||
|
||||
prtd->dma = jz4740_dma_request(substream, "PCM Playback");
|
||||
} else {
|
||||
dma_config = &jz4740_pcm_dma_capture_config;
|
||||
dma_config->dst_width = width;
|
||||
|
||||
prtd->dma = jz4740_dma_request(substream, "PCM Capture");
|
||||
}
|
||||
|
||||
if (!prtd->dma)
|
||||
return -EBUSY;
|
||||
|
||||
jz4740_dma_configure(prtd->dma, dma_config);
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
jz4740_dma_set_dst_addr(prtd->dma, CPHYSADDR(AIC_DR));
|
||||
else
|
||||
jz4740_dma_set_src_addr(prtd->dma, CPHYSADDR(AIC_DR));
|
||||
jz4740_dma_configure(prtd->dma, config->dma_config);
|
||||
prtd->fifo_addr = config->fifo_addr;
|
||||
|
||||
jz4740_dma_set_complete_cb(prtd->dma, jz4740_pcm_dma_transfer_done);
|
||||
|
||||
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
|
||||
runtime->dma_bytes = size;
|
||||
runtime->dma_bytes = params_buffer_bytes(params);
|
||||
|
||||
prtd->dma_period = params_period_bytes(params);
|
||||
prtd->dma_start = runtime->dma_addr;
|
||||
prtd->dma_pos = prtd->dma_start;
|
||||
prtd->dma_end = prtd->dma_start + size;
|
||||
prtd->dma_end = prtd->dma_start + runtime->dma_bytes;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -271,7 +233,7 @@ static int jz4740_pcm_mmap(struct snd_pcm_substream *substream,
|
||||
vma->vm_end - vma->vm_start, vma->vm_page_prot);
|
||||
}
|
||||
|
||||
struct snd_pcm_ops jz4740_pcm_ops = {
|
||||
static const struct snd_pcm_ops jz4740_pcm_ops = {
|
||||
.open = jz4740_pcm_open,
|
||||
.close = jz4740_pcm_close,
|
||||
.ioctl = snd_pcm_lib_ioctl,
|
||||
@ -303,7 +265,7 @@ static int jz4740_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz4740_pcm_free_dma_buffers(struct snd_pcm *pcm)
|
||||
static void jz4740_pcm_free(struct snd_pcm *pcm)
|
||||
{
|
||||
struct snd_pcm_substream *substream;
|
||||
struct snd_dma_buffer *buf;
|
||||
@ -359,7 +321,7 @@ struct snd_soc_platform jz4740_soc_platform = {
|
||||
.name = "jz4740-pcm",
|
||||
.pcm_ops = &jz4740_pcm_ops,
|
||||
.pcm_new = jz4740_pcm_new,
|
||||
.pcm_free = jz4740_pcm_free_dma_buffers,
|
||||
.pcm_free = jz4740_pcm_free,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(jz4740_soc_platform);
|
||||
|
||||
|
||||
@ -8,7 +8,15 @@
|
||||
#ifndef _JZ4740_PCM_H
|
||||
#define _JZ4740_PCM_H
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/mach-jz4740/dma.h>
|
||||
|
||||
/* platform data */
|
||||
extern struct snd_soc_platform jz4740_soc_platform;
|
||||
|
||||
struct jz4740_pcm_config {
|
||||
struct jz4740_dma_config *dma_config;
|
||||
phys_addr_t fifo_addr;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user