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ramips: rt305x: add OHCI/EHCI registration code for RT3352

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31402 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
2012-04-21 12:30:48 +00:00
parent 3ff5d8da9a
commit e958af1110
2 changed files with 161 additions and 5 deletions
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34
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
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@@ -46,6 +46,11 @@
#define RT305X_FLASH1_SIZE (16 * 1024 * 1024)
#define RT305X_FLASH0_SIZE (8 * 1024 * 1024)
#define RT3352_EHCI_BASE 0x101c0000
#define RT3352_EHCI_SIZE 0x1000
#define RT3352_OHCI_BASE 0x101c1000
#define RT3352_OHCI_SIZE 0x1000
/* SYSC registers */
#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
@@ -57,6 +62,11 @@
#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
#define RT3352_SYSC_REG_SYSCFG1 0x014
#define RT3352_SYSC_REG_CLKCFG1 0x030
#define RT3352_SYSC_REG_RSTCTRL 0x034
#define RT3352_SYSC_REG_USB_PS 0x05c
#define RT3052_CHIP_NAME0 0x30335452
#define RT3052_CHIP_NAME1 0x20203235
@@ -85,6 +95,11 @@
#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
#define RT305X_GPIO_MODE_I2C BIT(0)
#define RT305X_GPIO_MODE_SPI BIT(1)
#define RT305X_GPIO_MODE_UART0_SHIFT 2
@@ -121,6 +136,25 @@
#define RT305X_RESET_OTG BIT(22)
#define RT305X_RESET_ESW BIT(23)
#define RT3352_RSTCTRL_SYS BIT(0)
#define RT3352_RSTCTRL_TIMER BIT(8)
#define RT3352_RSTCTRL_INTC BIT(9)
#define RT3352_RSTCTRL_MEMC BIT(10)
#define RT3352_RSTCTRL_PCM BIT(11)
#define RT3352_RSTCTRL_UART0 BIT(12)
#define RT3352_RSTCTRL_PIO BIT(13)
#define RT3352_RSTCTRL_DMA BIT(14)
#define RT3352_RSTCTRL_I2C BIT(16)
#define RT3352_RSTCTRL_I2S BIT(17)
#define RT3352_RSTCTRL_SPI BIT(18)
#define RT3352_RSTCTRL_UART1 BIT(19)
#define RT3352_RSTCTRL_WNIC BIT(20)
#define RT3352_RSTCTRL_FE BIT(21)
#define RT3352_RSTCTRL_UHST BIT(22)
#define RT3352_RSTCTRL_ESW BIT(23)
#define RT3352_RSTCTRL_EPHY BIT(24)
#define RT3352_RSTCTRL_UDEV BIT(25)
#define RT305X_INTC_INT_SYSCTL BIT(0)
#define RT305X_INTC_INT_TIMER0 BIT(1)
#define RT305X_INTC_INT_TIMER1 BIT(2)