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ar71xx: define NAND controller base address and register size for AR934X/QCA955x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33382 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -20,7 +20,7 @@
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#define AR71XX_PCI_MEM_BASE 0x10000000
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#define AR71XX_PCI_MEM_SIZE 0x07000000
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@@ -82,11 +88,15 @@
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@@ -82,17 +88,23 @@
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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@ -36,16 +36,26 @@
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_EHCI_BASE 0x1b000000
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@@ -112,6 +122,8 @@
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#define AR934X_EHCI_SIZE 0x200
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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+#define AR934X_NFC_BASE 0x1b000200
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+#define AR934X_NFC_SIZE 0xb8
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#define QCA955X_PCI_MEM_BASE0 0x10000000
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#define QCA955X_PCI_MEM_BASE1 0x12000000
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@@ -112,6 +124,10 @@
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#define QCA955X_EHCI0_BASE 0x1b000000
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#define QCA955X_EHCI1_BASE 0x1b400000
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#define QCA955X_EHCI_SIZE 0x200
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+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define QCA955X_GMAC_SIZE 0x40
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+#define QCA955X_NFC_BASE 0x1b000200
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+#define QCA955X_NFC_SIZE 0xb8
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/*
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* DDR_CTRL block
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@@ -167,6 +179,9 @@
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@@ -167,6 +183,9 @@
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#define AR71XX_AHB_DIV_SHIFT 20
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#define AR71XX_AHB_DIV_MASK 0x7
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@ -55,7 +65,7 @@
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#define AR724X_PLL_REG_CPU_CONFIG 0x00
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#define AR724X_PLL_REG_PCIE_CONFIG 0x18
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@@ -179,6 +194,8 @@
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@@ -179,6 +198,8 @@
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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@ -64,7 +74,7 @@
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#define AR913X_PLL_REG_CPU_CONFIG 0x00
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#define AR913X_PLL_REG_ETH_CONFIG 0x04
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#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
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@@ -191,6 +208,9 @@
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@@ -191,6 +212,9 @@
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#define AR913X_AHB_DIV_SHIFT 19
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#define AR913X_AHB_DIV_MASK 0x1
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@ -74,7 +84,7 @@
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#define AR933X_PLL_CPU_CONFIG_REG 0x00
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#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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@@ -212,6 +232,8 @@
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@@ -212,6 +236,8 @@
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#define AR934X_PLL_CPU_CONFIG_REG 0x00
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#define AR934X_PLL_DDR_CONFIG_REG 0x04
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
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@ -83,7 +93,7 @@
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#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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@@ -244,6 +266,8 @@
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@@ -244,6 +270,8 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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@ -92,7 +102,7 @@
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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@@ -370,16 +394,50 @@
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@@ -370,16 +398,50 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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@ -143,7 +153,7 @@
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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@@ -520,6 +578,14 @@
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@@ -520,6 +582,14 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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@ -158,7 +168,7 @@
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#define AR71XX_GPIO_COUNT 16
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#define AR724X_GPIO_COUNT 18
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#define AR913X_GPIO_COUNT 22
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@@ -548,4 +614,133 @@
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@@ -548,4 +618,133 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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@ -149,9 +149,9 @@
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#endif /* _ATH79_DEV_WMAC_H */
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -125,6 +125,14 @@
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#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define QCA955X_GMAC_SIZE 0x40
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@@ -129,6 +129,14 @@
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#define QCA955X_NFC_BASE 0x1b000200
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#define QCA955X_NFC_SIZE 0xb8
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+#define AR9300_OTP_BASE 0x14000
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+#define AR9300_OTP_STATUS 0x15f18
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