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mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2025-04-21 12:27:27 +03:00

[generic-2.4] add OCF 20100325 support to brcm-2.4

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21357 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
jow
2010-05-04 21:00:14 +00:00
parent 40b344028b
commit ea6674d9de
186 changed files with 86782 additions and 2 deletions

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# for SGlinux builds
-include $(ROOTDIR)/modules/.config
obj-$(CONFIG_OCF_SAFE) += safe.o
obj ?= .
EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/
ifdef TOPDIR
-include $(TOPDIR)/Rules.make
endif

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/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */
/*
* Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the project nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#if 0
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $");
#include <sys/types.h>
#include <sys/cdefs.h>
#include <sys/time.h>
#include <sys/systm.h>
#include <crypto/md5.h>
#endif
#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s))))
#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z)))
#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z)))
#define H(X, Y, Z) ((X) ^ (Y) ^ (Z))
#define I(X, Y, Z) ((Y) ^ ((X) | (~Z)))
#define ROUND1(a, b, c, d, k, s, i) { \
(a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \
(a) = SHIFT((a), (s)); \
(a) = (b) + (a); \
}
#define ROUND2(a, b, c, d, k, s, i) { \
(a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \
(a) = SHIFT((a), (s)); \
(a) = (b) + (a); \
}
#define ROUND3(a, b, c, d, k, s, i) { \
(a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \
(a) = SHIFT((a), (s)); \
(a) = (b) + (a); \
}
#define ROUND4(a, b, c, d, k, s, i) { \
(a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \
(a) = SHIFT((a), (s)); \
(a) = (b) + (a); \
}
#define Sa 7
#define Sb 12
#define Sc 17
#define Sd 22
#define Se 5
#define Sf 9
#define Sg 14
#define Sh 20
#define Si 4
#define Sj 11
#define Sk 16
#define Sl 23
#define Sm 6
#define Sn 10
#define So 15
#define Sp 21
#define MD5_A0 0x67452301
#define MD5_B0 0xefcdab89
#define MD5_C0 0x98badcfe
#define MD5_D0 0x10325476
/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */
static const u_int32_t T[65] = {
0,
0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee,
0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501,
0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be,
0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821,
0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa,
0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8,
0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed,
0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a,
0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c,
0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70,
0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05,
0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665,
0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039,
0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1,
0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1,
0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391,
};
static const u_int8_t md5_paddat[MD5_BUFLEN] = {
0x80, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
};
static void md5_calc(u_int8_t *, md5_ctxt *);
void md5_init(ctxt)
md5_ctxt *ctxt;
{
ctxt->md5_n = 0;
ctxt->md5_i = 0;
ctxt->md5_sta = MD5_A0;
ctxt->md5_stb = MD5_B0;
ctxt->md5_stc = MD5_C0;
ctxt->md5_std = MD5_D0;
bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf));
}
void md5_loop(ctxt, input, len)
md5_ctxt *ctxt;
u_int8_t *input;
u_int len; /* number of bytes */
{
u_int gap, i;
ctxt->md5_n += len * 8; /* byte to bit */
gap = MD5_BUFLEN - ctxt->md5_i;
if (len >= gap) {
bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i),
gap);
md5_calc(ctxt->md5_buf, ctxt);
for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) {
md5_calc((u_int8_t *)(input + i), ctxt);
}
ctxt->md5_i = len - i;
bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i);
} else {
bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i),
len);
ctxt->md5_i += len;
}
}
void md5_pad(ctxt)
md5_ctxt *ctxt;
{
u_int gap;
/* Don't count up padding. Keep md5_n. */
gap = MD5_BUFLEN - ctxt->md5_i;
if (gap > 8) {
bcopy(md5_paddat,
(void *)(ctxt->md5_buf + ctxt->md5_i),
gap - sizeof(ctxt->md5_n));
} else {
/* including gap == 8 */
bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i),
gap);
md5_calc(ctxt->md5_buf, ctxt);
bcopy((md5_paddat + gap),
(void *)ctxt->md5_buf,
MD5_BUFLEN - sizeof(ctxt->md5_n));
}
/* 8 byte word */
#if BYTE_ORDER == LITTLE_ENDIAN
bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8);
#endif
#if BYTE_ORDER == BIG_ENDIAN
ctxt->md5_buf[56] = ctxt->md5_n8[7];
ctxt->md5_buf[57] = ctxt->md5_n8[6];
ctxt->md5_buf[58] = ctxt->md5_n8[5];
ctxt->md5_buf[59] = ctxt->md5_n8[4];
ctxt->md5_buf[60] = ctxt->md5_n8[3];
ctxt->md5_buf[61] = ctxt->md5_n8[2];
ctxt->md5_buf[62] = ctxt->md5_n8[1];
ctxt->md5_buf[63] = ctxt->md5_n8[0];
#endif
md5_calc(ctxt->md5_buf, ctxt);
}
void md5_result(digest, ctxt)
u_int8_t *digest;
md5_ctxt *ctxt;
{
/* 4 byte words */
#if BYTE_ORDER == LITTLE_ENDIAN
bcopy(&ctxt->md5_st8[0], digest, 16);
#endif
#if BYTE_ORDER == BIG_ENDIAN
digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2];
digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0];
digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6];
digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4];
digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10];
digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8];
digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14];
digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12];
#endif
}
static void md5_calc(b64, ctxt)
u_int8_t *b64;
md5_ctxt *ctxt;
{
u_int32_t A = ctxt->md5_sta;
u_int32_t B = ctxt->md5_stb;
u_int32_t C = ctxt->md5_stc;
u_int32_t D = ctxt->md5_std;
#if BYTE_ORDER == LITTLE_ENDIAN
u_int32_t *X = (u_int32_t *)b64;
#endif
#if BYTE_ORDER == BIG_ENDIAN
/* 4 byte words */
/* what a brute force but fast! */
u_int32_t X[16];
u_int8_t *y = (u_int8_t *)X;
y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0];
y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4];
y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8];
y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12];
y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16];
y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20];
y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24];
y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28];
y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32];
y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36];
y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40];
y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44];
y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48];
y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52];
y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56];
y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60];
#endif
ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2);
ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4);
ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6);
ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8);
ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10);
ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12);
ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14);
ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16);
ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18);
ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20);
ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22);
ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24);
ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26);
ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28);
ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30);
ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32);
ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34);
ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36);
ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38);
ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40);
ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42);
ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44);
ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46);
ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48);
ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50);
ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52);
ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54);
ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56);
ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58);
ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60);
ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62);
ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64);
ctxt->md5_sta += A;
ctxt->md5_stb += B;
ctxt->md5_stc += C;
ctxt->md5_std += D;
}

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/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */
/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */
/*
* Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the project nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _NETINET6_MD5_H_
#define _NETINET6_MD5_H_
#define MD5_BUFLEN 64
typedef struct {
union {
u_int32_t md5_state32[4];
u_int8_t md5_state8[16];
} md5_st;
#define md5_sta md5_st.md5_state32[0]
#define md5_stb md5_st.md5_state32[1]
#define md5_stc md5_st.md5_state32[2]
#define md5_std md5_st.md5_state32[3]
#define md5_st8 md5_st.md5_state8
union {
u_int64_t md5_count64;
u_int8_t md5_count8[8];
} md5_count;
#define md5_n md5_count.md5_count64
#define md5_n8 md5_count.md5_count8
u_int md5_i;
u_int8_t md5_buf[MD5_BUFLEN];
} md5_ctxt;
extern void md5_init(md5_ctxt *);
extern void md5_loop(md5_ctxt *, u_int8_t *, u_int);
extern void md5_pad(md5_ctxt *);
extern void md5_result(u_int8_t *, md5_ctxt *);
/* compatibility */
#define MD5_CTX md5_ctxt
#define MD5Init(x) md5_init((x))
#define MD5Update(x, y, z) md5_loop((x), (y), (z))
#define MD5Final(x, y) \
do { \
md5_pad((y)); \
md5_result((x), (y)); \
} while (0)
#endif /* ! _NETINET6_MD5_H_*/

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/*-
* Copyright (c) 2003 Sam Leffler, Errno Consulting
* Copyright (c) 2003 Global Technology Associates, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $
*/
#ifndef _SAFE_SAFEREG_H_
#define _SAFE_SAFEREG_H_
/*
* Register definitions for SafeNet SafeXcel-1141 crypto device.
* Definitions from revision 1.3 (Nov 6 2002) of the User's Manual.
*/
#define BS_BAR 0x10 /* DMA base address register */
#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */
/* SafeNet */
#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */
#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */
#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
#define SAFE_PE_SA 0x000c /* Packet Engine SA */
#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */
#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */
#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */
#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */
#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */
#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */
#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */
#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */
#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */
#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */
#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */
#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */
#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */
#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */
#define SAFE_DEVID 0x0084 /* Device ID */
#define SAFE_DEVINFO 0x0088 /* Device Info */
#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */
#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */
#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */
#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */
#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */
#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */
#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */
#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */
#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */
#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */
#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */
#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */
#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */
#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */
#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */
#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */
#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */
#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */
#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */
#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */
#define SAFE_PK_FUNC 0x081c /* Public Key Function */
#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */
#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */
#define SAFE_RNG_OUT 0x0100 /* RNG Output */
#define SAFE_RNG_STAT 0x0104 /* RNG Status */
#define SAFE_RNG_CTRL 0x0108 /* RNG Control */
#define SAFE_RNG_A 0x010c /* RNG A */
#define SAFE_RNG_B 0x0110 /* RNG B */
#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */
#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */
#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */
#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */
#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */
#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */
#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */
#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */
#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */
#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */
#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */
#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */
#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */
#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */
#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */
#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */
#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */
#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */
#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */
#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */
#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */
#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */
#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */
#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */
#define SAFE_PE_CSR_XECODE_S 20
#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */
#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */
#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */
#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */
#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */
#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */
#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */
#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */
#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */
#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */
#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */
#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */
#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */
#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */
#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */
/*
* Check the CSR to see if the PE has returned ownership to
* the host. Note that before processing a descriptor this
* must be done followed by a check of the SAFE_PE_LEN register
* status bits to avoid premature processing of a descriptor
* on its way back to the host.
*/
#define SAFE_PE_CSR_IS_DONE(_csr) \
(((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE)
#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */
#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */
#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */
#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */
#define SAFE_PE_LEN_BYPASS_S 24
#define SAFE_PE_LEN_IS_DONE(_len) \
(((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE)
/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */
#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */
#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */
#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */
#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */
#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */
#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */
#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */
#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */
#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */
#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */
#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */
#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */
#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */
#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */
#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */
#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */
#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */
#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */
#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */
#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */
#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */
#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */
#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */
#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */
#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */
#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */
#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */
#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */
#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */
#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */
#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */
#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */
#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */
#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */
#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */
#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */
#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */
#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */
#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */
#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */
#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */
#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */
#define SAFE_PE_RINGCFG_OFFSET_S 16
#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */
#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */
#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */
#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */
#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */
#define SAFE_PE_ERNGSTAT_NEXT_S 16
#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */
#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */
#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */
#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */
#define SAFE_PE_PARTCFG_GBURST_2 0x00000000
#define SAFE_PE_PARTCFG_GBURST_4 0x00010000
#define SAFE_PE_PARTCFG_GBURST_8 0x00020000
#define SAFE_PE_PARTCFG_GBURST_16 0x00030000
#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */
#define SAFE_PE_PARTCFG_SBURST_2 0x00000000
#define SAFE_PE_PARTCFG_SBURST_4 0x00040000
#define SAFE_PE_PARTCFG_SBURST_8 0x00080000
#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000
#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */
#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */
#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */
#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */
#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */
#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */
#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */
#define SAFE_DEVINFO_REV_MAJ_S 4
#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */
#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */
#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */
#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */
#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */
#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */
#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */
#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */
#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */
#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */
#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */
#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min))
#define SAFE_REV_MAJ(_chiprev) \
(((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S)
#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN)
#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */
#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */
#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */
#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */
#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */
#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */
#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */
#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */
#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */
#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */
#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */
#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */
#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */
#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */
#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */
#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */
#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */
#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */
#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */
#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */
#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */
#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */
#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */
/*
* Packet engine descriptor. Note that d_csr is a copy of the
* SAFE_PE_CSR register and all definitions apply, and d_len
* is a copy of the SAFE_PE_LEN register and all definitions apply.
* d_src and d_len may point directly to contiguous data or to a
* list of ``particle descriptors'' when using scatter/gather i/o.
*/
struct safe_desc {
u_int32_t d_csr; /* per-packet control/status */
u_int32_t d_src; /* source address */
u_int32_t d_dst; /* destination address */
u_int32_t d_sa; /* SA address */
u_int32_t d_len; /* length, bypass, status */
};
/*
* Scatter/Gather particle descriptor.
*
* NB: scatter descriptors do not specify a size; this is fixed
* by the setting of the SAFE_PE_PARTCFG register.
*/
struct safe_pdesc {
u_int32_t pd_addr; /* particle address */
#ifdef __BIG_ENDIAN
u_int16_t pd_flags; /* control word */
u_int16_t pd_size; /* particle size (bytes) */
#else
u_int16_t pd_flags; /* control word */
u_int16_t pd_size; /* particle size (bytes) */
#endif
};
#define SAFE_PD_READY 0x0001 /* ready for processing */
#define SAFE_PD_DONE 0x0002 /* h/w completed processing */
/*
* Security Association (SA) Record (Rev 1). One of these is
* required for each operation processed by the packet engine.
*/
struct safe_sarec {
u_int32_t sa_cmd0;
u_int32_t sa_cmd1;
u_int32_t sa_resv0;
u_int32_t sa_resv1;
u_int32_t sa_key[8]; /* DES/3DES/AES key */
u_int32_t sa_indigest[5]; /* inner digest */
u_int32_t sa_outdigest[5]; /* outer digest */
u_int32_t sa_spi; /* SPI */
u_int32_t sa_seqnum; /* sequence number */
u_int32_t sa_seqmask[2]; /* sequence number mask */
u_int32_t sa_resv2;
u_int32_t sa_staterec; /* address of state record */
u_int32_t sa_resv3[2];
u_int32_t sa_samgmt0; /* SA management field 0 */
u_int32_t sa_samgmt1; /* SA management field 0 */
};
#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */
#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */
#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */
#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */
#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */
#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */
#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */
#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */
#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */
#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */
#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */
#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */
#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */
#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */
#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */
#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */
#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */
#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */
#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */
#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */
#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */
#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */
#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */
#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */
#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */
#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */
#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */
#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */
#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */
#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */
#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */
#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */
#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */
#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */
#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */
#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */
#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */
#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */
#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */
#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */
#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */
#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */
#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */
#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */
#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */
#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */
#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */
#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */
#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */
#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */
#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */
#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */
#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */
#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */
#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */
#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */
#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */
#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */
#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */
#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */
#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */
#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */
#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS
#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */
#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */
#define SAFE_SA_CMD1_OFFSET_S 16
#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */
#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */
#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */
#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */
/*
* Security Associate State Record (Rev 1).
*/
struct safe_sastate {
u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */
u_int32_t sa_saved_hashbc; /* saved hash byte count */
u_int32_t sa_saved_indigest[5]; /* saved inner digest */
};
#endif /* _SAFE_SAFEREG_H_ */

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@@ -0,0 +1,230 @@
/*-
* The linux port of this code done by David McCullough
* Copyright (C) 2004-2010 David McCullough <david_mccullough@mcafee.com>
* The license and original author are listed below.
*
* Copyright (c) 2003 Sam Leffler, Errno Consulting
* Copyright (c) 2003 Global Technology Associates, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $
*/
#ifndef _SAFE_SAFEVAR_H_
#define _SAFE_SAFEVAR_H_
/* Maximum queue length */
#ifndef SAFE_MAX_NQUEUE
#define SAFE_MAX_NQUEUE 60
#endif
#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */
#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */
#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */
#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */
#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */
/* total src+dst particle descriptors */
#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART)
#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART)
#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */
#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28)
#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff)
#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff))
#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */
#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */
#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */
#ifdef __KERNEL__
/*
* State associated with the allocation of each chunk
* of memory setup for DMA.
*/
struct safe_dma_alloc {
dma_addr_t dma_paddr;
void *dma_vaddr;
};
/*
* Cryptographic operand state. One of these exists for each
* source and destination operand passed in from the crypto
* subsystem. When possible source and destination operands
* refer to the same memory. More often they are distinct.
* We track the virtual address of each operand as well as
* where each is mapped for DMA.
*/
struct safe_operand {
union {
struct sk_buff *skb;
struct uio *io;
} u;
void *map;
int mapsize; /* total number of bytes in segs */
struct {
dma_addr_t ds_addr;
int ds_len;
int ds_tlen;
} segs[SAFE_MAX_PART];
int nsegs;
};
/*
* Packet engine ring entry and cryptographic operation state.
* The packet engine requires a ring of descriptors that contain
* pointers to various cryptographic state. However the ring
* configuration register allows you to specify an arbitrary size
* for ring entries. We use this feature to collect most of the
* state for each cryptographic request into one spot. Other than
* ring entries only the ``particle descriptors'' (scatter/gather
* lists) and the actual operand data are kept separate. The
* particle descriptors must also be organized in rings. The
* operand data can be located aribtrarily (modulo alignment constraints).
*
* Note that the descriptor ring is mapped onto the PCI bus so
* the hardware can DMA data. This means the entire ring must be
* contiguous.
*/
struct safe_ringentry {
struct safe_desc re_desc; /* command descriptor */
struct safe_sarec re_sa; /* SA record */
struct safe_sastate re_sastate; /* SA state record */
struct cryptop *re_crp; /* crypto operation */
struct safe_operand re_src; /* source operand */
struct safe_operand re_dst; /* destination operand */
int re_sesn; /* crypto session ID */
int re_flags;
#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */
#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */
};
#define re_src_skb re_src.u.skb
#define re_src_io re_src.u.io
#define re_src_map re_src.map
#define re_src_nsegs re_src.nsegs
#define re_src_segs re_src.segs
#define re_src_mapsize re_src.mapsize
#define re_dst_skb re_dst.u.skb
#define re_dst_io re_dst.u.io
#define re_dst_map re_dst.map
#define re_dst_nsegs re_dst.nsegs
#define re_dst_segs re_dst.segs
#define re_dst_mapsize re_dst.mapsize
struct rndstate_test;
struct safe_session {
u_int32_t ses_used;
u_int32_t ses_klen; /* key length in bits */
u_int32_t ses_key[8]; /* DES/3DES/AES key */
u_int32_t ses_mlen; /* hmac length in bytes */
u_int32_t ses_hminner[5]; /* hmac inner state */
u_int32_t ses_hmouter[5]; /* hmac outer state */
u_int32_t ses_iv[4]; /* DES/3DES/AES iv */
};
struct safe_pkq {
struct list_head pkq_list;
struct cryptkop *pkq_krp;
};
struct safe_softc {
softc_device_decl sc_dev;
u32 sc_irq;
struct pci_dev *sc_pcidev;
ocf_iomem_t sc_base_addr;
u_int sc_chiprev; /* major/minor chip revision */
int sc_flags; /* device specific flags */
#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */
#define SAFE_FLAGS_RNG 0x02 /* hardware rng */
int sc_suspended;
int sc_needwakeup; /* notify crypto layer */
int32_t sc_cid; /* crypto tag */
struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */
struct safe_ringentry *sc_ring; /* PE ring */
struct safe_ringentry *sc_ringtop; /* PE ring top */
struct safe_ringentry *sc_front; /* next free entry */
struct safe_ringentry *sc_back; /* next pending entry */
int sc_nqchip; /* # passed to chip */
spinlock_t sc_ringmtx; /* PE ring lock */
struct safe_pdesc *sc_spring; /* src particle ring */
struct safe_pdesc *sc_springtop; /* src particle ring top */
struct safe_pdesc *sc_spfree; /* next free src particle */
struct safe_dma_alloc sc_spalloc; /* src particle ring state */
struct safe_pdesc *sc_dpring; /* dest particle ring */
struct safe_pdesc *sc_dpringtop; /* dest particle ring top */
struct safe_pdesc *sc_dpfree; /* next free dest particle */
struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */
int sc_nsessions; /* # of sessions */
struct safe_session *sc_sessions; /* sessions */
struct timer_list sc_pkto; /* PK polling */
spinlock_t sc_pkmtx; /* PK lock */
struct list_head sc_pkq; /* queue of PK requests */
struct safe_pkq *sc_pkq_cur; /* current processing request */
u_int32_t sc_pk_reslen, sc_pk_resoff;
int sc_max_dsize; /* maximum safe DMA size */
};
#endif /* __KERNEL__ */
struct safe_stats {
u_int64_t st_ibytes;
u_int64_t st_obytes;
u_int32_t st_ipackets;
u_int32_t st_opackets;
u_int32_t st_invalid; /* invalid argument */
u_int32_t st_badsession; /* invalid session id */
u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */
u_int32_t st_nodesc; /* op submitted w/o descriptors */
u_int32_t st_badalg; /* unsupported algorithm */
u_int32_t st_ringfull; /* PE descriptor ring full */
u_int32_t st_peoperr; /* PE marked error */
u_int32_t st_dmaerr; /* PE DMA error */
u_int32_t st_bypasstoobig; /* bypass > 96 bytes */
u_int32_t st_skipmismatch; /* enc part begins before auth part */
u_int32_t st_lenmismatch; /* enc length different auth length */
u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */
u_int32_t st_cofftoobig; /* crypto offset > 255 words */
u_int32_t st_iovmisaligned; /* iov op not aligned */
u_int32_t st_iovnotuniform; /* iov op not suitable */
u_int32_t st_unaligned; /* unaligned src caused copy */
u_int32_t st_notuniform; /* non-uniform src caused copy */
u_int32_t st_nomap; /* bus_dmamap_create failed */
u_int32_t st_noload; /* bus_dmamap_load_* failed */
u_int32_t st_nombuf; /* MGET* failed */
u_int32_t st_nomcl; /* MCLGET* failed */
u_int32_t st_maxqchip; /* max mcr1 ops out for processing */
u_int32_t st_rng; /* RNG requests */
u_int32_t st_rngalarm; /* RNG alarm requests */
u_int32_t st_noicvcopy; /* ICV data copies suppressed */
};
#endif /* _SAFE_SAFEVAR_H_ */

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@@ -0,0 +1,279 @@
/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */
/*
* Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the project nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* FIPS pub 180-1: Secure Hash Algorithm (SHA-1)
* based on: http://csrc.nist.gov/fips/fip180-1.txt
* implemented by Jun-ichiro itojun Itoh <itojun@itojun.org>
*/
#if 0
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $");
#include <sys/types.h>
#include <sys/cdefs.h>
#include <sys/time.h>
#include <sys/systm.h>
#include <crypto/sha1.h>
#endif
/* sanity check */
#if BYTE_ORDER != BIG_ENDIAN
# if BYTE_ORDER != LITTLE_ENDIAN
# define unsupported 1
# endif
#endif
#ifndef unsupported
/* constant table */
static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 };
#define K(t) _K[(t) / 20]
#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d)))
#define F1(b, c, d) (((b) ^ (c)) ^ (d))
#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d)))
#define F3(b, c, d) (((b) ^ (c)) ^ (d))
#define S(n, x) (((x) << (n)) | ((x) >> (32 - n)))
#undef H
#define H(n) (ctxt->h.b32[(n)])
#define COUNT (ctxt->count)
#define BCOUNT (ctxt->c.b64[0] / 8)
#define W(n) (ctxt->m.b32[(n)])
#define PUTBYTE(x) { \
ctxt->m.b8[(COUNT % 64)] = (x); \
COUNT++; \
COUNT %= 64; \
ctxt->c.b64[0] += 8; \
if (COUNT % 64 == 0) \
sha1_step(ctxt); \
}
#define PUTPAD(x) { \
ctxt->m.b8[(COUNT % 64)] = (x); \
COUNT++; \
COUNT %= 64; \
if (COUNT % 64 == 0) \
sha1_step(ctxt); \
}
static void sha1_step(struct sha1_ctxt *);
static void
sha1_step(ctxt)
struct sha1_ctxt *ctxt;
{
u_int32_t a, b, c, d, e;
size_t t, s;
u_int32_t tmp;
#if BYTE_ORDER == LITTLE_ENDIAN
struct sha1_ctxt tctxt;
bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64);
ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2];
ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0];
ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6];
ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4];
ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10];
ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8];
ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14];
ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12];
ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18];
ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16];
ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22];
ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20];
ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26];
ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24];
ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30];
ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28];
ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34];
ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32];
ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38];
ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36];
ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42];
ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40];
ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46];
ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44];
ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50];
ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48];
ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54];
ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52];
ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58];
ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56];
ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62];
ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60];
#endif
a = H(0); b = H(1); c = H(2); d = H(3); e = H(4);
for (t = 0; t < 20; t++) {
s = t & 0x0f;
if (t >= 16) {
W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s));
}
tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t);
e = d; d = c; c = S(30, b); b = a; a = tmp;
}
for (t = 20; t < 40; t++) {
s = t & 0x0f;
W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s));
tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t);
e = d; d = c; c = S(30, b); b = a; a = tmp;
}
for (t = 40; t < 60; t++) {
s = t & 0x0f;
W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s));
tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t);
e = d; d = c; c = S(30, b); b = a; a = tmp;
}
for (t = 60; t < 80; t++) {
s = t & 0x0f;
W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s));
tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t);
e = d; d = c; c = S(30, b); b = a; a = tmp;
}
H(0) = H(0) + a;
H(1) = H(1) + b;
H(2) = H(2) + c;
H(3) = H(3) + d;
H(4) = H(4) + e;
bzero(&ctxt->m.b8[0], 64);
}
/*------------------------------------------------------------*/
void
sha1_init(ctxt)
struct sha1_ctxt *ctxt;
{
bzero(ctxt, sizeof(struct sha1_ctxt));
H(0) = 0x67452301;
H(1) = 0xefcdab89;
H(2) = 0x98badcfe;
H(3) = 0x10325476;
H(4) = 0xc3d2e1f0;
}
void
sha1_pad(ctxt)
struct sha1_ctxt *ctxt;
{
size_t padlen; /*pad length in bytes*/
size_t padstart;
PUTPAD(0x80);
padstart = COUNT % 64;
padlen = 64 - padstart;
if (padlen < 8) {
bzero(&ctxt->m.b8[padstart], padlen);
COUNT += padlen;
COUNT %= 64;
sha1_step(ctxt);
padstart = COUNT % 64; /* should be 0 */
padlen = 64 - padstart; /* should be 64 */
}
bzero(&ctxt->m.b8[padstart], padlen - 8);
COUNT += (padlen - 8);
COUNT %= 64;
#if BYTE_ORDER == BIG_ENDIAN
PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]);
PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]);
PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]);
PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]);
#else
PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]);
PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]);
PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]);
PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]);
#endif
}
void
sha1_loop(ctxt, input, len)
struct sha1_ctxt *ctxt;
const u_int8_t *input;
size_t len;
{
size_t gaplen;
size_t gapstart;
size_t off;
size_t copysiz;
off = 0;
while (off < len) {
gapstart = COUNT % 64;
gaplen = 64 - gapstart;
copysiz = (gaplen < len - off) ? gaplen : len - off;
bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz);
COUNT += copysiz;
COUNT %= 64;
ctxt->c.b64[0] += copysiz * 8;
if (COUNT % 64 == 0)
sha1_step(ctxt);
off += copysiz;
}
}
void
sha1_result(ctxt, digest0)
struct sha1_ctxt *ctxt;
caddr_t digest0;
{
u_int8_t *digest;
digest = (u_int8_t *)digest0;
sha1_pad(ctxt);
#if BYTE_ORDER == BIG_ENDIAN
bcopy(&ctxt->h.b8[0], digest, 20);
#else
digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2];
digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0];
digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6];
digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4];
digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10];
digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8];
digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14];
digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12];
digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18];
digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16];
#endif
}
#endif /*unsupported*/

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@@ -0,0 +1,72 @@
/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */
/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */
/*
* Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the project nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* FIPS pub 180-1: Secure Hash Algorithm (SHA-1)
* based on: http://csrc.nist.gov/fips/fip180-1.txt
* implemented by Jun-ichiro itojun Itoh <itojun@itojun.org>
*/
#ifndef _NETINET6_SHA1_H_
#define _NETINET6_SHA1_H_
struct sha1_ctxt {
union {
u_int8_t b8[20];
u_int32_t b32[5];
} h;
union {
u_int8_t b8[8];
u_int64_t b64[1];
} c;
union {
u_int8_t b8[64];
u_int32_t b32[16];
} m;
u_int8_t count;
};
#ifdef __KERNEL__
extern void sha1_init(struct sha1_ctxt *);
extern void sha1_pad(struct sha1_ctxt *);
extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t);
extern void sha1_result(struct sha1_ctxt *, caddr_t);
/* compatibilty with other SHA1 source codes */
typedef struct sha1_ctxt SHA1_CTX;
#define SHA1Init(x) sha1_init((x))
#define SHA1Update(x, y, z) sha1_loop((x), (y), (z))
#define SHA1Final(x, y) sha1_result((y), (x))
#endif /* __KERNEL__ */
#define SHA1_RESULTLEN (160/8)
#endif /*_NETINET6_SHA1_H_*/