mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-27 21:44:04 +02:00
nuke old 2.6.23 code for brcm47xx
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13910 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
parent
3b617e51cc
commit
ee47517d9a
@ -1,246 +0,0 @@
|
|||||||
CONFIG_32BIT=y
|
|
||||||
# CONFIG_64BIT is not set
|
|
||||||
# CONFIG_8139TOO is not set
|
|
||||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
|
||||||
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
|
|
||||||
# CONFIG_ARCH_SUPPORTS_MSI is not set
|
|
||||||
# CONFIG_ARPD is not set
|
|
||||||
# CONFIG_ATMEL is not set
|
|
||||||
CONFIG_B44=y
|
|
||||||
CONFIG_BASE_SMALL=0
|
|
||||||
# CONFIG_BCM43XX is not set
|
|
||||||
CONFIG_BCM947XX=y
|
|
||||||
CONFIG_BITREVERSE=y
|
|
||||||
# CONFIG_BONDING is not set
|
|
||||||
# CONFIG_BSD_DISKLABEL is not set
|
|
||||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
|
||||||
# CONFIG_BT_HCIBCM203X is not set
|
|
||||||
# CONFIG_BT_HCIBFUSB is not set
|
|
||||||
# CONFIG_BT_HCIBPA10X is not set
|
|
||||||
# CONFIG_BT_HCIVHCI is not set
|
|
||||||
CONFIG_CFE=y
|
|
||||||
# CONFIG_CIFS_STATS is not set
|
|
||||||
# CONFIG_CLS_U32_MARK is not set
|
|
||||||
# CONFIG_CLS_U32_PERF is not set
|
|
||||||
CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 init=/etc/preinit noinitrd console=ttyS0,115200"
|
|
||||||
# CONFIG_CONFIGFS_FS is not set
|
|
||||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
|
||||||
CONFIG_CPU_HAS_LLSC=y
|
|
||||||
CONFIG_CPU_HAS_PREFETCH=y
|
|
||||||
CONFIG_CPU_HAS_SYNC=y
|
|
||||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
|
||||||
# CONFIG_CPU_LOONGSON2 is not set
|
|
||||||
CONFIG_CPU_MIPS32=y
|
|
||||||
CONFIG_CPU_MIPS32_R1=y
|
|
||||||
# CONFIG_CPU_MIPS32_R2 is not set
|
|
||||||
# CONFIG_CPU_MIPS64_R1 is not set
|
|
||||||
# CONFIG_CPU_MIPS64_R2 is not set
|
|
||||||
CONFIG_CPU_MIPSR1=y
|
|
||||||
# CONFIG_CPU_NEVADA is not set
|
|
||||||
# CONFIG_CPU_R10000 is not set
|
|
||||||
# CONFIG_CPU_R3000 is not set
|
|
||||||
# CONFIG_CPU_R4300 is not set
|
|
||||||
# CONFIG_CPU_R4X00 is not set
|
|
||||||
# CONFIG_CPU_R5000 is not set
|
|
||||||
# CONFIG_CPU_R5432 is not set
|
|
||||||
# CONFIG_CPU_R6000 is not set
|
|
||||||
# CONFIG_CPU_R8000 is not set
|
|
||||||
# CONFIG_CPU_RM7000 is not set
|
|
||||||
# CONFIG_CPU_RM9000 is not set
|
|
||||||
# CONFIG_CPU_SB1 is not set
|
|
||||||
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
|
||||||
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
|
||||||
# CONFIG_CPU_TX39XX is not set
|
|
||||||
# CONFIG_CPU_TX49XX is not set
|
|
||||||
# CONFIG_CPU_VR41XX is not set
|
|
||||||
CONFIG_DEVPORT=y
|
|
||||||
# CONFIG_DM9000 is not set
|
|
||||||
CONFIG_DMA_NEED_PCI_MAP_STATE=y
|
|
||||||
CONFIG_DMA_NONCOHERENT=y
|
|
||||||
# CONFIG_E100 is not set
|
|
||||||
CONFIG_FS_POSIX_ACL=y
|
|
||||||
CONFIG_GENERIC_FIND_NEXT_BIT=y
|
|
||||||
CONFIG_GENERIC_GPIO=y
|
|
||||||
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
|
|
||||||
CONFIG_HAS_DMA=y
|
|
||||||
CONFIG_HAS_IOMEM=y
|
|
||||||
CONFIG_HAS_IOPORT=y
|
|
||||||
CONFIG_HID=m
|
|
||||||
# CONFIG_HID_SUPPORT is not set
|
|
||||||
CONFIG_HW_HAS_PCI=y
|
|
||||||
CONFIG_HW_RANDOM=y
|
|
||||||
CONFIG_HZ=250
|
|
||||||
# CONFIG_HZ_100 is not set
|
|
||||||
CONFIG_HZ_250=y
|
|
||||||
# CONFIG_I2C is not set
|
|
||||||
# CONFIG_IDE is not set
|
|
||||||
# CONFIG_IKCONFIG is not set
|
|
||||||
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
|
|
||||||
CONFIG_INITRAMFS_SOURCE=""
|
|
||||||
CONFIG_INPUT=m
|
|
||||||
# CONFIG_IP6_NF_MATCH_FRAG is not set
|
|
||||||
# CONFIG_IP6_NF_MATCH_HL is not set
|
|
||||||
# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
|
|
||||||
# CONFIG_IP6_NF_MATCH_OPTS is not set
|
|
||||||
# CONFIG_IP6_NF_MATCH_RT is not set
|
|
||||||
# CONFIG_IP6_NF_TARGET_HL is not set
|
|
||||||
CONFIG_IPW2200_QOS=y
|
|
||||||
# CONFIG_IP_ROUTE_VERBOSE is not set
|
|
||||||
CONFIG_IRQ_CPU=y
|
|
||||||
# CONFIG_LEDS_ALIX is not set
|
|
||||||
# CONFIG_LEDS_GPIO is not set
|
|
||||||
# CONFIG_LEMOTE_FULONG is not set
|
|
||||||
# CONFIG_LLC2 is not set
|
|
||||||
# CONFIG_MACH_ALCHEMY is not set
|
|
||||||
# CONFIG_MACH_DECSTATION is not set
|
|
||||||
# CONFIG_MACH_JAZZ is not set
|
|
||||||
# CONFIG_MACH_VR41XX is not set
|
|
||||||
CONFIG_MIPS=y
|
|
||||||
# CONFIG_MIPS_ATLAS is not set
|
|
||||||
# CONFIG_MIPS_COBALT is not set
|
|
||||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
|
||||||
# CONFIG_MIPS_MALTA is not set
|
|
||||||
CONFIG_MIPS_MT_DISABLED=y
|
|
||||||
# CONFIG_MIPS_MT_SMP is not set
|
|
||||||
# CONFIG_MIPS_MT_SMTC is not set
|
|
||||||
# CONFIG_MIPS_SEAD is not set
|
|
||||||
# CONFIG_MIPS_SIM is not set
|
|
||||||
CONFIG_MTD=y
|
|
||||||
# CONFIG_MTD_ABSENT is not set
|
|
||||||
CONFIG_MTD_BCM47XX=y
|
|
||||||
CONFIG_MTD_BLKDEVS=y
|
|
||||||
CONFIG_MTD_BLOCK=y
|
|
||||||
# CONFIG_MTD_BLOCK2MTD is not set
|
|
||||||
CONFIG_MTD_CFI=y
|
|
||||||
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
|
|
||||||
CONFIG_MTD_CFI_AMDSTD=y
|
|
||||||
CONFIG_MTD_CFI_I1=y
|
|
||||||
CONFIG_MTD_CFI_I2=y
|
|
||||||
# CONFIG_MTD_CFI_I4 is not set
|
|
||||||
# CONFIG_MTD_CFI_I8 is not set
|
|
||||||
CONFIG_MTD_CFI_INTELEXT=y
|
|
||||||
# CONFIG_MTD_CFI_STAA is not set
|
|
||||||
CONFIG_MTD_CFI_UTIL=y
|
|
||||||
CONFIG_MTD_CHAR=y
|
|
||||||
# CONFIG_MTD_CMDLINE_PARTS is not set
|
|
||||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
|
||||||
# CONFIG_MTD_CONCAT is not set
|
|
||||||
# CONFIG_MTD_DEBUG is not set
|
|
||||||
# CONFIG_MTD_DOC2000 is not set
|
|
||||||
# CONFIG_MTD_DOC2001 is not set
|
|
||||||
# CONFIG_MTD_DOC2001PLUS is not set
|
|
||||||
CONFIG_MTD_GEN_PROBE=y
|
|
||||||
# CONFIG_MTD_JEDECPROBE is not set
|
|
||||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
|
||||||
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
|
|
||||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
|
||||||
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
|
|
||||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
|
||||||
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
|
|
||||||
# CONFIG_MTD_MTDRAM is not set
|
|
||||||
# CONFIG_MTD_ONENAND is not set
|
|
||||||
CONFIG_MTD_PARTITIONS=y
|
|
||||||
# CONFIG_MTD_PCI is not set
|
|
||||||
# CONFIG_MTD_PHRAM is not set
|
|
||||||
# CONFIG_MTD_PHYSMAP is not set
|
|
||||||
# CONFIG_MTD_PLATRAM is not set
|
|
||||||
# CONFIG_MTD_PMC551 is not set
|
|
||||||
# CONFIG_MTD_RAM is not set
|
|
||||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
|
||||||
# CONFIG_MTD_ROM is not set
|
|
||||||
# CONFIG_MTD_SLRAM is not set
|
|
||||||
# CONFIG_NATSEMI is not set
|
|
||||||
# CONFIG_NE2K_PCI is not set
|
|
||||||
CONFIG_NETDEV_1000=y
|
|
||||||
# CONFIG_NET_EMATCH is not set
|
|
||||||
# CONFIG_NET_IPGRE_BROADCAST is not set
|
|
||||||
# CONFIG_NET_PKTGEN is not set
|
|
||||||
# CONFIG_NET_SCH_NETEM is not set
|
|
||||||
# CONFIG_NET_VENDOR_3COM is not set
|
|
||||||
# CONFIG_NO_IOPORT is not set
|
|
||||||
# CONFIG_PAGE_SIZE_16KB is not set
|
|
||||||
CONFIG_PAGE_SIZE_4KB=y
|
|
||||||
# CONFIG_PAGE_SIZE_64KB is not set
|
|
||||||
# CONFIG_PAGE_SIZE_8KB is not set
|
|
||||||
CONFIG_PCI=y
|
|
||||||
# CONFIG_PMC_MSP is not set
|
|
||||||
# CONFIG_PMC_YOSEMITE is not set
|
|
||||||
# CONFIG_PNX8550_JBS is not set
|
|
||||||
# CONFIG_PNX8550_STB810 is not set
|
|
||||||
# CONFIG_PPP_MULTILINK is not set
|
|
||||||
# CONFIG_PPP_SYNC_TTY is not set
|
|
||||||
# CONFIG_PROC_KCORE is not set
|
|
||||||
# CONFIG_RTC is not set
|
|
||||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
|
||||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
|
||||||
# CONFIG_SCSI_MULTI_LUN is not set
|
|
||||||
CONFIG_SCSI_WAIT_SCAN=m
|
|
||||||
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
|
|
||||||
CONFIG_SERIAL_8250_EXTENDED=y
|
|
||||||
# CONFIG_SERIAL_8250_MANY_PORTS is not set
|
|
||||||
# CONFIG_SERIAL_8250_RSA is not set
|
|
||||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
|
||||||
# CONFIG_SGI_IP22 is not set
|
|
||||||
# CONFIG_SGI_IP27 is not set
|
|
||||||
# CONFIG_SGI_IP32 is not set
|
|
||||||
# CONFIG_SIBYTE_BIGSUR is not set
|
|
||||||
# CONFIG_SIBYTE_CARMEL is not set
|
|
||||||
# CONFIG_SIBYTE_CRHINE is not set
|
|
||||||
# CONFIG_SIBYTE_CRHONE is not set
|
|
||||||
# CONFIG_SIBYTE_LITTLESUR is not set
|
|
||||||
# CONFIG_SIBYTE_PTSWARM is not set
|
|
||||||
# CONFIG_SIBYTE_RHONE is not set
|
|
||||||
# CONFIG_SIBYTE_SENTOSA is not set
|
|
||||||
# CONFIG_SIBYTE_SWARM is not set
|
|
||||||
# CONFIG_SPARSEMEM_STATIC is not set
|
|
||||||
CONFIG_SSB=y
|
|
||||||
CONFIG_SSB_DEBUG=y
|
|
||||||
CONFIG_SSB_DRIVER_EXTIF=y
|
|
||||||
# CONFIG_SSB_DRIVER_GIGE is not set
|
|
||||||
CONFIG_SSB_DRIVER_MIPS=y
|
|
||||||
CONFIG_SSB_DRIVER_PCICORE=y
|
|
||||||
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
|
|
||||||
CONFIG_SSB_EMBEDDED=y
|
|
||||||
CONFIG_SSB_PCICORE_HOSTMODE=y
|
|
||||||
CONFIG_SSB_PCIHOST=y
|
|
||||||
CONFIG_SSB_PCIHOST_POSSIBLE=y
|
|
||||||
CONFIG_SSB_POSSIBLE=y
|
|
||||||
CONFIG_SSB_SERIAL=y
|
|
||||||
# CONFIG_SSB_SILENT is not set
|
|
||||||
CONFIG_SYSVIPC_SYSCTL=y
|
|
||||||
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
|
||||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
|
||||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
|
||||||
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
|
||||||
# CONFIG_TC35815 is not set
|
|
||||||
# CONFIG_TOSHIBA_JMR3927 is not set
|
|
||||||
# CONFIG_TOSHIBA_RBTX4927 is not set
|
|
||||||
# CONFIG_TOSHIBA_RBTX4938 is not set
|
|
||||||
CONFIG_TRAD_SIGNALS=y
|
|
||||||
CONFIG_USB=m
|
|
||||||
# CONFIG_USB_CATC is not set
|
|
||||||
CONFIG_USB_EHCI_HCD=m
|
|
||||||
CONFIG_USB_EHCI_SPLIT_ISO=y
|
|
||||||
# CONFIG_USB_KAWETH is not set
|
|
||||||
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
|
|
||||||
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
|
|
||||||
CONFIG_USB_OHCI_HCD=m
|
|
||||||
CONFIG_USB_OHCI_HCD_SSB=y
|
|
||||||
# CONFIG_USB_PEGASUS is not set
|
|
||||||
# CONFIG_USB_R8A66597_HCD is not set
|
|
||||||
# CONFIG_USB_SERIAL_OTI6858 is not set
|
|
||||||
# CONFIG_USB_STORAGE_ALAUDA is not set
|
|
||||||
# CONFIG_USB_STORAGE_DATAFAB is not set
|
|
||||||
# CONFIG_USB_STORAGE_DPCM is not set
|
|
||||||
# CONFIG_USB_STORAGE_FREECOM is not set
|
|
||||||
# CONFIG_USB_STORAGE_JUMPSHOT is not set
|
|
||||||
# CONFIG_USB_STORAGE_KARMA is not set
|
|
||||||
# CONFIG_USB_STORAGE_SDDR09 is not set
|
|
||||||
# CONFIG_USB_STORAGE_SDDR55 is not set
|
|
||||||
# CONFIG_USB_STORAGE_USBAT is not set
|
|
||||||
CONFIG_USB_UHCI_HCD=m
|
|
||||||
# CONFIG_USER_NS is not set
|
|
||||||
# CONFIG_VGASTATE is not set
|
|
||||||
# CONFIG_VIA_RHINE is not set
|
|
||||||
# CONFIG_WATCHDOG is not set
|
|
||||||
CONFIG_ZONE_DMA_FLAG=0
|
|
||||||
@ -1,7 +0,0 @@
|
|||||||
#
|
|
||||||
# Makefile for the BCM47xx specific kernel interface routines
|
|
||||||
# under Linux.
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y := irq.o prom.o setup.o time.o
|
|
||||||
obj-y += nvram.o cfe_env.o
|
|
||||||
@ -1,229 +0,0 @@
|
|||||||
/*
|
|
||||||
* CFE environment variable access
|
|
||||||
*
|
|
||||||
* Copyright 2001-2003, Broadcom Corporation
|
|
||||||
* Copyright 2006, Felix Fietkau <nbd@openwrt.org>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/string.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/uaccess.h>
|
|
||||||
|
|
||||||
#define NVRAM_SIZE (0x1ff0)
|
|
||||||
static char _nvdata[NVRAM_SIZE];
|
|
||||||
static char _valuestr[256];
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TLV types. These codes are used in the "type-length-value"
|
|
||||||
* encoding of the items stored in the NVRAM device (flash or EEPROM)
|
|
||||||
*
|
|
||||||
* The layout of the flash/nvram is as follows:
|
|
||||||
*
|
|
||||||
* <type> <length> <data ...> <type> <length> <data ...> <type_end>
|
|
||||||
*
|
|
||||||
* The type code of "ENV_TLV_TYPE_END" marks the end of the list.
|
|
||||||
* The "length" field marks the length of the data section, not
|
|
||||||
* including the type and length fields.
|
|
||||||
*
|
|
||||||
* Environment variables are stored as follows:
|
|
||||||
*
|
|
||||||
* <type_env> <length> <flags> <name> = <value>
|
|
||||||
*
|
|
||||||
* If bit 0 (low bit) is set, the length is an 8-bit value.
|
|
||||||
* If bit 0 (low bit) is clear, the length is a 16-bit value
|
|
||||||
*
|
|
||||||
* Bit 7 set indicates "user" TLVs. In this case, bit 0 still
|
|
||||||
* indicates the size of the length field.
|
|
||||||
*
|
|
||||||
* Flags are from the constants below:
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define ENV_LENGTH_16BITS 0x00 /* for low bit */
|
|
||||||
#define ENV_LENGTH_8BITS 0x01
|
|
||||||
|
|
||||||
#define ENV_TYPE_USER 0x80
|
|
||||||
|
|
||||||
#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
|
|
||||||
#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The actual TLV types we support
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ENV_TLV_TYPE_END 0x00
|
|
||||||
#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment variable flags
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define ENV_FLG_NORMAL 0x00 /* normal read/write */
|
|
||||||
#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
|
|
||||||
#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
|
|
||||||
|
|
||||||
#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
|
|
||||||
#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
|
|
||||||
|
|
||||||
|
|
||||||
/* *********************************************************************
|
|
||||||
* _nvram_read(buffer,offset,length)
|
|
||||||
*
|
|
||||||
* Read data from the NVRAM device
|
|
||||||
*
|
|
||||||
* Input parameters:
|
|
||||||
* buffer - destination buffer
|
|
||||||
* offset - offset of data to read
|
|
||||||
* length - number of bytes to read
|
|
||||||
*
|
|
||||||
* Return value:
|
|
||||||
* number of bytes read, or <0 if error occured
|
|
||||||
********************************************************************* */
|
|
||||||
static int
|
|
||||||
_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
if (offset > NVRAM_SIZE)
|
|
||||||
return -1;
|
|
||||||
|
|
||||||
for ( i = 0; i < length; i++) {
|
|
||||||
buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
|
|
||||||
}
|
|
||||||
return length;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static char*
|
|
||||||
_strnchr(const char *dest,int c,size_t cnt)
|
|
||||||
{
|
|
||||||
while (*dest && (cnt > 0)) {
|
|
||||||
if (*dest == c) return (char *) dest;
|
|
||||||
dest++;
|
|
||||||
cnt--;
|
|
||||||
}
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Core support API: Externally visible.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Get the value of an NVRAM variable
|
|
||||||
* @param name name of variable to get
|
|
||||||
* @return value of variable or NULL if undefined
|
|
||||||
*/
|
|
||||||
|
|
||||||
char*
|
|
||||||
cfe_env_get(unsigned char *nv_buf, char* name)
|
|
||||||
{
|
|
||||||
int size;
|
|
||||||
unsigned char *buffer;
|
|
||||||
unsigned char *ptr;
|
|
||||||
unsigned char *envval;
|
|
||||||
unsigned int reclen;
|
|
||||||
unsigned int rectype;
|
|
||||||
int offset;
|
|
||||||
int flg;
|
|
||||||
|
|
||||||
if (!strcmp(name, "nvram_type"))
|
|
||||||
return "cfe";
|
|
||||||
|
|
||||||
size = NVRAM_SIZE;
|
|
||||||
buffer = &_nvdata[0];
|
|
||||||
|
|
||||||
ptr = buffer;
|
|
||||||
offset = 0;
|
|
||||||
|
|
||||||
/* Read the record type and length */
|
|
||||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
|
|
||||||
goto error;
|
|
||||||
}
|
|
||||||
|
|
||||||
while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
|
|
||||||
|
|
||||||
/* Adjust pointer for TLV type */
|
|
||||||
rectype = *(ptr);
|
|
||||||
offset++;
|
|
||||||
size--;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Read the length. It can be either 1 or 2 bytes
|
|
||||||
* depending on the code
|
|
||||||
*/
|
|
||||||
if (rectype & ENV_LENGTH_8BITS) {
|
|
||||||
/* Read the record type and length - 8 bits */
|
|
||||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
|
|
||||||
goto error;
|
|
||||||
}
|
|
||||||
reclen = *(ptr);
|
|
||||||
size--;
|
|
||||||
offset++;
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
/* Read the record type and length - 16 bits, MSB first */
|
|
||||||
if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
|
|
||||||
goto error;
|
|
||||||
}
|
|
||||||
reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
|
|
||||||
size -= 2;
|
|
||||||
offset += 2;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (reclen > size)
|
|
||||||
break; /* should not happen, bad NVRAM */
|
|
||||||
|
|
||||||
switch (rectype) {
|
|
||||||
case ENV_TLV_TYPE_ENV:
|
|
||||||
/* Read the TLV data */
|
|
||||||
if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
|
|
||||||
goto error;
|
|
||||||
flg = *ptr++;
|
|
||||||
envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
|
|
||||||
if (envval) {
|
|
||||||
*envval++ = '\0';
|
|
||||||
memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
|
|
||||||
_valuestr[(reclen-1)-(envval-ptr)] = '\0';
|
|
||||||
#if 0
|
|
||||||
printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
|
|
||||||
#endif
|
|
||||||
if(!strcmp(ptr, name)){
|
|
||||||
return _valuestr;
|
|
||||||
}
|
|
||||||
if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
|
|
||||||
return _valuestr;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
/* Unknown TLV type, skip it. */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Advance to next TLV
|
|
||||||
*/
|
|
||||||
|
|
||||||
size -= (int)reclen;
|
|
||||||
offset += reclen;
|
|
||||||
|
|
||||||
/* Read the next record type */
|
|
||||||
ptr = buffer;
|
|
||||||
if (_nvram_read(nv_buf, ptr,offset,1) != 1)
|
|
||||||
goto error;
|
|
||||||
}
|
|
||||||
|
|
||||||
error:
|
|
||||||
return NULL;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,37 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __NVRAM_H
|
|
||||||
#define __NVRAM_H
|
|
||||||
|
|
||||||
struct nvram_header {
|
|
||||||
u32 magic;
|
|
||||||
u32 len;
|
|
||||||
u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
|
|
||||||
u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
|
|
||||||
u32 config_ncdl; /* ncdl values for memc */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct nvram_tuple {
|
|
||||||
char *name;
|
|
||||||
char *value;
|
|
||||||
struct nvram_tuple *next;
|
|
||||||
};
|
|
||||||
|
|
||||||
#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
|
|
||||||
#define NVRAM_VERSION 1
|
|
||||||
#define NVRAM_HEADER_SIZE 20
|
|
||||||
#define NVRAM_SPACE 0x8000
|
|
||||||
|
|
||||||
#define NVRAM_MAX_VALUE_LEN 255
|
|
||||||
#define NVRAM_MAX_PARAM_LEN 64
|
|
||||||
|
|
||||||
char *nvram_get(const char *name);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,86 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
|
||||||
* Copyright (C) 2008 Michael Buesch <mb@bu3sch.de>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
|
||||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along
|
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/errno.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/interrupt.h>
|
|
||||||
#include <linux/irq.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/smp.h>
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/pci.h>
|
|
||||||
#include <linux/ssb/ssb.h>
|
|
||||||
|
|
||||||
#include <asm/cpu.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/irq.h>
|
|
||||||
#include <asm/irq_cpu.h>
|
|
||||||
|
|
||||||
|
|
||||||
extern struct ssb_bus ssb;
|
|
||||||
|
|
||||||
|
|
||||||
void plat_irq_dispatch(void)
|
|
||||||
{
|
|
||||||
u32 cause;
|
|
||||||
|
|
||||||
cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
|
|
||||||
|
|
||||||
clear_c0_status(cause);
|
|
||||||
|
|
||||||
if (cause & CAUSEF_IP7)
|
|
||||||
do_IRQ(7);
|
|
||||||
if (cause & CAUSEF_IP2)
|
|
||||||
do_IRQ(2);
|
|
||||||
if (cause & CAUSEF_IP3)
|
|
||||||
do_IRQ(3);
|
|
||||||
if (cause & CAUSEF_IP4)
|
|
||||||
do_IRQ(4);
|
|
||||||
if (cause & CAUSEF_IP5)
|
|
||||||
do_IRQ(5);
|
|
||||||
if (cause & CAUSEF_IP6)
|
|
||||||
do_IRQ(6);
|
|
||||||
}
|
|
||||||
|
|
||||||
void __init arch_init_irq(void)
|
|
||||||
{
|
|
||||||
mips_cpu_irq_init();
|
|
||||||
}
|
|
||||||
|
|
||||||
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|
||||||
{
|
|
||||||
int res;
|
|
||||||
|
|
||||||
res = ssb_pcibios_map_irq(dev, slot, pin);
|
|
||||||
if (res < 0) {
|
|
||||||
printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
|
|
||||||
dev->dev.bus_id);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
/* IRQ-0 and IRQ-1 are software interrupts. */
|
|
||||||
WARN_ON((res == 0) || (res == 1));
|
|
||||||
|
|
||||||
return res;
|
|
||||||
}
|
|
||||||
@ -1,125 +0,0 @@
|
|||||||
/*
|
|
||||||
* BCM947xx nvram variable access
|
|
||||||
*
|
|
||||||
* Copyright 2005, Broadcom Corporation
|
|
||||||
* Copyright 2006, Felix Fietkau <nbd@openwrt.org>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/ssb/ssb.h>
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/string.h>
|
|
||||||
#include <linux/interrupt.h>
|
|
||||||
#include <linux/spinlock.h>
|
|
||||||
#include <linux/slab.h>
|
|
||||||
#include <asm/byteorder.h>
|
|
||||||
#include <asm/bootinfo.h>
|
|
||||||
#include <asm/addrspace.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/uaccess.h>
|
|
||||||
|
|
||||||
#include <nvram.h>
|
|
||||||
|
|
||||||
#define MB * 1048576
|
|
||||||
extern struct ssb_bus ssb;
|
|
||||||
|
|
||||||
static char nvram_buf[NVRAM_SPACE];
|
|
||||||
static int cfe_env;
|
|
||||||
extern char *cfe_env_get(char *nv_buf, const char *name);
|
|
||||||
|
|
||||||
/* Probe for NVRAM header */
|
|
||||||
static void __init early_nvram_init(void)
|
|
||||||
{
|
|
||||||
struct ssb_mipscore *mcore = &ssb.mipscore;
|
|
||||||
struct nvram_header *header;
|
|
||||||
int i;
|
|
||||||
u32 base, lim, off;
|
|
||||||
u32 *src, *dst;
|
|
||||||
|
|
||||||
base = mcore->flash_window;
|
|
||||||
lim = mcore->flash_window_size;
|
|
||||||
cfe_env = 0;
|
|
||||||
|
|
||||||
|
|
||||||
/* XXX: hack for supporting the CFE environment stuff on WGT634U */
|
|
||||||
if (lim >= 8 MB) {
|
|
||||||
src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
|
|
||||||
dst = (u32 *) nvram_buf;
|
|
||||||
|
|
||||||
if ((*src & 0xff00ff) == 0x000001) {
|
|
||||||
printk("early_nvram_init: WGT634U NVRAM found.\n");
|
|
||||||
|
|
||||||
for (i = 0; i < 0x1ff0; i++) {
|
|
||||||
if (*src == 0xFFFFFFFF)
|
|
||||||
break;
|
|
||||||
*dst++ = *src++;
|
|
||||||
}
|
|
||||||
cfe_env = 1;
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
off = 0x20000;
|
|
||||||
while (off <= lim) {
|
|
||||||
/* Windowed flash access */
|
|
||||||
header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
|
|
||||||
if (header->magic == NVRAM_HEADER)
|
|
||||||
goto found;
|
|
||||||
off <<= 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
|
|
||||||
header = (struct nvram_header *) KSEG1ADDR(base + 4096);
|
|
||||||
if (header->magic == NVRAM_HEADER)
|
|
||||||
goto found;
|
|
||||||
|
|
||||||
header = (struct nvram_header *) KSEG1ADDR(base + 1024);
|
|
||||||
if (header->magic == NVRAM_HEADER)
|
|
||||||
goto found;
|
|
||||||
|
|
||||||
return;
|
|
||||||
|
|
||||||
found:
|
|
||||||
src = (u32 *) header;
|
|
||||||
dst = (u32 *) nvram_buf;
|
|
||||||
for (i = 0; i < sizeof(struct nvram_header); i += 4)
|
|
||||||
*dst++ = *src++;
|
|
||||||
for (; i < header->len && i < NVRAM_SPACE; i += 4)
|
|
||||||
*dst++ = le32_to_cpu(*src++);
|
|
||||||
}
|
|
||||||
|
|
||||||
char *nvram_get(const char *name)
|
|
||||||
{
|
|
||||||
char *var, *value, *end, *eq;
|
|
||||||
|
|
||||||
if (!name)
|
|
||||||
return NULL;
|
|
||||||
|
|
||||||
if (!nvram_buf[0])
|
|
||||||
early_nvram_init();
|
|
||||||
|
|
||||||
if (cfe_env)
|
|
||||||
return cfe_env_get(nvram_buf, name);
|
|
||||||
|
|
||||||
/* Look for name=value and return value */
|
|
||||||
var = &nvram_buf[sizeof(struct nvram_header)];
|
|
||||||
end = nvram_buf + sizeof(nvram_buf) - 2;
|
|
||||||
end[0] = end[1] = '\0';
|
|
||||||
for (; *var; var = value + strlen(value) + 1) {
|
|
||||||
if (!(eq = strchr(var, '=')))
|
|
||||||
break;
|
|
||||||
value = eq + 1;
|
|
||||||
if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
|
|
||||||
return value;
|
|
||||||
}
|
|
||||||
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
EXPORT_SYMBOL(nvram_get);
|
|
||||||
@ -1,61 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
|
||||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along
|
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/mm.h>
|
|
||||||
#include <linux/sched.h>
|
|
||||||
#include <linux/bootmem.h>
|
|
||||||
|
|
||||||
#include <asm/addrspace.h>
|
|
||||||
#include <asm/bootinfo.h>
|
|
||||||
#include <asm/pmon.h>
|
|
||||||
#include "../cfe/cfe_private.h"
|
|
||||||
|
|
||||||
const char *get_system_type(void)
|
|
||||||
{
|
|
||||||
return "Broadcom BCM47xx";
|
|
||||||
}
|
|
||||||
|
|
||||||
void __init prom_init(void)
|
|
||||||
{
|
|
||||||
unsigned long mem;
|
|
||||||
|
|
||||||
mips_machgroup = MACH_GROUP_BRCM;
|
|
||||||
mips_machtype = MACH_BCM47XX;
|
|
||||||
|
|
||||||
cfe_setup(fw_arg0, fw_arg1, fw_arg2, fw_arg3);
|
|
||||||
|
|
||||||
/* Figure out memory size by finding aliases */
|
|
||||||
for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
|
|
||||||
if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
|
|
||||||
*(unsigned long *)(prom_init))
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
add_memory_region(0, mem, BOOT_MEM_RAM);
|
|
||||||
}
|
|
||||||
|
|
||||||
void __init prom_free_prom_memory(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
@ -1,246 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
|
||||||
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
|
|
||||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
|
||||||
* Copyright (C) 2006-2008 Michael Buesch <mb@bu3sch.de>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
|
||||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along
|
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/tty.h>
|
|
||||||
#include <linux/serial.h>
|
|
||||||
#include <linux/serial_core.h>
|
|
||||||
#include <linux/serial_reg.h>
|
|
||||||
#include <linux/serial_8250.h>
|
|
||||||
#include <asm/bootinfo.h>
|
|
||||||
#include <asm/time.h>
|
|
||||||
#include <asm/reboot.h>
|
|
||||||
#include <asm/cfe.h>
|
|
||||||
#include <linux/pm.h>
|
|
||||||
#include <linux/ssb/ssb.h>
|
|
||||||
#include <linux/ssb/ssb_embedded.h>
|
|
||||||
|
|
||||||
#include <nvram.h>
|
|
||||||
|
|
||||||
extern void bcm47xx_pci_init(void);
|
|
||||||
extern void bcm47xx_time_init(void);
|
|
||||||
|
|
||||||
struct ssb_bus ssb;
|
|
||||||
|
|
||||||
|
|
||||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
|
||||||
{
|
|
||||||
int err;
|
|
||||||
|
|
||||||
err = ssb_pcibios_plat_dev_init(dev);
|
|
||||||
if (err) {
|
|
||||||
printk(KERN_ALERT "PCI: Failed to init device %s\n",
|
|
||||||
pci_name(dev));
|
|
||||||
}
|
|
||||||
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void bcm47xx_machine_restart(char *command)
|
|
||||||
{
|
|
||||||
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
|
|
||||||
local_irq_disable();
|
|
||||||
/* CFE has a reboot callback, but that does not work.
|
|
||||||
* Oopses with: Reserved instruction in kernel code.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Set the watchdog timer to reset immediately */
|
|
||||||
if (ssb_watchdog_timer_set(&ssb, 1))
|
|
||||||
printk(KERN_EMERG "SSB watchdog-triggered reboot failed!\n");
|
|
||||||
while (1)
|
|
||||||
cpu_relax();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void bcm47xx_machine_halt(void)
|
|
||||||
{
|
|
||||||
/* Disable interrupts and watchdog and spin forever */
|
|
||||||
local_irq_disable();
|
|
||||||
if (ssb_watchdog_timer_set(&ssb, 0))
|
|
||||||
printk(KERN_EMERG "Failed to disable SSB watchdog!\n");
|
|
||||||
while (1)
|
|
||||||
cpu_relax();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void e_aton(char *str, char *dest)
|
|
||||||
{
|
|
||||||
int i = 0;
|
|
||||||
|
|
||||||
if (str == NULL) {
|
|
||||||
memset(dest, 0, 6);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (;;) {
|
|
||||||
dest[i++] = (char) simple_strtoul(str, NULL, 16);
|
|
||||||
str += 2;
|
|
||||||
if (!*str++ || i == 6)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
|
|
||||||
{
|
|
||||||
char *s;
|
|
||||||
|
|
||||||
memset(sprom, 0xFF, sizeof(struct ssb_sprom));
|
|
||||||
|
|
||||||
sprom->revision = 1;
|
|
||||||
if ((s = nvram_get("il0macaddr")))
|
|
||||||
e_aton(s, sprom->il0mac);
|
|
||||||
if ((s = nvram_get("et0macaddr")))
|
|
||||||
e_aton(s, sprom->et0mac);
|
|
||||||
if ((s = nvram_get("et1macaddr")))
|
|
||||||
e_aton(s, sprom->et1mac);
|
|
||||||
if ((s = nvram_get("et0phyaddr")))
|
|
||||||
sprom->et0phyaddr = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("et1phyaddr")))
|
|
||||||
sprom->et1phyaddr = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("et0mdcport")))
|
|
||||||
sprom->et0mdcport = !!simple_strtoul(s, NULL, 10);
|
|
||||||
if ((s = nvram_get("et1mdcport")))
|
|
||||||
sprom->et1mdcport = !!simple_strtoul(s, NULL, 10);
|
|
||||||
if ((s = nvram_get("pa0b0")))
|
|
||||||
sprom->pa0b0 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa0b1")))
|
|
||||||
sprom->pa0b1 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa0b2")))
|
|
||||||
sprom->pa0b2 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa1b0")))
|
|
||||||
sprom->pa1b0 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa1b1")))
|
|
||||||
sprom->pa1b1 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa1b2")))
|
|
||||||
sprom->pa1b2 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("wl0gpio0")))
|
|
||||||
sprom->gpio0 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("wl0gpio1")))
|
|
||||||
sprom->gpio1 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("wl0gpio2")))
|
|
||||||
sprom->gpio2 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("wl0gpio3")))
|
|
||||||
sprom->gpio3 = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa0maxpwr")))
|
|
||||||
sprom->maxpwr_bg = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa1maxpwr")))
|
|
||||||
sprom->maxpwr_a = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa0itssit")))
|
|
||||||
sprom->itssi_bg = simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("pa1itssit")))
|
|
||||||
sprom->itssi_a = simple_strtoul(s, NULL, 0);
|
|
||||||
sprom->boardflags_lo = 0;
|
|
||||||
if ((s = nvram_get("boardflags")))
|
|
||||||
sprom->boardflags_lo = simple_strtoul(s, NULL, 0);
|
|
||||||
sprom->boardflags_hi = 0;
|
|
||||||
if ((s = nvram_get("boardflags2")))
|
|
||||||
sprom->boardflags_hi = simple_strtoul(s, NULL, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int bcm47xx_get_invariants(struct ssb_bus *bus, struct ssb_init_invariants *iv)
|
|
||||||
{
|
|
||||||
char *s;
|
|
||||||
|
|
||||||
iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
|
|
||||||
if ((s = nvram_get("boardtype")))
|
|
||||||
iv->boardinfo.type = (u16)simple_strtoul(s, NULL, 0);
|
|
||||||
if ((s = nvram_get("boardrev")))
|
|
||||||
iv->boardinfo.rev = (u16)simple_strtoul(s, NULL, 0);
|
|
||||||
|
|
||||||
bcm47xx_fill_sprom(&iv->sprom);
|
|
||||||
|
|
||||||
if ((s = nvram_get("cardbus")))
|
|
||||||
iv->has_cardbus_slot = !!simple_strtoul(s, NULL, 10);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void __init plat_mem_setup(void)
|
|
||||||
{
|
|
||||||
int i, err;
|
|
||||||
char *s;
|
|
||||||
struct ssb_mipscore *mcore;
|
|
||||||
|
|
||||||
err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_get_invariants);
|
|
||||||
if (err) {
|
|
||||||
const char *msg = "Failed to initialize SSB bus (err %d)\n";
|
|
||||||
cfe_printk(msg, err); /* Make sure the message gets out of the box. */
|
|
||||||
panic(msg, err);
|
|
||||||
}
|
|
||||||
mcore = &ssb.mipscore;
|
|
||||||
|
|
||||||
s = nvram_get("kernel_args");
|
|
||||||
if (s && !strncmp(s, "console=ttyS1", 13)) {
|
|
||||||
struct ssb_serial_port port;
|
|
||||||
|
|
||||||
cfe_printk("Swapping serial ports!\n");
|
|
||||||
/* swap serial ports */
|
|
||||||
memcpy(&port, &mcore->serial_ports[0], sizeof(port));
|
|
||||||
memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
|
|
||||||
memcpy(&mcore->serial_ports[1], &port, sizeof(port));
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < mcore->nr_serial_ports; i++) {
|
|
||||||
struct ssb_serial_port *port = &(mcore->serial_ports[i]);
|
|
||||||
struct uart_port s;
|
|
||||||
|
|
||||||
memset(&s, 0, sizeof(s));
|
|
||||||
s.line = i;
|
|
||||||
s.membase = port->regs;
|
|
||||||
s.irq = port->irq + 2;
|
|
||||||
s.uartclk = port->baud_base;
|
|
||||||
s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
|
|
||||||
s.iotype = SERIAL_IO_MEM;
|
|
||||||
s.regshift = port->reg_shift;
|
|
||||||
|
|
||||||
early_serial_setup(&s);
|
|
||||||
}
|
|
||||||
cfe_printk("Serial init done.\n");
|
|
||||||
|
|
||||||
_machine_restart = bcm47xx_machine_restart;
|
|
||||||
_machine_halt = bcm47xx_machine_halt;
|
|
||||||
pm_power_off = bcm47xx_machine_halt;
|
|
||||||
board_time_init = bcm47xx_time_init;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int __init bcm47xx_register_gpiodev(void)
|
|
||||||
{
|
|
||||||
static struct resource res = {
|
|
||||||
.start = 0xFFFFFFFF,
|
|
||||||
};
|
|
||||||
struct platform_device *pdev;
|
|
||||||
|
|
||||||
pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
|
|
||||||
if (!pdev) {
|
|
||||||
printk(KERN_ERR "bcm47xx: GPIODEV init failed\n");
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
device_initcall(bcm47xx_register_gpiodev);
|
|
||||||
|
|
||||||
EXPORT_SYMBOL(ssb);
|
|
||||||
@ -1,62 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
|
||||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along
|
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/sched.h>
|
|
||||||
#include <linux/serial_reg.h>
|
|
||||||
#include <linux/interrupt.h>
|
|
||||||
#include <linux/ssb/ssb.h>
|
|
||||||
#include <asm/addrspace.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/time.h>
|
|
||||||
|
|
||||||
extern struct ssb_bus ssb;
|
|
||||||
|
|
||||||
void __init
|
|
||||||
bcm47xx_time_init(void)
|
|
||||||
{
|
|
||||||
unsigned long hz;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Use deterministic values for initial counter interrupt
|
|
||||||
* so that calibrate delay avoids encountering a counter wrap.
|
|
||||||
*/
|
|
||||||
write_c0_count(0);
|
|
||||||
write_c0_compare(0xffff);
|
|
||||||
|
|
||||||
hz = ssb_cpu_clock(&ssb.mipscore) / 2;
|
|
||||||
if (!hz)
|
|
||||||
hz = 100000000;
|
|
||||||
|
|
||||||
/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
|
|
||||||
mips_hpt_frequency = hz;
|
|
||||||
}
|
|
||||||
|
|
||||||
void __init
|
|
||||||
plat_timer_setup(struct irqaction *irq)
|
|
||||||
{
|
|
||||||
/* Enable the timer interrupt */
|
|
||||||
setup_irq(7, irq);
|
|
||||||
}
|
|
||||||
@ -1,5 +0,0 @@
|
|||||||
#
|
|
||||||
# Makefile for the Broadcom Common Firmware Environment support
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y += cfe.o
|
|
||||||
@ -1,533 +0,0 @@
|
|||||||
/*
|
|
||||||
* Broadcom Common Firmware Environment (CFE) support
|
|
||||||
*
|
|
||||||
* Copyright 2000, 2001, 2002
|
|
||||||
* Broadcom Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2006 Michael Buesch
|
|
||||||
*
|
|
||||||
* Original Authors: Mitch Lichtenberg, Chris Demetriou
|
|
||||||
*
|
|
||||||
* This software is furnished under license and may be used and copied only
|
|
||||||
* in accordance with the following terms and conditions. Subject to these
|
|
||||||
* conditions, you may download, copy, install, use, modify and distribute
|
|
||||||
* modified or unmodified copies of this software in source and/or binary
|
|
||||||
* form. No title or ownership is transferred hereby.
|
|
||||||
*
|
|
||||||
* 1) Any source code used, modified or distributed must reproduce and
|
|
||||||
* retain this copyright notice and list of conditions as they appear in
|
|
||||||
* the source file.
|
|
||||||
*
|
|
||||||
* 2) No right is granted to use any trade name, trademark, or logo of
|
|
||||||
* Broadcom Corporation. The "Broadcom Corporation" name may not be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without the prior written permission of Broadcom Corporation.
|
|
||||||
*
|
|
||||||
* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
|
|
||||||
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
|
|
||||||
* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
|
|
||||||
* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
|
||||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
|
||||||
* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/string.h>
|
|
||||||
#include <linux/errno.h>
|
|
||||||
#include <linux/spinlock.h>
|
|
||||||
#include <asm/cfe.h>
|
|
||||||
|
|
||||||
#include "cfe_private.h"
|
|
||||||
|
|
||||||
|
|
||||||
static cfe_uint_t cfe_handle;
|
|
||||||
static int (*cfe_trampoline)(long handle, long iocb);
|
|
||||||
|
|
||||||
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
|
|
||||||
void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
|
|
||||||
unsigned long fwarg2, unsigned long fwarg3)
|
|
||||||
{
|
|
||||||
if (fwarg3 == 0x80300000) {
|
|
||||||
/* WRT54G workaround */
|
|
||||||
fwarg3 = CFE_EPTSEAL;
|
|
||||||
fwarg2 = 0xBFC00500;
|
|
||||||
}
|
|
||||||
if (fwarg3 != CFE_EPTSEAL) {
|
|
||||||
/* We are not booted from CFE */
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
if (fwarg1 == 0) {
|
|
||||||
/* We are on the boot CPU */
|
|
||||||
cfe_handle = (cfe_uint_t)fwarg0;
|
|
||||||
cfe_trampoline = CFE_TO_PTR(fwarg2);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_vprintk(const char *fmt, va_list args)
|
|
||||||
{
|
|
||||||
static char buffer[1024];
|
|
||||||
static DEFINE_SPINLOCK(lock);
|
|
||||||
static const char pfx[] = "CFE-console: ";
|
|
||||||
static const size_t pfx_len = sizeof(pfx) - 1;
|
|
||||||
unsigned long flags;
|
|
||||||
int len, cnt, pos;
|
|
||||||
int handle;
|
|
||||||
int res;
|
|
||||||
|
|
||||||
if (!cfe_present())
|
|
||||||
return -ENODEV;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&lock, flags);
|
|
||||||
handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
|
|
||||||
if (CFE_ISERR(handle)) {
|
|
||||||
len = -EIO;
|
|
||||||
goto out;
|
|
||||||
}
|
|
||||||
strcpy(buffer, pfx);
|
|
||||||
len = vscnprintf(buffer + pfx_len,
|
|
||||||
sizeof(buffer) - pfx_len - 2,
|
|
||||||
fmt, args);
|
|
||||||
len += pfx_len;
|
|
||||||
/* The CFE console requires CR-LF line-ends.
|
|
||||||
* Add a CR, if we only terminate lines with a LF.
|
|
||||||
* This does only fix CR-LF at the end of the string.
|
|
||||||
* So for multiple lines, use multiple cfe_vprintk calls.
|
|
||||||
*/
|
|
||||||
if (len > 1 &&
|
|
||||||
buffer[len - 1] == '\n' && buffer[len - 2] != '\r') {
|
|
||||||
buffer[len - 1] = '\r';
|
|
||||||
buffer[len] = '\n';
|
|
||||||
len += 1;
|
|
||||||
}
|
|
||||||
cnt = len;
|
|
||||||
pos = 0;
|
|
||||||
while (cnt > 0) {
|
|
||||||
res = cfe_write(handle, buffer + pos, len - pos);
|
|
||||||
if (CFE_ISERR(res)) {
|
|
||||||
len = -EIO;
|
|
||||||
goto out;
|
|
||||||
}
|
|
||||||
cnt -= res;
|
|
||||||
pos += res;
|
|
||||||
}
|
|
||||||
out:
|
|
||||||
spin_unlock_irqrestore(&lock, flags);
|
|
||||||
|
|
||||||
return len;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_printk(const char *fmt, ...)
|
|
||||||
{
|
|
||||||
va_list args;
|
|
||||||
int res;
|
|
||||||
|
|
||||||
va_start(args, fmt);
|
|
||||||
res = cfe_vprintk(fmt, args);
|
|
||||||
va_end(args);
|
|
||||||
|
|
||||||
return res;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int cfe_iocb_dispatch(struct cfe_iocb *iocb)
|
|
||||||
{
|
|
||||||
if (!cfe_present())
|
|
||||||
return CFE_ERR_UNSUPPORTED;
|
|
||||||
return cfe_trampoline((long)cfe_handle, (long)iocb);
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_present(void)
|
|
||||||
{
|
|
||||||
return (cfe_trampoline != NULL);
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_close(int handle)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_CLOSE;
|
|
||||||
iocb.handle = handle;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_FW_CPUCTL;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_cpuctl);
|
|
||||||
iocb.cpuctl.number = cpu;
|
|
||||||
iocb.cpuctl.command = CFE_CPU_CMD_START;
|
|
||||||
iocb.cpuctl.gp = gp;
|
|
||||||
iocb.cpuctl.sp = sp;
|
|
||||||
iocb.cpuctl.a1 = a1;
|
|
||||||
iocb.cpuctl.start_addr = (long)fn;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_cpu_stop(int cpu)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_FW_CPUCTL;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_cpuctl);
|
|
||||||
iocb.cpuctl.number = cpu;
|
|
||||||
iocb.cpuctl.command = CFE_CPU_CMD_STOP;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_ENV_ENUM;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_envbuf);
|
|
||||||
iocb.envbuf.index = idx;
|
|
||||||
iocb.envbuf.name = PTR_TO_CFE(name);
|
|
||||||
iocb.envbuf.name_len = namelen;
|
|
||||||
iocb.envbuf.val = PTR_TO_CFE(val);
|
|
||||||
iocb.envbuf.val_len = vallen;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_enumdev(int idx, char *name, int namelen)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
|
|
||||||
iocb.fcode = CFE_CMD_DEV_ENUM;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_envbuf);
|
|
||||||
iocb.envbuf.index = idx;
|
|
||||||
iocb.envbuf.name = PTR_TO_CFE(name);
|
|
||||||
iocb.envbuf.name_len = namelen;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
|
|
||||||
u64 *type)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
|
|
||||||
iocb.fcode = CFE_CMD_FW_MEMENUM;
|
|
||||||
iocb.flags = flags;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_meminfo);
|
|
||||||
iocb.meminfo.index = idx;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (!CFE_ISERR(iocb.status)) {
|
|
||||||
*start = iocb.meminfo.addr;
|
|
||||||
*length = iocb.meminfo.size;
|
|
||||||
*type = iocb.meminfo.type;
|
|
||||||
}
|
|
||||||
|
|
||||||
return iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_exit(int warm, int status)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
printk("CFE REBOOT\n");
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_FW_RESTART;
|
|
||||||
if (warm)
|
|
||||||
iocb.flags = CFE_FLG_WARMSTART;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_exitstat);
|
|
||||||
iocb.exitstat.status = status;
|
|
||||||
|
|
||||||
printk("CALL\n");
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
printk("DONE\n");
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_flushcache(int flags)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_FW_FLUSHCACHE;
|
|
||||||
iocb.flags = flags;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_getdevinfo(char *name)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_GETINFO;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_buf);
|
|
||||||
iocb.buffer.ptr = PTR_TO_CFE(name);
|
|
||||||
iocb.buffer.length = strlen(name);
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return iocb.status;
|
|
||||||
|
|
||||||
return iocb.buffer.devflags;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_getenv(char *name, char *dest, int destlen)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
dest[0] = '\0';
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_ENV_GET;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_envbuf);
|
|
||||||
iocb.envbuf.name = PTR_TO_CFE(name);
|
|
||||||
iocb.envbuf.name_len = strlen(name);
|
|
||||||
iocb.envbuf.val = PTR_TO_CFE(dest);
|
|
||||||
iocb.envbuf.val_len = destlen;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_getfwinfo(struct cfe_fwinfo *info)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_FW_GETINFO;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_fwinfo);
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return err;
|
|
||||||
|
|
||||||
info->version = iocb.fwinfo.version;
|
|
||||||
info->totalmem = iocb.fwinfo.totalmem;
|
|
||||||
info->flags = iocb.fwinfo.flags;
|
|
||||||
info->boardid = iocb.fwinfo.boardid;
|
|
||||||
info->bootarea_va = iocb.fwinfo.bootarea_va;
|
|
||||||
info->bootarea_pa = iocb.fwinfo.bootarea_pa;
|
|
||||||
info->bootarea_size = iocb.fwinfo.bootarea_size;
|
|
||||||
|
|
||||||
return iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_getstdhandle(int handletype)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_GETHANDLE;
|
|
||||||
iocb.flags = handletype;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return iocb.status;
|
|
||||||
|
|
||||||
return iocb.handle;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_getticks(s64 *ticks)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_FW_GETTIME;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_time);
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (!CFE_ISERR(iocb.status))
|
|
||||||
*ticks = iocb.time.ticks;
|
|
||||||
|
|
||||||
return iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_inpstat(int handle)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_INPSTAT;
|
|
||||||
iocb.handle = handle;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_inpstat);
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return iocb.status;
|
|
||||||
|
|
||||||
return iocb.inpstat.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_ioctl(int handle, unsigned int ioctlnum,
|
|
||||||
unsigned char *buffer, int length,
|
|
||||||
int *retlen, u64 offset)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_IOCTL;
|
|
||||||
iocb.handle = handle;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_buf);
|
|
||||||
iocb.buffer.offset = offset;
|
|
||||||
iocb.buffer.ioctlcmd = ioctlnum;
|
|
||||||
iocb.buffer.ptr = PTR_TO_CFE(buffer);
|
|
||||||
iocb.buffer.length = length;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return iocb.status;
|
|
||||||
if (retlen)
|
|
||||||
*retlen = iocb.buffer.retlen;
|
|
||||||
|
|
||||||
return iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_open(char *name)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_OPEN;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_buf);
|
|
||||||
iocb.buffer.ptr = PTR_TO_CFE(name);
|
|
||||||
iocb.buffer.length = strlen(name);
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return iocb.status;
|
|
||||||
|
|
||||||
return iocb.handle;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_read(int handle, unsigned char *buffer, int length)
|
|
||||||
{
|
|
||||||
return cfe_readblk(handle, 0, buffer, length);
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_READ;
|
|
||||||
iocb.handle = handle;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_buf);
|
|
||||||
iocb.buffer.offset = offset;
|
|
||||||
iocb.buffer.ptr = PTR_TO_CFE(buffer);
|
|
||||||
iocb.buffer.length = length;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return iocb.status;
|
|
||||||
|
|
||||||
return iocb.buffer.retlen;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_setenv(char *name, char *val)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_ENV_SET;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_envbuf);
|
|
||||||
iocb.envbuf.name = PTR_TO_CFE(name);
|
|
||||||
iocb.envbuf.name_len = strlen(name);
|
|
||||||
iocb.envbuf.val = PTR_TO_CFE(val);
|
|
||||||
iocb.envbuf.val_len = strlen(val);
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
|
|
||||||
return (CFE_ISERR(err)) ? err : iocb.status;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_write(int handle, unsigned char *buffer, int length)
|
|
||||||
{
|
|
||||||
return cfe_writeblk(handle, 0, buffer, length);
|
|
||||||
}
|
|
||||||
|
|
||||||
int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
|
|
||||||
{
|
|
||||||
struct cfe_iocb iocb;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
memset(&iocb, 0, sizeof(iocb));
|
|
||||||
iocb.fcode = CFE_CMD_DEV_WRITE;
|
|
||||||
iocb.handle = handle;
|
|
||||||
iocb.psize = sizeof(struct cfe_iocb_buf);
|
|
||||||
iocb.buffer.offset = offset;
|
|
||||||
iocb.buffer.ptr = PTR_TO_CFE(buffer);
|
|
||||||
iocb.buffer.length = length;
|
|
||||||
|
|
||||||
err = cfe_iocb_dispatch(&iocb);
|
|
||||||
if (CFE_ISERR(err))
|
|
||||||
return err;
|
|
||||||
if (CFE_ISERR(iocb.status))
|
|
||||||
return iocb.status;
|
|
||||||
|
|
||||||
return iocb.buffer.retlen;
|
|
||||||
}
|
|
||||||
@ -1,176 +0,0 @@
|
|||||||
/*
|
|
||||||
* Broadcom Common Firmware Environment (CFE) support
|
|
||||||
*
|
|
||||||
* Copyright 2000, 2001, 2002
|
|
||||||
* Broadcom Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2006 Michael Buesch
|
|
||||||
*
|
|
||||||
* Original Authors: Mitch Lichtenberg, Chris Demetriou
|
|
||||||
*
|
|
||||||
* This software is furnished under license and may be used and copied only
|
|
||||||
* in accordance with the following terms and conditions. Subject to these
|
|
||||||
* conditions, you may download, copy, install, use, modify and distribute
|
|
||||||
* modified or unmodified copies of this software in source and/or binary
|
|
||||||
* form. No title or ownership is transferred hereby.
|
|
||||||
*
|
|
||||||
* 1) Any source code used, modified or distributed must reproduce and
|
|
||||||
* retain this copyright notice and list of conditions as they appear in
|
|
||||||
* the source file.
|
|
||||||
*
|
|
||||||
* 2) No right is granted to use any trade name, trademark, or logo of
|
|
||||||
* Broadcom Corporation. The "Broadcom Corporation" name may not be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without the prior written permission of Broadcom Corporation.
|
|
||||||
*
|
|
||||||
* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
|
|
||||||
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
|
|
||||||
* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
|
|
||||||
* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
|
||||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
|
||||||
* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LINUX_CFE_PRIVATE_H_
|
|
||||||
#define LINUX_CFE_PRIVATE_H_
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
|
|
||||||
/* Seal indicating CFE's presence, passed to the kernel. */
|
|
||||||
#define CFE_EPTSEAL 0x43464531
|
|
||||||
|
|
||||||
#define CFE_CMD_FW_GETINFO 0
|
|
||||||
#define CFE_CMD_FW_RESTART 1
|
|
||||||
#define CFE_CMD_FW_BOOT 2
|
|
||||||
#define CFE_CMD_FW_CPUCTL 3
|
|
||||||
#define CFE_CMD_FW_GETTIME 4
|
|
||||||
#define CFE_CMD_FW_MEMENUM 5
|
|
||||||
#define CFE_CMD_FW_FLUSHCACHE 6
|
|
||||||
|
|
||||||
#define CFE_CMD_DEV_GETHANDLE 9
|
|
||||||
#define CFE_CMD_DEV_ENUM 10
|
|
||||||
#define CFE_CMD_DEV_OPEN 11
|
|
||||||
#define CFE_CMD_DEV_INPSTAT 12
|
|
||||||
#define CFE_CMD_DEV_READ 13
|
|
||||||
#define CFE_CMD_DEV_WRITE 14
|
|
||||||
#define CFE_CMD_DEV_IOCTL 15
|
|
||||||
#define CFE_CMD_DEV_CLOSE 16
|
|
||||||
#define CFE_CMD_DEV_GETINFO 17
|
|
||||||
|
|
||||||
#define CFE_CMD_ENV_ENUM 20
|
|
||||||
#define CFE_CMD_ENV_GET 22
|
|
||||||
#define CFE_CMD_ENV_SET 23
|
|
||||||
#define CFE_CMD_ENV_DEL 24
|
|
||||||
|
|
||||||
#define CFE_CMD_MAX 32
|
|
||||||
|
|
||||||
#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
|
|
||||||
|
|
||||||
typedef u64 cfe_uint_t;
|
|
||||||
typedef s64 cfe_int_t;
|
|
||||||
typedef s64 cfe_ptr_t;
|
|
||||||
|
|
||||||
/* Cast a pointer from native to CFE-API pointer and back */
|
|
||||||
#define CFE_TO_PTR(p) ((void *)(unsigned long)(p))
|
|
||||||
#define PTR_TO_CFE(p) ((cfe_ptr_t)(unsigned long)(p))
|
|
||||||
|
|
||||||
struct cfe_iocb_buf {
|
|
||||||
cfe_uint_t offset; /* offset on device (bytes) */
|
|
||||||
cfe_ptr_t ptr; /* pointer to a buffer */
|
|
||||||
cfe_uint_t length; /* length of this buffer */
|
|
||||||
cfe_uint_t retlen; /* returned length (for read ops) */
|
|
||||||
union {
|
|
||||||
cfe_uint_t ioctlcmd; /* IOCTL command (used only for IOCTLs) */
|
|
||||||
cfe_uint_t devflags; /* Returned device info flags */
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
struct cfe_iocb_inpstat {
|
|
||||||
cfe_uint_t status; /* 1 means input available */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct cfe_iocb_envbuf {
|
|
||||||
cfe_int_t index; /* 0-based enumeration index */
|
|
||||||
cfe_ptr_t name; /* name string buffer */
|
|
||||||
cfe_int_t name_len; /* size of name buffer */
|
|
||||||
cfe_ptr_t val; /* value string buffer */
|
|
||||||
cfe_int_t val_len; /* size of value string buffer */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct cfe_iocb_cpuctl {
|
|
||||||
cfe_uint_t number; /* cpu number to control */
|
|
||||||
cfe_uint_t command; /* command to issue to CPU */
|
|
||||||
cfe_uint_t start_addr; /* CPU start address */
|
|
||||||
cfe_uint_t gp; /* starting GP value */
|
|
||||||
cfe_uint_t sp; /* starting SP value */
|
|
||||||
cfe_uint_t a1; /* starting A1 value */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct cfe_iocb_time {
|
|
||||||
cfe_int_t ticks; /* current time in ticks */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct cfe_iocb_exitstat {
|
|
||||||
cfe_int_t status;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct cfe_iocb_meminfo {
|
|
||||||
cfe_int_t index; /* 0-based enumeration index */
|
|
||||||
cfe_int_t type; /* type of memory block */
|
|
||||||
cfe_uint_t addr; /* physical start address */
|
|
||||||
cfe_uint_t size; /* block size */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct cfe_iocb_fwinfo {
|
|
||||||
cfe_int_t version; /* major, minor, eco version */
|
|
||||||
cfe_int_t totalmem; /* total installed mem */
|
|
||||||
cfe_int_t flags; /* various flags */
|
|
||||||
cfe_int_t boardid; /* board ID */
|
|
||||||
cfe_int_t bootarea_va; /* VA of boot area */
|
|
||||||
cfe_int_t bootarea_pa; /* PA of boot area */
|
|
||||||
cfe_int_t bootarea_size; /* size of boot area */
|
|
||||||
cfe_int_t reserved1;
|
|
||||||
cfe_int_t reserved2;
|
|
||||||
cfe_int_t reserved3;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* CFE I/O Control Block */
|
|
||||||
struct cfe_iocb {
|
|
||||||
cfe_uint_t fcode; /* IOCB function code */
|
|
||||||
cfe_int_t status; /* return status */
|
|
||||||
cfe_int_t handle; /* file/device handle */
|
|
||||||
cfe_uint_t flags; /* flags for this IOCB */
|
|
||||||
cfe_uint_t psize; /* size of parameter list */
|
|
||||||
union {
|
|
||||||
struct cfe_iocb_buf buffer; /* buffer parameters */
|
|
||||||
struct cfe_iocb_inpstat inpstat; /* input status parameters */
|
|
||||||
struct cfe_iocb_envbuf envbuf; /* environment function parameters */
|
|
||||||
struct cfe_iocb_cpuctl cpuctl; /* CPU control parameters */
|
|
||||||
struct cfe_iocb_time time; /* timer parameters */
|
|
||||||
struct cfe_iocb_meminfo meminfo; /* memory arena info parameters */
|
|
||||||
struct cfe_iocb_fwinfo fwinfo; /* firmware information */
|
|
||||||
struct cfe_iocb_exitstat exitstat; /* Exit Status */
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
|
|
||||||
void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
|
|
||||||
unsigned long fwarg2, unsigned long fwarg3);
|
|
||||||
|
|
||||||
#else /* __ASSEMBLY__ */
|
|
||||||
|
|
||||||
.macro cfe_early_init
|
|
||||||
#ifdef CONFIG_CFE
|
|
||||||
jal cfe_setup
|
|
||||||
#endif
|
|
||||||
.endm
|
|
||||||
|
|
||||||
#endif /* __ASSEMBLY__ */
|
|
||||||
#endif /* LINUX_CFE_PRIVATE_H_ */
|
|
||||||
@ -1,439 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
|
||||||
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
|
|
||||||
* Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
|
|
||||||
*
|
|
||||||
* original functions for finding root filesystem from Mike Baker
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
|
||||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along
|
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
||||||
*
|
|
||||||
* Copyright 2001-2003, Broadcom Corporation
|
|
||||||
* All Rights Reserved.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
|
||||||
* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
|
||||||
* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
|
||||||
* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
|
||||||
*
|
|
||||||
* Flash mapping for BCM947XX boards
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/sched.h>
|
|
||||||
#include <linux/wait.h>
|
|
||||||
#include <linux/mtd/mtd.h>
|
|
||||||
#include <linux/mtd/map.h>
|
|
||||||
#ifdef CONFIG_MTD_PARTITIONS
|
|
||||||
#include <linux/mtd/partitions.h>
|
|
||||||
#endif
|
|
||||||
#include <linux/crc32.h>
|
|
||||||
#ifdef CONFIG_SSB
|
|
||||||
#include <linux/ssb/ssb.h>
|
|
||||||
#endif
|
|
||||||
#include <asm/io.h>
|
|
||||||
|
|
||||||
|
|
||||||
#define TRX_MAGIC 0x30524448 /* "HDR0" */
|
|
||||||
#define TRX_VERSION 1
|
|
||||||
#define TRX_MAX_LEN 0x3A0000
|
|
||||||
#define TRX_NO_HEADER 1 /* Do not write TRX header */
|
|
||||||
#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
|
|
||||||
#define TRX_MAX_OFFSET 3
|
|
||||||
|
|
||||||
struct trx_header {
|
|
||||||
u32 magic; /* "HDR0" */
|
|
||||||
u32 len; /* Length of file including header */
|
|
||||||
u32 crc32; /* 32-bit CRC from flag_version to end of file */
|
|
||||||
u32 flag_version; /* 0:15 flags, 16:31 version */
|
|
||||||
u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
|
|
||||||
};
|
|
||||||
|
|
||||||
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
|
|
||||||
#define NVRAM_SPACE 0x8000
|
|
||||||
#define WINDOW_ADDR 0x1fc00000
|
|
||||||
#define WINDOW_SIZE 0x400000
|
|
||||||
#define BUSWIDTH 2
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB
|
|
||||||
extern struct ssb_bus ssb;
|
|
||||||
#endif
|
|
||||||
static struct mtd_info *bcm947xx_mtd;
|
|
||||||
|
|
||||||
static void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
|
|
||||||
{
|
|
||||||
if (len==1) {
|
|
||||||
memcpy_fromio(to, map->virt + from, len);
|
|
||||||
} else {
|
|
||||||
int i;
|
|
||||||
u16 *dest = (u16 *) to;
|
|
||||||
u16 *src = (u16 *) (map->virt + from);
|
|
||||||
for (i = 0; i < (len / 2); i++) {
|
|
||||||
dest[i] = src[i];
|
|
||||||
}
|
|
||||||
if (len & 1)
|
|
||||||
*((u8 *)dest+len-1) = src[i] & 0xff;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct map_info bcm947xx_map = {
|
|
||||||
name: "Physically mapped flash",
|
|
||||||
size: WINDOW_SIZE,
|
|
||||||
bankwidth: BUSWIDTH,
|
|
||||||
phys: WINDOW_ADDR,
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef CONFIG_MTD_PARTITIONS
|
|
||||||
|
|
||||||
static struct mtd_partition bcm947xx_parts[] = {
|
|
||||||
{ name: "cfe", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
|
|
||||||
{ name: "linux", offset: 0, size: 0, },
|
|
||||||
{ name: "rootfs", offset: 0, size: 0, },
|
|
||||||
{ name: "nvram", offset: 0, size: 0, },
|
|
||||||
{ name: NULL, },
|
|
||||||
};
|
|
||||||
|
|
||||||
static int __init
|
|
||||||
find_cfe_size(struct mtd_info *mtd, size_t size)
|
|
||||||
{
|
|
||||||
struct trx_header *trx;
|
|
||||||
unsigned char buf[512];
|
|
||||||
int off;
|
|
||||||
size_t len;
|
|
||||||
int blocksize;
|
|
||||||
|
|
||||||
trx = (struct trx_header *) buf;
|
|
||||||
|
|
||||||
blocksize = mtd->erasesize;
|
|
||||||
if (blocksize < 0x10000)
|
|
||||||
blocksize = 0x10000;
|
|
||||||
|
|
||||||
for (off = (128*1024); off < size; off += blocksize) {
|
|
||||||
memset(buf, 0xe5, sizeof(buf));
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Read into buffer
|
|
||||||
*/
|
|
||||||
if (mtd->read(mtd, off, sizeof(buf), &len, buf) ||
|
|
||||||
len != sizeof(buf))
|
|
||||||
continue;
|
|
||||||
|
|
||||||
/* found a TRX header */
|
|
||||||
if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
|
|
||||||
goto found;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
printk(KERN_NOTICE
|
|
||||||
"%s: Couldn't find bootloader size\n",
|
|
||||||
mtd->name);
|
|
||||||
return -1;
|
|
||||||
|
|
||||||
found:
|
|
||||||
printk(KERN_NOTICE "bootloader size: %d\n", off);
|
|
||||||
return off;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Copied from mtdblock.c
|
|
||||||
*
|
|
||||||
* Cache stuff...
|
|
||||||
*
|
|
||||||
* Since typical flash erasable sectors are much larger than what Linux's
|
|
||||||
* buffer cache can handle, we must implement read-modify-write on flash
|
|
||||||
* sectors for each block write requests. To avoid over-erasing flash sectors
|
|
||||||
* and to speed things up, we locally cache a whole flash sector while it is
|
|
||||||
* being written to until a different sector is required.
|
|
||||||
*/
|
|
||||||
|
|
||||||
static void erase_callback(struct erase_info *done)
|
|
||||||
{
|
|
||||||
wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
|
|
||||||
wake_up(wait_q);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int erase_write (struct mtd_info *mtd, unsigned long pos,
|
|
||||||
int len, const char *buf)
|
|
||||||
{
|
|
||||||
struct erase_info erase;
|
|
||||||
DECLARE_WAITQUEUE(wait, current);
|
|
||||||
wait_queue_head_t wait_q;
|
|
||||||
size_t retlen;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* First, let's erase the flash block.
|
|
||||||
*/
|
|
||||||
|
|
||||||
init_waitqueue_head(&wait_q);
|
|
||||||
erase.mtd = mtd;
|
|
||||||
erase.callback = erase_callback;
|
|
||||||
erase.addr = pos;
|
|
||||||
erase.len = len;
|
|
||||||
erase.priv = (u_long)&wait_q;
|
|
||||||
|
|
||||||
set_current_state(TASK_INTERRUPTIBLE);
|
|
||||||
add_wait_queue(&wait_q, &wait);
|
|
||||||
|
|
||||||
ret = mtd->erase(mtd, &erase);
|
|
||||||
if (ret) {
|
|
||||||
set_current_state(TASK_RUNNING);
|
|
||||||
remove_wait_queue(&wait_q, &wait);
|
|
||||||
printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
|
|
||||||
"on \"%s\" failed\n",
|
|
||||||
pos, len, mtd->name);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
schedule(); /* Wait for erase to finish. */
|
|
||||||
remove_wait_queue(&wait_q, &wait);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Next, writhe data to flash.
|
|
||||||
*/
|
|
||||||
|
|
||||||
ret = mtd->write (mtd, pos, len, &retlen, buf);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
if (retlen != len)
|
|
||||||
return -EIO;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
static int __init
|
|
||||||
find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
|
|
||||||
{
|
|
||||||
struct trx_header trx, *trx2;
|
|
||||||
unsigned char buf[512], *block;
|
|
||||||
int off, blocksize;
|
|
||||||
u32 i, crc = ~0;
|
|
||||||
size_t len;
|
|
||||||
struct squashfs_super_block *sb = (struct squashfs_super_block *) buf;
|
|
||||||
|
|
||||||
blocksize = mtd->erasesize;
|
|
||||||
if (blocksize < 0x10000)
|
|
||||||
blocksize = 0x10000;
|
|
||||||
|
|
||||||
for (off = (128*1024); off < size; off += blocksize) {
|
|
||||||
memset(&trx, 0xe5, sizeof(trx));
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Read into buffer
|
|
||||||
*/
|
|
||||||
if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
|
|
||||||
len != sizeof(trx))
|
|
||||||
continue;
|
|
||||||
|
|
||||||
/* found a TRX header */
|
|
||||||
if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
|
|
||||||
part->offset = le32_to_cpu(trx.offsets[2]) ? :
|
|
||||||
le32_to_cpu(trx.offsets[1]);
|
|
||||||
part->size = le32_to_cpu(trx.len);
|
|
||||||
|
|
||||||
part->size -= part->offset;
|
|
||||||
part->offset += off;
|
|
||||||
|
|
||||||
goto found;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
printk(KERN_NOTICE
|
|
||||||
"%s: Couldn't find root filesystem\n",
|
|
||||||
mtd->name);
|
|
||||||
return -1;
|
|
||||||
|
|
||||||
found:
|
|
||||||
if (part->size == 0)
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
if (mtd->read(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
/* Move the fs outside of the trx */
|
|
||||||
part->size = 0;
|
|
||||||
|
|
||||||
if (trx.len != part->offset + part->size - off) {
|
|
||||||
/* Update the trx offsets and length */
|
|
||||||
trx.len = part->offset + part->size - off;
|
|
||||||
|
|
||||||
/* Update the trx crc32 */
|
|
||||||
for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
|
|
||||||
if (mtd->read(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
|
|
||||||
return 0;
|
|
||||||
crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
|
|
||||||
}
|
|
||||||
trx.crc32 = crc;
|
|
||||||
|
|
||||||
/* read first eraseblock from the trx */
|
|
||||||
block = kmalloc(mtd->erasesize, GFP_KERNEL);
|
|
||||||
trx2 = (struct trx_header *) block;
|
|
||||||
if (mtd->read(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
|
|
||||||
printk("Error accessing the first trx eraseblock\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
printk("Updating TRX offsets and length:\n");
|
|
||||||
printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
|
|
||||||
printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx.offsets[0], trx.offsets[1], trx.offsets[2], trx.len, trx.crc32);
|
|
||||||
|
|
||||||
/* Write updated trx header to the flash */
|
|
||||||
memcpy(block, &trx, sizeof(trx));
|
|
||||||
if (mtd->unlock)
|
|
||||||
mtd->unlock(mtd, off, mtd->erasesize);
|
|
||||||
erase_write(mtd, off, mtd->erasesize, block);
|
|
||||||
if (mtd->sync)
|
|
||||||
mtd->sync(mtd);
|
|
||||||
kfree(block);
|
|
||||||
printk("Done\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
return part->size;
|
|
||||||
}
|
|
||||||
|
|
||||||
struct mtd_partition * __init
|
|
||||||
init_mtd_partitions(struct mtd_info *mtd, size_t size)
|
|
||||||
{
|
|
||||||
int cfe_size;
|
|
||||||
|
|
||||||
if ((cfe_size = find_cfe_size(mtd,size)) < 0)
|
|
||||||
return NULL;
|
|
||||||
|
|
||||||
/* boot loader */
|
|
||||||
bcm947xx_parts[0].offset = 0;
|
|
||||||
bcm947xx_parts[0].size = cfe_size;
|
|
||||||
|
|
||||||
/* nvram */
|
|
||||||
if (cfe_size != 384 * 1024) {
|
|
||||||
bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
|
||||||
bcm947xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
|
||||||
} else {
|
|
||||||
/* nvram (old 128kb config partition on netgear wgt634u) */
|
|
||||||
bcm947xx_parts[3].offset = bcm947xx_parts[0].size;
|
|
||||||
bcm947xx_parts[3].size = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* linux (kernel and rootfs) */
|
|
||||||
if (cfe_size != 384 * 1024) {
|
|
||||||
bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
|
|
||||||
bcm947xx_parts[1].size = bcm947xx_parts[3].offset -
|
|
||||||
bcm947xx_parts[1].offset;
|
|
||||||
} else {
|
|
||||||
/* do not count the elf loader, which is on one block */
|
|
||||||
bcm947xx_parts[1].offset = bcm947xx_parts[0].size +
|
|
||||||
bcm947xx_parts[3].size + mtd->erasesize;
|
|
||||||
bcm947xx_parts[1].size = size -
|
|
||||||
bcm947xx_parts[0].size -
|
|
||||||
(2*bcm947xx_parts[3].size) -
|
|
||||||
mtd->erasesize;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* find and size rootfs */
|
|
||||||
find_root(mtd,size,&bcm947xx_parts[2]);
|
|
||||||
bcm947xx_parts[2].size = size - bcm947xx_parts[2].offset - bcm947xx_parts[3].size;
|
|
||||||
|
|
||||||
return bcm947xx_parts;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
int __init init_bcm947xx_map(void)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_SSB
|
|
||||||
struct ssb_mipscore *mcore = &ssb.mipscore;
|
|
||||||
#endif
|
|
||||||
size_t size;
|
|
||||||
int ret = 0;
|
|
||||||
#ifdef CONFIG_MTD_PARTITIONS
|
|
||||||
struct mtd_partition *parts;
|
|
||||||
int i;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB
|
|
||||||
u32 window = mcore->flash_window;
|
|
||||||
u32 window_size = mcore->flash_window_size;
|
|
||||||
|
|
||||||
printk("flash init: 0x%08x 0x%08x\n", window, window_size);
|
|
||||||
bcm947xx_map.phys = window;
|
|
||||||
bcm947xx_map.size = window_size;
|
|
||||||
bcm947xx_map.virt = ioremap_nocache(window, window_size);
|
|
||||||
#else
|
|
||||||
printk("flash init: 0x%08x 0x%08x\n", WINDOW_ADDR, WINDOW_SIZE);
|
|
||||||
bcm947xx_map.virt = ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (!bcm947xx_map.virt) {
|
|
||||||
printk("Failed to ioremap\n");
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
simple_map_init(&bcm947xx_map);
|
|
||||||
|
|
||||||
if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
|
|
||||||
printk("Failed to do_map_probe\n");
|
|
||||||
iounmap((void *)bcm947xx_map.virt);
|
|
||||||
return -ENXIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* override copy_from routine */
|
|
||||||
bcm947xx_map.copy_from = bcm947xx_map_copy_from;
|
|
||||||
|
|
||||||
bcm947xx_mtd->owner = THIS_MODULE;
|
|
||||||
|
|
||||||
size = bcm947xx_mtd->size;
|
|
||||||
|
|
||||||
printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
|
|
||||||
|
|
||||||
#ifdef CONFIG_MTD_PARTITIONS
|
|
||||||
parts = init_mtd_partitions(bcm947xx_mtd, size);
|
|
||||||
for (i = 0; parts[i].name; i++);
|
|
||||||
ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
|
|
||||||
if (ret) {
|
|
||||||
printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
|
|
||||||
goto fail;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
fail:
|
|
||||||
if (bcm947xx_mtd)
|
|
||||||
map_destroy(bcm947xx_mtd);
|
|
||||||
if (bcm947xx_map.virt)
|
|
||||||
iounmap((void *)bcm947xx_map.virt);
|
|
||||||
bcm947xx_map.virt = 0;
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
void __exit cleanup_bcm947xx_map(void)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_MTD_PARTITIONS
|
|
||||||
del_mtd_partitions(bcm947xx_mtd);
|
|
||||||
#endif
|
|
||||||
map_destroy(bcm947xx_mtd);
|
|
||||||
iounmap((void *)bcm947xx_map.virt);
|
|
||||||
}
|
|
||||||
|
|
||||||
module_init(init_bcm947xx_map);
|
|
||||||
module_exit(cleanup_bcm947xx_map);
|
|
||||||
@ -1,189 +0,0 @@
|
|||||||
/*
|
|
||||||
* Broadcom Common Firmware Environment (CFE) support
|
|
||||||
*
|
|
||||||
* Copyright 2000, 2001, 2002
|
|
||||||
* Broadcom Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2006 Michael Buesch
|
|
||||||
*
|
|
||||||
* Original Authors: Mitch Lichtenberg, Chris Demetriou
|
|
||||||
*
|
|
||||||
* This software is furnished under license and may be used and copied only
|
|
||||||
* in accordance with the following terms and conditions. Subject to these
|
|
||||||
* conditions, you may download, copy, install, use, modify and distribute
|
|
||||||
* modified or unmodified copies of this software in source and/or binary
|
|
||||||
* form. No title or ownership is transferred hereby.
|
|
||||||
*
|
|
||||||
* 1) Any source code used, modified or distributed must reproduce and
|
|
||||||
* retain this copyright notice and list of conditions as they appear in
|
|
||||||
* the source file.
|
|
||||||
*
|
|
||||||
* 2) No right is granted to use any trade name, trademark, or logo of
|
|
||||||
* Broadcom Corporation. The "Broadcom Corporation" name may not be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without the prior written permission of Broadcom Corporation.
|
|
||||||
*
|
|
||||||
* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
|
|
||||||
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
|
|
||||||
* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
|
|
||||||
* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
|
||||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
||||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
|
||||||
* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LINUX_CFE_API_H_
|
|
||||||
#define LINUX_CFE_API_H_
|
|
||||||
|
|
||||||
#include <linux/types.h>
|
|
||||||
|
|
||||||
|
|
||||||
#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
|
|
||||||
#define CFE_MI_AVAILABLE 1 /* memory is available */
|
|
||||||
|
|
||||||
#define CFE_FLG_WARMSTART 0x00000001
|
|
||||||
#define CFE_FLG_FULL_ARENA 0x00000001
|
|
||||||
#define CFE_FLG_ENV_PERMANENT 0x00000001
|
|
||||||
|
|
||||||
#define CFE_CPU_CMD_START 1
|
|
||||||
#define CFE_CPU_CMD_STOP 0
|
|
||||||
|
|
||||||
#define CFE_STDHANDLE_CONSOLE 0
|
|
||||||
|
|
||||||
#define CFE_DEV_NETWORK 1
|
|
||||||
#define CFE_DEV_DISK 2
|
|
||||||
#define CFE_DEV_FLASH 3
|
|
||||||
#define CFE_DEV_SERIAL 4
|
|
||||||
#define CFE_DEV_CPU 5
|
|
||||||
#define CFE_DEV_NVRAM 6
|
|
||||||
#define CFE_DEV_CLOCK 7
|
|
||||||
#define CFE_DEV_OTHER 8
|
|
||||||
#define CFE_DEV_MASK 0x0F
|
|
||||||
|
|
||||||
#define CFE_CACHE_FLUSH_D 1
|
|
||||||
#define CFE_CACHE_INVAL_I 2
|
|
||||||
#define CFE_CACHE_INVAL_D 4
|
|
||||||
#define CFE_CACHE_INVAL_L2 8
|
|
||||||
|
|
||||||
#define CFE_FWI_64BIT 0x00000001
|
|
||||||
#define CFE_FWI_32BIT 0x00000002
|
|
||||||
#define CFE_FWI_RELOC 0x00000004
|
|
||||||
#define CFE_FWI_UNCACHED 0x00000008
|
|
||||||
#define CFE_FWI_MULTICPU 0x00000010
|
|
||||||
#define CFE_FWI_FUNCSIM 0x00000020
|
|
||||||
#define CFE_FWI_RTLSIM 0x00000040
|
|
||||||
|
|
||||||
struct cfe_fwinfo {
|
|
||||||
s64 version; /* major, minor, eco version */
|
|
||||||
s64 totalmem; /* total installed mem */
|
|
||||||
s64 flags; /* various flags */
|
|
||||||
s64 boardid; /* board ID */
|
|
||||||
s64 bootarea_va; /* VA of boot area */
|
|
||||||
s64 bootarea_pa; /* PA of boot area */
|
|
||||||
s64 bootarea_size; /* size of boot area */
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/* The public CFE API */
|
|
||||||
|
|
||||||
int cfe_present(void); /* Check if we booted from CFE. Returns bool */
|
|
||||||
|
|
||||||
int cfe_getticks(s64 *ticks);
|
|
||||||
int cfe_close(int handle);
|
|
||||||
int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1);
|
|
||||||
int cfe_cpu_stop(int cpu);
|
|
||||||
int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
|
|
||||||
int cfe_enumdev(int idx, char *name, int namelen);
|
|
||||||
int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
|
|
||||||
u64 *type);
|
|
||||||
int cfe_exit(int warm, int status);
|
|
||||||
int cfe_flushcache(int flags);
|
|
||||||
int cfe_getdevinfo(char *name);
|
|
||||||
int cfe_getenv(char *name, char *dest, int destlen);
|
|
||||||
int cfe_getfwinfo(struct cfe_fwinfo *info);
|
|
||||||
int cfe_getstdhandle(int handletype);
|
|
||||||
int cfe_inpstat(int handle);
|
|
||||||
int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
|
|
||||||
int length, int *retlen, u64 offset);
|
|
||||||
int cfe_open(char *name);
|
|
||||||
int cfe_read(int handle, unsigned char *buffer, int length);
|
|
||||||
int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length);
|
|
||||||
int cfe_setenv(char *name, char *val);
|
|
||||||
int cfe_write(int handle, unsigned char *buffer, int length);
|
|
||||||
int cfe_writeblk(int handle, s64 offset, unsigned char *buffer,
|
|
||||||
int length);
|
|
||||||
|
|
||||||
|
|
||||||
/* High level API */
|
|
||||||
|
|
||||||
/* Print some information to CFE's console (most likely serial line) */
|
|
||||||
int cfe_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
|
|
||||||
int cfe_vprintk(const char *fmt, va_list args);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* Error codes returned by the low API functions */
|
|
||||||
|
|
||||||
#define CFE_ISERR(errcode) (errcode < 0)
|
|
||||||
|
|
||||||
#define CFE_OK 0
|
|
||||||
#define CFE_ERR -1 /* generic error */
|
|
||||||
#define CFE_ERR_INV_COMMAND -2
|
|
||||||
#define CFE_ERR_EOF -3
|
|
||||||
#define CFE_ERR_IOERR -4
|
|
||||||
#define CFE_ERR_NOMEM -5
|
|
||||||
#define CFE_ERR_DEVNOTFOUND -6
|
|
||||||
#define CFE_ERR_DEVOPEN -7
|
|
||||||
#define CFE_ERR_INV_PARAM -8
|
|
||||||
#define CFE_ERR_ENVNOTFOUND -9
|
|
||||||
#define CFE_ERR_ENVREADONLY -10
|
|
||||||
|
|
||||||
#define CFE_ERR_NOTELF -11
|
|
||||||
#define CFE_ERR_NOT32BIT -12
|
|
||||||
#define CFE_ERR_WRONGENDIAN -13
|
|
||||||
#define CFE_ERR_BADELFVERS -14
|
|
||||||
#define CFE_ERR_NOTMIPS -15
|
|
||||||
#define CFE_ERR_BADELFFMT -16
|
|
||||||
#define CFE_ERR_BADADDR -17
|
|
||||||
|
|
||||||
#define CFE_ERR_FILENOTFOUND -18
|
|
||||||
#define CFE_ERR_UNSUPPORTED -19
|
|
||||||
|
|
||||||
#define CFE_ERR_HOSTUNKNOWN -20
|
|
||||||
|
|
||||||
#define CFE_ERR_TIMEOUT -21
|
|
||||||
|
|
||||||
#define CFE_ERR_PROTOCOLERR -22
|
|
||||||
|
|
||||||
#define CFE_ERR_NETDOWN -23
|
|
||||||
#define CFE_ERR_NONAMESERVER -24
|
|
||||||
|
|
||||||
#define CFE_ERR_NOHANDLES -25
|
|
||||||
#define CFE_ERR_ALREADYBOUND -26
|
|
||||||
|
|
||||||
#define CFE_ERR_CANNOTSET -27
|
|
||||||
#define CFE_ERR_NOMORE -28
|
|
||||||
#define CFE_ERR_BADFILESYS -29
|
|
||||||
#define CFE_ERR_FSNOTAVAIL -30
|
|
||||||
|
|
||||||
#define CFE_ERR_INVBOOTBLOCK -31
|
|
||||||
#define CFE_ERR_WRONGDEVTYPE -32
|
|
||||||
#define CFE_ERR_BBCHECKSUM -33
|
|
||||||
#define CFE_ERR_BOOTPROGCHKSUM -34
|
|
||||||
|
|
||||||
#define CFE_ERR_LDRNOTAVAIL -35
|
|
||||||
|
|
||||||
#define CFE_ERR_NOTREADY -36
|
|
||||||
|
|
||||||
#define CFE_ERR_GETMEM -37
|
|
||||||
#define CFE_ERR_SETMEM -38
|
|
||||||
|
|
||||||
#define CFE_ERR_NOTCONN -39
|
|
||||||
#define CFE_ERR_ADDRINUSE -40
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* LINUX_CFE_API_H_ */
|
|
||||||
@ -1,67 +0,0 @@
|
|||||||
#ifndef __BCM947XX_GPIO_H
|
|
||||||
#define __BCM947XX_GPIO_H
|
|
||||||
|
|
||||||
#include <linux/ssb/ssb_embedded.h>
|
|
||||||
|
|
||||||
extern struct ssb_bus ssb;
|
|
||||||
|
|
||||||
static inline int gpio_request(unsigned gpio, const char *label)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void gpio_free(unsigned gpio)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_direction_input(unsigned gpio)
|
|
||||||
{
|
|
||||||
ssb_gpio_outen(&ssb, 1 << gpio, 0);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_direction_output(unsigned gpio, int value)
|
|
||||||
{
|
|
||||||
ssb_gpio_out(&ssb, 1 << gpio, (value ? 1 << gpio : 0));
|
|
||||||
ssb_gpio_outen(&ssb, 1 << gpio, 1 << gpio);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static inline int gpio_to_irq(unsigned gpio)
|
|
||||||
{
|
|
||||||
struct ssb_device *dev;
|
|
||||||
|
|
||||||
dev = ssb.chipco.dev;
|
|
||||||
if (!dev)
|
|
||||||
dev = ssb.extif.dev;
|
|
||||||
if (!dev)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
return ssb_mips_irq(dev) + 2;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int irq_to_gpio(unsigned gpio)
|
|
||||||
{
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static inline int gpio_get_value(unsigned gpio)
|
|
||||||
{
|
|
||||||
return !!ssb_gpio_in(&ssb, 1 << gpio);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_set_value(unsigned gpio, int value)
|
|
||||||
{
|
|
||||||
ssb_gpio_out(&ssb, 1 << gpio, (value ? 1 << gpio : 0));
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/* cansleep wrappers */
|
|
||||||
#include <asm-generic/gpio.h>
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* __BCM947XX_GPIO_H */
|
|
||||||
|
|
||||||
@ -1,26 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
|
||||||
* for more details.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2005 Embedded Alley Solutions, Inc
|
|
||||||
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
|
|
||||||
* Copyright (C) 2006 Michael Buesch
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
|
|
||||||
#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
|
|
||||||
|
|
||||||
/* Intentionally empty macro, used in head.S. Override in
|
|
||||||
* arch/mips/mach-xxx/kernel-entry-init.h when necessary.
|
|
||||||
*/
|
|
||||||
.macro kernel_entry_setup
|
|
||||||
.endm
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Do SMP slave processor setup necessary before we can savely execute C code.
|
|
||||||
*/
|
|
||||||
.macro smp_slave_setup
|
|
||||||
.endm
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
|
|
||||||
@ -1,152 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_chipcommon.c
|
|
||||||
+++ b/drivers/ssb/driver_chipcommon.c
|
|
||||||
@@ -39,12 +39,14 @@
|
|
||||||
ssb_write32(cc->dev, offset, value);
|
|
||||||
}
|
|
||||||
|
|
||||||
-static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
|
|
||||||
- u32 mask, u32 value)
|
|
||||||
+static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
|
|
||||||
+ u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
value &= mask;
|
|
||||||
value |= chipco_read32(cc, offset) & ~mask;
|
|
||||||
chipco_write32(cc, offset, value);
|
|
||||||
+
|
|
||||||
+ return value;
|
|
||||||
}
|
|
||||||
|
|
||||||
void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
|
|
||||||
@@ -355,16 +357,37 @@
|
|
||||||
{
|
|
||||||
return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
|
|
||||||
}
|
|
||||||
+EXPORT_SYMBOL(ssb_chipco_gpio_in);
|
|
||||||
+
|
|
||||||
+u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_chipco_gpio_out);
|
|
||||||
+
|
|
||||||
+u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_chipco_gpio_outen);
|
|
||||||
+
|
|
||||||
+u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_chipco_gpio_control);
|
|
||||||
|
|
||||||
-void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
+u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
- chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
|
|
||||||
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
|
|
||||||
}
|
|
||||||
+EXPORT_SYMBOL(ssb_chipco_gpio_intmask);
|
|
||||||
|
|
||||||
-void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
+u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
- chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
|
|
||||||
+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
|
|
||||||
}
|
|
||||||
+EXPORT_SYMBOL(ssb_chipco_gpio_polarity);
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB_SERIAL
|
|
||||||
int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
|
|
||||||
--- a/drivers/ssb/driver_extif.c
|
|
||||||
+++ b/drivers/ssb/driver_extif.c
|
|
||||||
@@ -27,12 +27,14 @@
|
|
||||||
ssb_write32(extif->dev, offset, value);
|
|
||||||
}
|
|
||||||
|
|
||||||
-static inline void extif_write32_masked(struct ssb_extif *extif, u16 offset,
|
|
||||||
- u32 mask, u32 value)
|
|
||||||
+static inline u32 extif_write32_masked(struct ssb_extif *extif, u16 offset,
|
|
||||||
+ u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
value &= mask;
|
|
||||||
value |= extif_read32(extif, offset) & ~mask;
|
|
||||||
extif_write32(extif, offset, value);
|
|
||||||
+
|
|
||||||
+ return value;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB_SERIAL
|
|
||||||
@@ -114,16 +116,30 @@
|
|
||||||
{
|
|
||||||
return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask;
|
|
||||||
}
|
|
||||||
+EXPORT_SYMBOL(ssb_extif_gpio_in);
|
|
||||||
|
|
||||||
-void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
+u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
|
|
||||||
mask, value);
|
|
||||||
}
|
|
||||||
+EXPORT_SYMBOL(ssb_extif_gpio_out);
|
|
||||||
|
|
||||||
-void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
+u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
|
|
||||||
mask, value);
|
|
||||||
}
|
|
||||||
+EXPORT_SYMBOL(ssb_extif_gpio_outen);
|
|
||||||
+
|
|
||||||
+u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_extif_gpio_polarity);
|
|
||||||
|
|
||||||
+u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_extif_gpio_intmask);
|
|
||||||
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
|
||||||
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
|
||||||
@@ -382,11 +382,13 @@
|
|
||||||
extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
|
|
||||||
u32 ticks);
|
|
||||||
|
|
||||||
+/* Chipcommon GPIO pin access. */
|
|
||||||
u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
|
|
||||||
-
|
|
||||||
-void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
||||||
-
|
|
||||||
-void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
||||||
+u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
||||||
+u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
||||||
+u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
||||||
+u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
||||||
+u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB_SERIAL
|
|
||||||
extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
|
|
||||||
--- a/include/linux/ssb/ssb_driver_extif.h
|
|
||||||
+++ b/include/linux/ssb/ssb_driver_extif.h
|
|
||||||
@@ -171,11 +171,12 @@
|
|
||||||
extern void ssb_extif_timing_init(struct ssb_extif *extif,
|
|
||||||
unsigned long ns);
|
|
||||||
|
|
||||||
+/* Extif GPIO pin access */
|
|
||||||
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
|
|
||||||
-
|
|
||||||
-void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
-
|
|
||||||
-void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
+u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
+u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
+u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
+u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB_SERIAL
|
|
||||||
extern int ssb_extif_serial_init(struct ssb_extif *extif,
|
|
||||||
@ -1,193 +0,0 @@
|
|||||||
--- a/arch/mips/Kconfig
|
|
||||||
+++ b/arch/mips/Kconfig
|
|
||||||
@@ -4,6 +4,10 @@
|
|
||||||
# Horrible source of confusion. Die, die, die ...
|
|
||||||
select EMBEDDED
|
|
||||||
|
|
||||||
+config CFE
|
|
||||||
+ bool
|
|
||||||
+ # Common Firmware Environment
|
|
||||||
+
|
|
||||||
mainmenu "Linux/MIPS Kernel Configuration"
|
|
||||||
|
|
||||||
menu "Machine selection"
|
|
||||||
@@ -44,6 +48,23 @@
|
|
||||||
note that a kernel built with this option selected will not be
|
|
||||||
able to run on normal units.
|
|
||||||
|
|
||||||
+config BCM947XX
|
|
||||||
+ bool "Support for BCM947xx based boards"
|
|
||||||
+ select DMA_NONCOHERENT
|
|
||||||
+ select HW_HAS_PCI
|
|
||||||
+ select IRQ_CPU
|
|
||||||
+ select SYS_HAS_CPU_MIPS32_R1
|
|
||||||
+ select SYS_SUPPORTS_32BIT_KERNEL
|
|
||||||
+ select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
||||||
+ select SSB
|
|
||||||
+ select SSB_SERIAL
|
|
||||||
+ select SSB_DRIVER_PCICORE
|
|
||||||
+ select SSB_PCICORE_HOSTMODE
|
|
||||||
+ select CFE
|
|
||||||
+ select GENERIC_GPIO
|
|
||||||
+ help
|
|
||||||
+ Support for BCM947xx based boards
|
|
||||||
+
|
|
||||||
config MIPS_COBALT
|
|
||||||
bool "Cobalt Server"
|
|
||||||
select DMA_NONCOHERENT
|
|
||||||
--- a/arch/mips/kernel/cpu-probe.c
|
|
||||||
+++ b/arch/mips/kernel/cpu-probe.c
|
|
||||||
@@ -793,6 +793,28 @@
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
|
|
||||||
+{
|
|
||||||
+ decode_config1(c);
|
|
||||||
+ switch (c->processor_id & 0xff00) {
|
|
||||||
+ case PRID_IMP_BCM3302:
|
|
||||||
+ c->cputype = CPU_BCM3302;
|
|
||||||
+ c->isa_level = MIPS_CPU_ISA_M32R1;
|
|
||||||
+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
|
|
||||||
+ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
|
|
||||||
+ break;
|
|
||||||
+ case PRID_IMP_BCM4710:
|
|
||||||
+ c->cputype = CPU_BCM4710;
|
|
||||||
+ c->isa_level = MIPS_CPU_ISA_M32R1;
|
|
||||||
+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
|
|
||||||
+ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
|
|
||||||
+ break;
|
|
||||||
+ default:
|
|
||||||
+ c->cputype = CPU_UNKNOWN;
|
|
||||||
+ break;
|
|
||||||
+ }
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
__init void cpu_probe(void)
|
|
||||||
{
|
|
||||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
||||||
@@ -815,6 +837,9 @@
|
|
||||||
case PRID_COMP_SIBYTE:
|
|
||||||
cpu_probe_sibyte(c);
|
|
||||||
break;
|
|
||||||
+ case PRID_COMP_BROADCOM:
|
|
||||||
+ cpu_probe_broadcom(c);
|
|
||||||
+ break;
|
|
||||||
case PRID_COMP_SANDCRAFT:
|
|
||||||
cpu_probe_sandcraft(c);
|
|
||||||
break;
|
|
||||||
--- a/arch/mips/kernel/proc.c
|
|
||||||
+++ b/arch/mips/kernel/proc.c
|
|
||||||
@@ -82,6 +82,8 @@
|
|
||||||
[CPU_VR4181] = "NEC VR4181",
|
|
||||||
[CPU_VR4181A] = "NEC VR4181A",
|
|
||||||
[CPU_SR71000] = "Sandcraft SR71000",
|
|
||||||
+ [CPU_BCM3302] = "Broadcom BCM3302",
|
|
||||||
+ [CPU_BCM4710] = "Broadcom BCM4710",
|
|
||||||
[CPU_PR4450] = "Philips PR4450",
|
|
||||||
[CPU_LOONGSON2] = "ICT Loongson-2",
|
|
||||||
};
|
|
||||||
--- a/arch/mips/Makefile
|
|
||||||
+++ b/arch/mips/Makefile
|
|
||||||
@@ -533,6 +533,18 @@
|
|
||||||
load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
|
|
||||||
|
|
||||||
#
|
|
||||||
+# Broadcom BCM47XX boards
|
|
||||||
+#
|
|
||||||
+core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/
|
|
||||||
+cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx
|
|
||||||
+load-$(CONFIG_BCM947XX) := 0xffffffff80001000
|
|
||||||
+
|
|
||||||
+#
|
|
||||||
+# Common Firmware Environment
|
|
||||||
+#
|
|
||||||
+core-$(CONFIG_CFE) += arch/mips/cfe/
|
|
||||||
+
|
|
||||||
+#
|
|
||||||
# SNI RM
|
|
||||||
#
|
|
||||||
core-$(CONFIG_SNI_RM) += arch/mips/sni/
|
|
||||||
--- a/arch/mips/mm/tlbex.c
|
|
||||||
+++ b/arch/mips/mm/tlbex.c
|
|
||||||
@@ -895,6 +895,8 @@
|
|
||||||
case CPU_AU1550:
|
|
||||||
case CPU_AU1200:
|
|
||||||
case CPU_PR4450:
|
|
||||||
+ case CPU_BCM3302:
|
|
||||||
+ case CPU_BCM4710:
|
|
||||||
i_nop(p);
|
|
||||||
tlbw(p);
|
|
||||||
break;
|
|
||||||
--- a/drivers/Kconfig
|
|
||||||
+++ b/drivers/Kconfig
|
|
||||||
@@ -60,6 +60,8 @@
|
|
||||||
|
|
||||||
source "drivers/hwmon/Kconfig"
|
|
||||||
|
|
||||||
+source "drivers/ssb/Kconfig"
|
|
||||||
+
|
|
||||||
source "drivers/mfd/Kconfig"
|
|
||||||
|
|
||||||
source "drivers/media/Kconfig"
|
|
||||||
--- a/include/asm-mips/bootinfo.h
|
|
||||||
+++ b/include/asm-mips/bootinfo.h
|
|
||||||
@@ -208,6 +208,12 @@
|
|
||||||
#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */
|
|
||||||
#define MACH_WRPPMC 1
|
|
||||||
|
|
||||||
+/*
|
|
||||||
+ * Valid machtype for group Broadcom
|
|
||||||
+ */
|
|
||||||
+#define MACH_GROUP_BRCM 23 /* Broadcom */
|
|
||||||
+#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
|
|
||||||
+
|
|
||||||
#define CL_SIZE COMMAND_LINE_SIZE
|
|
||||||
|
|
||||||
const char *get_system_type(void);
|
|
||||||
--- a/include/asm-mips/cpu.h
|
|
||||||
+++ b/include/asm-mips/cpu.h
|
|
||||||
@@ -106,6 +106,13 @@
|
|
||||||
#define PRID_IMP_SR71000 0x0400
|
|
||||||
|
|
||||||
/*
|
|
||||||
+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+#define PRID_IMP_BCM4710 0x4000
|
|
||||||
+#define PRID_IMP_BCM3302 0x9000
|
|
||||||
+
|
|
||||||
+/*
|
|
||||||
* Definitions for 7:0 on legacy processors
|
|
||||||
*/
|
|
||||||
|
|
||||||
@@ -217,8 +224,10 @@
|
|
||||||
#define CPU_R14000 64
|
|
||||||
#define CPU_LOONGSON1 65
|
|
||||||
#define CPU_LOONGSON2 66
|
|
||||||
+#define CPU_BCM3302 67
|
|
||||||
+#define CPU_BCM4710 68
|
|
||||||
|
|
||||||
-#define CPU_LAST 66
|
|
||||||
+#define CPU_LAST 68
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ISA Level encodings
|
|
||||||
--- a/drivers/Makefile
|
|
||||||
+++ b/drivers/Makefile
|
|
||||||
@@ -89,3 +89,5 @@
|
|
||||||
obj-$(CONFIG_HID) += hid/
|
|
||||||
obj-$(CONFIG_PPC_PS3) += ps3/
|
|
||||||
obj-$(CONFIG_OF) += of/
|
|
||||||
+obj-$(CONFIG_SSB) += ssb/
|
|
||||||
+
|
|
||||||
--- a/include/linux/pci_ids.h
|
|
||||||
+++ b/include/linux/pci_ids.h
|
|
||||||
@@ -1980,6 +1980,7 @@
|
|
||||||
#define PCI_DEVICE_ID_TIGON3_5906M 0x1713
|
|
||||||
#define PCI_DEVICE_ID_BCM4401 0x4401
|
|
||||||
#define PCI_DEVICE_ID_BCM4401B0 0x4402
|
|
||||||
+#define PCI_DEVICE_ID_BCM4713 0x4713
|
|
||||||
|
|
||||||
#define PCI_VENDOR_ID_TOPIC 0x151f
|
|
||||||
#define PCI_DEVICE_ID_TOPIC_TP560 0x0000
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
--- a/drivers/mtd/maps/Kconfig
|
|
||||||
+++ b/drivers/mtd/maps/Kconfig
|
|
||||||
@@ -352,6 +352,12 @@
|
|
||||||
Mapping for the Flaga digital module. If you don't have one, ignore
|
|
||||||
this setting.
|
|
||||||
|
|
||||||
+config MTD_BCM47XX
|
|
||||||
+ tristate "BCM47xx flash device"
|
|
||||||
+ depends on MIPS && MTD_CFI && BCM947XX
|
|
||||||
+ help
|
|
||||||
+ Support for the flash chips on the BCM947xx board.
|
|
||||||
+
|
|
||||||
config MTD_WALNUT
|
|
||||||
tristate "Flash device mapped on IBM 405GP Walnut"
|
|
||||||
depends on MTD_JEDECPROBE && WALNUT
|
|
||||||
--- a/drivers/mtd/maps/Makefile
|
|
||||||
+++ b/drivers/mtd/maps/Makefile
|
|
||||||
@@ -33,6 +33,7 @@
|
|
||||||
obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
|
|
||||||
obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
|
|
||||||
obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
|
|
||||||
+obj-$(CONFIG_MTD_BCM47XX) += bcm47xx-flash.o
|
|
||||||
obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
|
|
||||||
obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
|
|
||||||
obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,13 +0,0 @@
|
|||||||
--- a/drivers/net/b44.c
|
|
||||||
+++ b/drivers/net/b44.c
|
|
||||||
@@ -2273,6 +2273,10 @@
|
|
||||||
bp->phy_addr = sdev->bus->sprom.et1phyaddr;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
+ /* Some ROMs have buggy PHY addresses with the high
|
|
||||||
+ * bits set (sign extension?). Truncate them to a
|
|
||||||
+ * valid PHY address. */
|
|
||||||
+ bp->phy_addr &= 0x1F;
|
|
||||||
|
|
||||||
memcpy(bp->dev->dev_addr, addr, 6);
|
|
||||||
|
|
||||||
@ -1,89 +0,0 @@
|
|||||||
--- a/arch/mips/Kconfig
|
|
||||||
+++ b/arch/mips/Kconfig
|
|
||||||
@@ -192,7 +192,6 @@
|
|
||||||
select I8259
|
|
||||||
select MIPS_BOARDS_GEN
|
|
||||||
select MIPS_BONITO64
|
|
||||||
- select MIPS_CPU_SCACHE
|
|
||||||
select PCI_GT64XXX_PCI0
|
|
||||||
select MIPS_MSC
|
|
||||||
select SWAP_IO_SPACE
|
|
||||||
@@ -1281,13 +1280,6 @@
|
|
||||||
bool
|
|
||||||
select BOARD_SCACHE
|
|
||||||
|
|
||||||
-#
|
|
||||||
-# Support for a MIPS32 / MIPS64 style S-caches
|
|
||||||
-#
|
|
||||||
-config MIPS_CPU_SCACHE
|
|
||||||
- bool
|
|
||||||
- select BOARD_SCACHE
|
|
||||||
-
|
|
||||||
config R5000_CPU_SCACHE
|
|
||||||
bool
|
|
||||||
select BOARD_SCACHE
|
|
||||||
--- a/arch/mips/kernel/cpu-probe.c
|
|
||||||
+++ b/arch/mips/kernel/cpu-probe.c
|
|
||||||
@@ -701,6 +701,8 @@
|
|
||||||
break;
|
|
||||||
case PRID_IMP_25KF:
|
|
||||||
c->cputype = CPU_25KF;
|
|
||||||
+ /* Probe for L2 cache */
|
|
||||||
+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
|
|
||||||
break;
|
|
||||||
case PRID_IMP_34K:
|
|
||||||
c->cputype = CPU_34K;
|
|
||||||
--- a/arch/mips/mm/c-r4k.c
|
|
||||||
+++ b/arch/mips/mm/c-r4k.c
|
|
||||||
@@ -1101,7 +1101,6 @@
|
|
||||||
|
|
||||||
extern int r5k_sc_init(void);
|
|
||||||
extern int rm7k_sc_init(void);
|
|
||||||
-extern int mips_sc_init(void);
|
|
||||||
|
|
||||||
static void __init setup_scache(void)
|
|
||||||
{
|
|
||||||
@@ -1155,29 +1154,17 @@
|
|
||||||
#endif
|
|
||||||
|
|
||||||
default:
|
|
||||||
- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
|
|
||||||
- c->isa_level == MIPS_CPU_ISA_M32R2 ||
|
|
||||||
- c->isa_level == MIPS_CPU_ISA_M64R1 ||
|
|
||||||
- c->isa_level == MIPS_CPU_ISA_M64R2) {
|
|
||||||
-#ifdef CONFIG_MIPS_CPU_SCACHE
|
|
||||||
- if (mips_sc_init ()) {
|
|
||||||
- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
|
|
||||||
- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
|
|
||||||
- scache_size >> 10,
|
|
||||||
- way_string[c->scache.ways], c->scache.linesz);
|
|
||||||
- }
|
|
||||||
-#else
|
|
||||||
- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
|
|
||||||
- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
|
|
||||||
-#endif
|
|
||||||
- return;
|
|
||||||
- }
|
|
||||||
sc_present = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!sc_present)
|
|
||||||
return;
|
|
||||||
|
|
||||||
+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
|
|
||||||
+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
|
|
||||||
+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
|
|
||||||
+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
|
|
||||||
+
|
|
||||||
/* compute a couple of other cache variables */
|
|
||||||
c->scache.waysize = scache_size / c->scache.ways;
|
|
||||||
|
|
||||||
--- a/arch/mips/mm/Makefile
|
|
||||||
+++ b/arch/mips/mm/Makefile
|
|
||||||
@@ -31,6 +31,5 @@
|
|
||||||
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
|
|
||||||
obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
|
|
||||||
obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
|
|
||||||
-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
|
|
||||||
|
|
||||||
EXTRA_CFLAGS += -Werror
|
|
||||||
@ -1,351 +0,0 @@
|
|||||||
--- a/arch/mips/kernel/genex.S
|
|
||||||
+++ b/arch/mips/kernel/genex.S
|
|
||||||
@@ -51,6 +51,10 @@
|
|
||||||
NESTED(except_vec3_generic, 0, sp)
|
|
||||||
.set push
|
|
||||||
.set noat
|
|
||||||
+#ifdef CONFIG_BCM947XX
|
|
||||||
+ nop
|
|
||||||
+ nop
|
|
||||||
+#endif
|
|
||||||
#if R5432_CP0_INTERRUPT_WAR
|
|
||||||
mfc0 k0, CP0_INDEX
|
|
||||||
#endif
|
|
||||||
--- a/arch/mips/mm/c-r4k.c
|
|
||||||
+++ b/arch/mips/mm/c-r4k.c
|
|
||||||
@@ -30,6 +30,9 @@
|
|
||||||
#include <asm/cacheflush.h> /* for run_uncached() */
|
|
||||||
|
|
||||||
|
|
||||||
+/* For enabling BCM4710 cache workarounds */
|
|
||||||
+int bcm4710 = 0;
|
|
||||||
+
|
|
||||||
/*
|
|
||||||
* Special Variant of smp_call_function for use by cache functions:
|
|
||||||
*
|
|
||||||
@@ -94,6 +97,9 @@
|
|
||||||
{
|
|
||||||
unsigned long dc_lsize = cpu_dcache_line_size();
|
|
||||||
|
|
||||||
+ if (bcm4710)
|
|
||||||
+ r4k_blast_dcache_page = blast_dcache_page;
|
|
||||||
+ else
|
|
||||||
if (dc_lsize == 0)
|
|
||||||
r4k_blast_dcache_page = (void *)cache_noop;
|
|
||||||
else if (dc_lsize == 16)
|
|
||||||
@@ -108,6 +114,9 @@
|
|
||||||
{
|
|
||||||
unsigned long dc_lsize = cpu_dcache_line_size();
|
|
||||||
|
|
||||||
+ if (bcm4710)
|
|
||||||
+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
|
|
||||||
+ else
|
|
||||||
if (dc_lsize == 0)
|
|
||||||
r4k_blast_dcache_page_indexed = (void *)cache_noop;
|
|
||||||
else if (dc_lsize == 16)
|
|
||||||
@@ -122,6 +131,9 @@
|
|
||||||
{
|
|
||||||
unsigned long dc_lsize = cpu_dcache_line_size();
|
|
||||||
|
|
||||||
+ if (bcm4710)
|
|
||||||
+ r4k_blast_dcache = blast_dcache;
|
|
||||||
+ else
|
|
||||||
if (dc_lsize == 0)
|
|
||||||
r4k_blast_dcache = (void *)cache_noop;
|
|
||||||
else if (dc_lsize == 16)
|
|
||||||
@@ -638,6 +650,8 @@
|
|
||||||
unsigned long addr = (unsigned long) arg;
|
|
||||||
|
|
||||||
R4600_HIT_CACHEOP_WAR_IMPL;
|
|
||||||
+ BCM4710_PROTECTED_FILL_TLB(addr);
|
|
||||||
+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
|
|
||||||
if (dc_lsize)
|
|
||||||
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
|
|
||||||
if (!cpu_icache_snoops_remote_store && scache_size)
|
|
||||||
@@ -1213,6 +1227,17 @@
|
|
||||||
* silly idea of putting something else there ...
|
|
||||||
*/
|
|
||||||
switch (current_cpu_data.cputype) {
|
|
||||||
+ case CPU_BCM3302:
|
|
||||||
+ {
|
|
||||||
+ u32 cm;
|
|
||||||
+ cm = read_c0_diag();
|
|
||||||
+ /* Enable icache */
|
|
||||||
+ cm |= (1 << 31);
|
|
||||||
+ /* Enable dcache */
|
|
||||||
+ cm |= (1 << 30);
|
|
||||||
+ write_c0_diag(cm);
|
|
||||||
+ }
|
|
||||||
+ break;
|
|
||||||
case CPU_R4000PC:
|
|
||||||
case CPU_R4000SC:
|
|
||||||
case CPU_R4000MC:
|
|
||||||
@@ -1243,6 +1268,15 @@
|
|
||||||
/* Default cache error handler for R4000 and R5000 family */
|
|
||||||
set_uncached_handler (0x100, &except_vec2_generic, 0x80);
|
|
||||||
|
|
||||||
+ /* Check if special workarounds are required */
|
|
||||||
+#ifdef CONFIG_BCM947XX
|
|
||||||
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
|
|
||||||
+ printk("Enabling BCM4710A0 cache workarounds.\n");
|
|
||||||
+ bcm4710 = 1;
|
|
||||||
+ } else
|
|
||||||
+#endif
|
|
||||||
+ bcm4710 = 0;
|
|
||||||
+
|
|
||||||
probe_pcache();
|
|
||||||
setup_scache();
|
|
||||||
|
|
||||||
@@ -1288,5 +1322,13 @@
|
|
||||||
build_clear_page();
|
|
||||||
build_copy_page();
|
|
||||||
local_r4k___flush_cache_all(NULL);
|
|
||||||
+#ifdef CONFIG_BCM947XX
|
|
||||||
+ {
|
|
||||||
+ static void (*_coherency_setup)(void);
|
|
||||||
+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
|
|
||||||
+ _coherency_setup();
|
|
||||||
+ }
|
|
||||||
+#else
|
|
||||||
coherency_setup();
|
|
||||||
+#endif
|
|
||||||
}
|
|
||||||
--- a/arch/mips/mm/tlbex.c
|
|
||||||
+++ b/arch/mips/mm/tlbex.c
|
|
||||||
@@ -1273,6 +1273,9 @@
|
|
||||||
/* No need for i_nop */
|
|
||||||
}
|
|
||||||
|
|
||||||
+#ifdef CONFIG_BCM947XX
|
|
||||||
+ i_nop(&p);
|
|
||||||
+#endif
|
|
||||||
#ifdef CONFIG_64BIT
|
|
||||||
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
|
||||||
#else
|
|
||||||
@@ -1708,6 +1711,9 @@
|
|
||||||
struct reloc **r, unsigned int pte,
|
|
||||||
unsigned int ptr)
|
|
||||||
{
|
|
||||||
+#ifdef CONFIG_BCM947XX
|
|
||||||
+ i_nop(p);
|
|
||||||
+#endif
|
|
||||||
#ifdef CONFIG_64BIT
|
|
||||||
build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
|
|
||||||
#else
|
|
||||||
--- a/include/asm-mips/r4kcache.h
|
|
||||||
+++ b/include/asm-mips/r4kcache.h
|
|
||||||
@@ -17,6 +17,20 @@
|
|
||||||
#include <asm/cpu-features.h>
|
|
||||||
#include <asm/mipsmtregs.h>
|
|
||||||
|
|
||||||
+#ifdef CONFIG_BCM947XX
|
|
||||||
+#include <asm/paccess.h>
|
|
||||||
+#include <linux/ssb/ssb.h>
|
|
||||||
+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
|
|
||||||
+
|
|
||||||
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
|
|
||||||
+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
|
|
||||||
+#else
|
|
||||||
+#define BCM4710_DUMMY_RREG()
|
|
||||||
+
|
|
||||||
+#define BCM4710_FILL_TLB(addr)
|
|
||||||
+#define BCM4710_PROTECTED_FILL_TLB(addr)
|
|
||||||
+#endif
|
|
||||||
+
|
|
||||||
/*
|
|
||||||
* This macro return a properly sign-extended address suitable as base address
|
|
||||||
* for indexed cache operations. Two issues here:
|
|
||||||
@@ -150,6 +164,7 @@
|
|
||||||
static inline void flush_dcache_line_indexed(unsigned long addr)
|
|
||||||
{
|
|
||||||
__dflush_prologue
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
cache_op(Index_Writeback_Inv_D, addr);
|
|
||||||
__dflush_epilogue
|
|
||||||
}
|
|
||||||
@@ -169,6 +184,7 @@
|
|
||||||
static inline void flush_dcache_line(unsigned long addr)
|
|
||||||
{
|
|
||||||
__dflush_prologue
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
cache_op(Hit_Writeback_Inv_D, addr);
|
|
||||||
__dflush_epilogue
|
|
||||||
}
|
|
||||||
@@ -176,6 +192,7 @@
|
|
||||||
static inline void invalidate_dcache_line(unsigned long addr)
|
|
||||||
{
|
|
||||||
__dflush_prologue
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
cache_op(Hit_Invalidate_D, addr);
|
|
||||||
__dflush_epilogue
|
|
||||||
}
|
|
||||||
@@ -208,6 +225,7 @@
|
|
||||||
*/
|
|
||||||
static inline void protected_flush_icache_line(unsigned long addr)
|
|
||||||
{
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
protected_cache_op(Hit_Invalidate_I, addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
@@ -219,6 +237,7 @@
|
|
||||||
*/
|
|
||||||
static inline void protected_writeback_dcache_line(unsigned long addr)
|
|
||||||
{
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
protected_cache_op(Hit_Writeback_Inv_D, addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
@@ -339,8 +358,52 @@
|
|
||||||
: "r" (base), \
|
|
||||||
"i" (op));
|
|
||||||
|
|
||||||
+static inline void blast_dcache(void)
|
|
||||||
+{
|
|
||||||
+ unsigned long start = KSEG0;
|
|
||||||
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
|
|
||||||
+ unsigned long end = (start + dcache_size);
|
|
||||||
+
|
|
||||||
+ do {
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+ cache_op(Index_Writeback_Inv_D, start);
|
|
||||||
+ start += current_cpu_data.dcache.linesz;
|
|
||||||
+ } while(start < end);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static inline void blast_dcache_page(unsigned long page)
|
|
||||||
+{
|
|
||||||
+ unsigned long start = page;
|
|
||||||
+ unsigned long end = start + PAGE_SIZE;
|
|
||||||
+
|
|
||||||
+ BCM4710_FILL_TLB(start);
|
|
||||||
+ do {
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+ cache_op(Hit_Writeback_Inv_D, start);
|
|
||||||
+ start += current_cpu_data.dcache.linesz;
|
|
||||||
+ } while(start < end);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static inline void blast_dcache_page_indexed(unsigned long page)
|
|
||||||
+{
|
|
||||||
+ unsigned long start = page;
|
|
||||||
+ unsigned long end = start + PAGE_SIZE;
|
|
||||||
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
|
||||||
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
|
|
||||||
+ current_cpu_data.dcache.waybit;
|
|
||||||
+ unsigned long ws, addr;
|
|
||||||
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
|
|
||||||
+ start = page + ws;
|
|
||||||
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
|
|
||||||
+ BCM4710_DUMMY_RREG();
|
|
||||||
+ cache_op(Index_Writeback_Inv_D, addr);
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+
|
|
||||||
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
|
|
||||||
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
|
|
||||||
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
|
|
||||||
static inline void blast_##pfx##cache##lsize(void) \
|
|
||||||
{ \
|
|
||||||
unsigned long start = INDEX_BASE; \
|
|
||||||
@@ -352,6 +415,7 @@
|
|
||||||
\
|
|
||||||
__##pfx##flush_prologue \
|
|
||||||
\
|
|
||||||
+ war \
|
|
||||||
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
|
||||||
for (addr = start; addr < end; addr += lsize * 32) \
|
|
||||||
cache##lsize##_unroll32(addr|ws,indexop); \
|
|
||||||
@@ -366,6 +430,7 @@
|
|
||||||
\
|
|
||||||
__##pfx##flush_prologue \
|
|
||||||
\
|
|
||||||
+ war \
|
|
||||||
do { \
|
|
||||||
cache##lsize##_unroll32(start,hitop); \
|
|
||||||
start += lsize * 32; \
|
|
||||||
@@ -384,6 +449,8 @@
|
|
||||||
current_cpu_data.desc.waybit; \
|
|
||||||
unsigned long ws, addr; \
|
|
||||||
\
|
|
||||||
+ war \
|
|
||||||
+ \
|
|
||||||
__##pfx##flush_prologue \
|
|
||||||
\
|
|
||||||
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
|
||||||
@@ -393,28 +460,30 @@
|
|
||||||
__##pfx##flush_epilogue \
|
|
||||||
}
|
|
||||||
|
|
||||||
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
|
|
||||||
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
|
|
||||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
|
|
||||||
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
|
|
||||||
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
|
|
||||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
|
|
||||||
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
|
|
||||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
|
|
||||||
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
|
|
||||||
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
|
|
||||||
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
|
|
||||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
|
|
||||||
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
|
|
||||||
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
|
|
||||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
|
|
||||||
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
|
|
||||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
|
|
||||||
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
|
|
||||||
|
|
||||||
/* build blast_xxx_range, protected_blast_xxx_range */
|
|
||||||
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
|
|
||||||
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
|
|
||||||
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
|
|
||||||
unsigned long end) \
|
|
||||||
{ \
|
|
||||||
unsigned long lsize = cpu_##desc##_line_size(); \
|
|
||||||
unsigned long addr = start & ~(lsize - 1); \
|
|
||||||
unsigned long aend = (end - 1) & ~(lsize - 1); \
|
|
||||||
+ war \
|
|
||||||
\
|
|
||||||
__##pfx##flush_prologue \
|
|
||||||
\
|
|
||||||
while (1) { \
|
|
||||||
+ war2 \
|
|
||||||
prot##cache_op(hitop, addr); \
|
|
||||||
if (addr == aend) \
|
|
||||||
break; \
|
|
||||||
@@ -424,13 +493,13 @@
|
|
||||||
__##pfx##flush_epilogue \
|
|
||||||
}
|
|
||||||
|
|
||||||
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
|
|
||||||
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
|
|
||||||
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
|
|
||||||
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
|
|
||||||
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
|
|
||||||
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
|
||||||
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
|
|
||||||
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
|
|
||||||
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
|
||||||
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
|
|
||||||
/* blast_inv_dcache_range */
|
|
||||||
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
|
|
||||||
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
|
|
||||||
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
|
|
||||||
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
|
|
||||||
|
|
||||||
#endif /* _ASM_R4KCACHE_H */
|
|
||||||
--- a/include/asm-mips/stackframe.h
|
|
||||||
+++ b/include/asm-mips/stackframe.h
|
|
||||||
@@ -350,6 +350,10 @@
|
|
||||||
.macro RESTORE_SP_AND_RET
|
|
||||||
LONG_L sp, PT_R29(sp)
|
|
||||||
.set mips3
|
|
||||||
+#ifdef CONFIG_BCM947XX
|
|
||||||
+ nop
|
|
||||||
+ nop
|
|
||||||
+#endif
|
|
||||||
eret
|
|
||||||
.set mips0
|
|
||||||
.endm
|
|
||||||
@ -1,57 +0,0 @@
|
|||||||
--- a/arch/mips/mm/init.c
|
|
||||||
+++ b/arch/mips/mm/init.c
|
|
||||||
@@ -211,7 +211,7 @@
|
|
||||||
void *vfrom, *vto;
|
|
||||||
|
|
||||||
vto = kmap_atomic(to, KM_USER1);
|
|
||||||
- if (cpu_has_dc_aliases && !Page_dcache_dirty(from)) {
|
|
||||||
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && !Page_dcache_dirty(from)) {
|
|
||||||
vfrom = kmap_coherent(from, vaddr);
|
|
||||||
copy_page(vto, vfrom);
|
|
||||||
kunmap_coherent();
|
|
||||||
@@ -234,7 +234,7 @@
|
|
||||||
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
|
||||||
unsigned long len)
|
|
||||||
{
|
|
||||||
- if (cpu_has_dc_aliases) {
|
|
||||||
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent) {
|
|
||||||
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
|
||||||
memcpy(vto, src, len);
|
|
||||||
kunmap_coherent();
|
|
||||||
@@ -250,7 +250,7 @@
|
|
||||||
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
|
||||||
unsigned long len)
|
|
||||||
{
|
|
||||||
- if (cpu_has_dc_aliases) {
|
|
||||||
+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent) {
|
|
||||||
void *vfrom =
|
|
||||||
kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
|
||||||
memcpy(dst, vfrom, len);
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/include/asm-mips/mach-bcm947xx/cpu-feature-overrides.h
|
|
||||||
@@ -0,0 +1,13 @@
|
|
||||||
+/*
|
|
||||||
+ * This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
+ * License. See the file "COPYING" in the main directory of this archive
|
|
||||||
+ * for more details.
|
|
||||||
+ *
|
|
||||||
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
|
|
||||||
+ */
|
|
||||||
+#ifndef __ASM_MACH_BCM947XX_CPU_FEATURE_OVERRIDES_H
|
|
||||||
+#define __ASM_MACH_BCM947XX_CPU_FEATURE_OVERRIDES_H
|
|
||||||
+
|
|
||||||
+#define cpu_use_kmap_coherent 0
|
|
||||||
+
|
|
||||||
+#endif /* __ASM_MACH_BCM947XX_CPU_FEATURE_OVERRIDES_H */
|
|
||||||
--- a/include/asm-mips/cpu-features.h
|
|
||||||
+++ b/include/asm-mips/cpu-features.h
|
|
||||||
@@ -101,6 +101,9 @@
|
|
||||||
#ifndef cpu_has_pindexed_dcache
|
|
||||||
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
|
|
||||||
#endif
|
|
||||||
+#ifndef cpu_use_kmap_coherent
|
|
||||||
+#define cpu_use_kmap_coherent 1
|
|
||||||
+#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
|
|
||||||
@ -1,10 +0,0 @@
|
|||||||
--- a/arch/mips/kernel/cpu-probe.c
|
|
||||||
+++ b/arch/mips/kernel/cpu-probe.c
|
|
||||||
@@ -159,6 +159,7 @@
|
|
||||||
case CPU_5KC:
|
|
||||||
case CPU_25KF:
|
|
||||||
case CPU_PR4450:
|
|
||||||
+ case CPU_BCM3302:
|
|
||||||
cpu_wait = r4k_wait;
|
|
||||||
break;
|
|
||||||
|
|
||||||
@ -1,42 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_chipcommon.c
|
|
||||||
+++ b/drivers/ssb/driver_chipcommon.c
|
|
||||||
@@ -270,6 +270,8 @@
|
|
||||||
void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
|
|
||||||
u32 *plltype, u32 *n, u32 *m)
|
|
||||||
{
|
|
||||||
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
|
|
||||||
+ return;
|
|
||||||
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
|
||||||
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
|
||||||
switch (*plltype) {
|
|
||||||
@@ -293,6 +295,8 @@
|
|
||||||
void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
|
|
||||||
u32 *plltype, u32 *n, u32 *m)
|
|
||||||
{
|
|
||||||
+ if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
|
|
||||||
+ return;
|
|
||||||
*n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
|
|
||||||
*plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
|
||||||
switch (*plltype) {
|
|
||||||
--- a/drivers/ssb/driver_mipscore.c
|
|
||||||
+++ b/drivers/ssb/driver_mipscore.c
|
|
||||||
@@ -161,6 +161,8 @@
|
|
||||||
|
|
||||||
if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
|
|
||||||
rate = 200000000;
|
|
||||||
+ } else if (bus->chip_id == 0x5354) {
|
|
||||||
+ rate = 240000000;
|
|
||||||
} else {
|
|
||||||
rate = ssb_calc_clock_rate(pll_type, n, m);
|
|
||||||
}
|
|
||||||
--- a/drivers/ssb/main.c
|
|
||||||
+++ b/drivers/ssb/main.c
|
|
||||||
@@ -862,6 +862,8 @@
|
|
||||||
|
|
||||||
if (bus->chip_id == 0x5365) {
|
|
||||||
rate = 100000000;
|
|
||||||
+ } else if (bus->chip_id == 0x5354) {
|
|
||||||
+ rate = 120000000;
|
|
||||||
} else {
|
|
||||||
rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
|
|
||||||
if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
|
|
||||||
@ -1,339 +0,0 @@
|
|||||||
From: Michael Buesch <mb@bu3sch.de>
|
|
||||||
Date: Wed, 10 Oct 2007 06:47:17 +0000 (-0700)
|
|
||||||
Subject: USB: ohci SSB bus glue
|
|
||||||
X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fralf%2Flinux.git;a=commitdiff_plain;h=c604e851486eabcbeb73e984279d436ce121fd5d
|
|
||||||
|
|
||||||
USB: ohci SSB bus glue
|
|
||||||
|
|
||||||
This adds SSB bus glue for the USB OHCI HCD.
|
|
||||||
|
|
||||||
Signed-off-by: Michael Buesch <mb@bu3sch.de>
|
|
||||||
Signed-off-by: John W. Linville <linville@tuxdriver.com>
|
|
||||||
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
|
|
||||||
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
|
||||||
---
|
|
||||||
|
|
||||||
--- a/drivers/usb/host/Kconfig
|
|
||||||
+++ b/drivers/usb/host/Kconfig
|
|
||||||
@@ -154,6 +154,19 @@
|
|
||||||
Enables support for PCI-bus plug-in USB controller cards.
|
|
||||||
If unsure, say Y.
|
|
||||||
|
|
||||||
+config USB_OHCI_HCD_SSB
|
|
||||||
+ bool "OHCI support for Broadcom SSB OHCI core"
|
|
||||||
+ depends on USB_OHCI_HCD && SSB && EXPERIMENTAL
|
|
||||||
+ default n
|
|
||||||
+ ---help---
|
|
||||||
+ Support for the Sonics Silicon Backplane (SSB) attached
|
|
||||||
+ Broadcom USB OHCI core.
|
|
||||||
+
|
|
||||||
+ This device is present in some embedded devices with
|
|
||||||
+ Broadcom based SSB bus.
|
|
||||||
+
|
|
||||||
+ If unsure, say N.
|
|
||||||
+
|
|
||||||
config USB_OHCI_BIG_ENDIAN_DESC
|
|
||||||
bool
|
|
||||||
depends on USB_OHCI_HCD
|
|
||||||
--- a/drivers/usb/host/ohci-hcd.c
|
|
||||||
+++ b/drivers/usb/host/ohci-hcd.c
|
|
||||||
@@ -926,11 +926,17 @@
|
|
||||||
#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
|
|
||||||
#endif
|
|
||||||
|
|
||||||
+#ifdef CONFIG_USB_OHCI_HCD_SSB
|
|
||||||
+#include "ohci-ssb.c"
|
|
||||||
+#define SSB_OHCI_DRIVER ssb_ohci_driver
|
|
||||||
+#endif
|
|
||||||
+
|
|
||||||
#if !defined(PCI_DRIVER) && \
|
|
||||||
!defined(PLATFORM_DRIVER) && \
|
|
||||||
!defined(OF_PLATFORM_DRIVER) && \
|
|
||||||
!defined(SA1111_DRIVER) && \
|
|
||||||
- !defined(PS3_SYSTEM_BUS_DRIVER)
|
|
||||||
+ !defined(PS3_SYSTEM_BUS_DRIVER) && \
|
|
||||||
+ !defined(SSB_OHCI_DRIVER)
|
|
||||||
#error "missing bus glue for ohci-hcd"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
@@ -975,10 +981,20 @@
|
|
||||||
goto error_pci;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
+#ifdef SSB_OHCI_DRIVER
|
|
||||||
+ retval = ssb_driver_register(&SSB_OHCI_DRIVER);
|
|
||||||
+ if (retval)
|
|
||||||
+ goto error_ssb;
|
|
||||||
+#endif
|
|
||||||
+
|
|
||||||
return retval;
|
|
||||||
|
|
||||||
/* Error path */
|
|
||||||
+#ifdef SSB_OHCI_DRIVER
|
|
||||||
+ error_ssb:
|
|
||||||
+#endif
|
|
||||||
#ifdef PCI_DRIVER
|
|
||||||
+ pci_unregister_driver(&PCI_DRIVER);
|
|
||||||
error_pci:
|
|
||||||
#endif
|
|
||||||
#ifdef SA1111_DRIVER
|
|
||||||
@@ -1003,6 +1019,9 @@
|
|
||||||
|
|
||||||
static void __exit ohci_hcd_mod_exit(void)
|
|
||||||
{
|
|
||||||
+#ifdef SSB_OHCI_DRIVER
|
|
||||||
+ ssb_driver_unregister(&SSB_OHCI_DRIVER);
|
|
||||||
+#endif
|
|
||||||
#ifdef PCI_DRIVER
|
|
||||||
pci_unregister_driver(&PCI_DRIVER);
|
|
||||||
#endif
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/drivers/usb/host/ohci-ssb.c
|
|
||||||
@@ -0,0 +1,247 @@
|
|
||||||
+/*
|
|
||||||
+ * Sonics Silicon Backplane
|
|
||||||
+ * Broadcom USB-core OHCI driver
|
|
||||||
+ *
|
|
||||||
+ * Copyright 2007 Michael Buesch <mb@bu3sch.de>
|
|
||||||
+ *
|
|
||||||
+ * Derived from the OHCI-PCI driver
|
|
||||||
+ * Copyright 1999 Roman Weissgaerber
|
|
||||||
+ * Copyright 2000-2002 David Brownell
|
|
||||||
+ * Copyright 1999 Linus Torvalds
|
|
||||||
+ * Copyright 1999 Gregory P. Smith
|
|
||||||
+ *
|
|
||||||
+ * Derived from the USBcore related parts of Broadcom-SB
|
|
||||||
+ * Copyright 2005 Broadcom Corporation
|
|
||||||
+ *
|
|
||||||
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
||||||
+ */
|
|
||||||
+#include <linux/ssb/ssb.h>
|
|
||||||
+
|
|
||||||
+
|
|
||||||
+#define SSB_OHCI_TMSLOW_HOSTMODE (1 << 29)
|
|
||||||
+
|
|
||||||
+struct ssb_ohci_device {
|
|
||||||
+ struct ohci_hcd ohci; /* _must_ be at the beginning. */
|
|
||||||
+
|
|
||||||
+ u32 enable_flags;
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
+static inline
|
|
||||||
+struct ssb_ohci_device *hcd_to_ssb_ohci(struct usb_hcd *hcd)
|
|
||||||
+{
|
|
||||||
+ return (struct ssb_ohci_device *)(hcd->hcd_priv);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+
|
|
||||||
+static int ssb_ohci_reset(struct usb_hcd *hcd)
|
|
||||||
+{
|
|
||||||
+ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
|
|
||||||
+ struct ohci_hcd *ohci = &ohcidev->ohci;
|
|
||||||
+ int err;
|
|
||||||
+
|
|
||||||
+ ohci_hcd_init(ohci);
|
|
||||||
+ err = ohci_init(ohci);
|
|
||||||
+
|
|
||||||
+ return err;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int ssb_ohci_start(struct usb_hcd *hcd)
|
|
||||||
+{
|
|
||||||
+ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
|
|
||||||
+ struct ohci_hcd *ohci = &ohcidev->ohci;
|
|
||||||
+ int err;
|
|
||||||
+
|
|
||||||
+ err = ohci_run(ohci);
|
|
||||||
+ if (err < 0) {
|
|
||||||
+ ohci_err(ohci, "can't start\n");
|
|
||||||
+ ohci_stop(hcd);
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ return err;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+#ifdef CONFIG_PM
|
|
||||||
+static int ssb_ohci_hcd_suspend(struct usb_hcd *hcd, pm_message_t message)
|
|
||||||
+{
|
|
||||||
+ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
|
|
||||||
+ struct ohci_hcd *ohci = &ohcidev->ohci;
|
|
||||||
+ unsigned long flags;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&ohci->lock, flags);
|
|
||||||
+
|
|
||||||
+ ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
|
|
||||||
+ ohci_readl(ohci, &ohci->regs->intrdisable); /* commit write */
|
|
||||||
+
|
|
||||||
+ /* make sure snapshot being resumed re-enumerates everything */
|
|
||||||
+ if (message.event == PM_EVENT_PRETHAW)
|
|
||||||
+ ohci_usb_reset(ohci);
|
|
||||||
+
|
|
||||||
+ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
|
||||||
+
|
|
||||||
+ spin_unlock_irqrestore(&ohci->lock, flags);
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int ssb_ohci_hcd_resume(struct usb_hcd *hcd)
|
|
||||||
+{
|
|
||||||
+ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
|
||||||
+ usb_hcd_resume_root_hub(hcd);
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+#endif /* CONFIG_PM */
|
|
||||||
+
|
|
||||||
+static const struct hc_driver ssb_ohci_hc_driver = {
|
|
||||||
+ .description = "ssb-usb-ohci",
|
|
||||||
+ .product_desc = "SSB OHCI Controller",
|
|
||||||
+ .hcd_priv_size = sizeof(struct ssb_ohci_device),
|
|
||||||
+
|
|
||||||
+ .irq = ohci_irq,
|
|
||||||
+ .flags = HCD_MEMORY | HCD_USB11,
|
|
||||||
+
|
|
||||||
+ .reset = ssb_ohci_reset,
|
|
||||||
+ .start = ssb_ohci_start,
|
|
||||||
+ .stop = ohci_stop,
|
|
||||||
+ .shutdown = ohci_shutdown,
|
|
||||||
+
|
|
||||||
+#ifdef CONFIG_PM
|
|
||||||
+ .suspend = ssb_ohci_hcd_suspend,
|
|
||||||
+ .resume = ssb_ohci_hcd_resume,
|
|
||||||
+#endif
|
|
||||||
+
|
|
||||||
+ .urb_enqueue = ohci_urb_enqueue,
|
|
||||||
+ .urb_dequeue = ohci_urb_dequeue,
|
|
||||||
+ .endpoint_disable = ohci_endpoint_disable,
|
|
||||||
+
|
|
||||||
+ .get_frame_number = ohci_get_frame,
|
|
||||||
+
|
|
||||||
+ .hub_status_data = ohci_hub_status_data,
|
|
||||||
+ .hub_control = ohci_hub_control,
|
|
||||||
+ .hub_irq_enable = ohci_rhsc_enable,
|
|
||||||
+ .bus_suspend = ohci_bus_suspend,
|
|
||||||
+ .bus_resume = ohci_bus_resume,
|
|
||||||
+
|
|
||||||
+ .start_port_reset = ohci_start_port_reset,
|
|
||||||
+};
|
|
||||||
+
|
|
||||||
+static void ssb_ohci_detach(struct ssb_device *dev)
|
|
||||||
+{
|
|
||||||
+ struct usb_hcd *hcd = ssb_get_drvdata(dev);
|
|
||||||
+
|
|
||||||
+ usb_remove_hcd(hcd);
|
|
||||||
+ iounmap(hcd->regs);
|
|
||||||
+ usb_put_hcd(hcd);
|
|
||||||
+ ssb_device_disable(dev, 0);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int ssb_ohci_attach(struct ssb_device *dev)
|
|
||||||
+{
|
|
||||||
+ struct ssb_ohci_device *ohcidev;
|
|
||||||
+ struct usb_hcd *hcd;
|
|
||||||
+ int err = -ENOMEM;
|
|
||||||
+ u32 tmp, flags = 0;
|
|
||||||
+
|
|
||||||
+ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
|
|
||||||
+ flags |= SSB_OHCI_TMSLOW_HOSTMODE;
|
|
||||||
+
|
|
||||||
+ ssb_device_enable(dev, flags);
|
|
||||||
+
|
|
||||||
+ hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
|
|
||||||
+ dev->dev->bus_id);
|
|
||||||
+ if (!hcd)
|
|
||||||
+ goto err_dev_disable;
|
|
||||||
+ ohcidev = hcd_to_ssb_ohci(hcd);
|
|
||||||
+ ohcidev->enable_flags = flags;
|
|
||||||
+
|
|
||||||
+ tmp = ssb_read32(dev, SSB_ADMATCH0);
|
|
||||||
+ hcd->rsrc_start = ssb_admatch_base(tmp);
|
|
||||||
+ hcd->rsrc_len = ssb_admatch_size(tmp);
|
|
||||||
+ hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
|
|
||||||
+ if (!hcd->regs)
|
|
||||||
+ goto err_put_hcd;
|
|
||||||
+ err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED);
|
|
||||||
+ if (err)
|
|
||||||
+ goto err_iounmap;
|
|
||||||
+
|
|
||||||
+ ssb_set_drvdata(dev, hcd);
|
|
||||||
+
|
|
||||||
+ return err;
|
|
||||||
+
|
|
||||||
+err_iounmap:
|
|
||||||
+ iounmap(hcd->regs);
|
|
||||||
+err_put_hcd:
|
|
||||||
+ usb_put_hcd(hcd);
|
|
||||||
+err_dev_disable:
|
|
||||||
+ ssb_device_disable(dev, flags);
|
|
||||||
+ return err;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int ssb_ohci_probe(struct ssb_device *dev,
|
|
||||||
+ const struct ssb_device_id *id)
|
|
||||||
+{
|
|
||||||
+ int err;
|
|
||||||
+ u16 chipid_top;
|
|
||||||
+
|
|
||||||
+ /* USBcores are only connected on embedded devices. */
|
|
||||||
+ chipid_top = (dev->bus->chip_id & 0xFF00);
|
|
||||||
+ if (chipid_top != 0x4700 && chipid_top != 0x5300)
|
|
||||||
+ return -ENODEV;
|
|
||||||
+
|
|
||||||
+ /* TODO: Probably need checks here; is the core connected? */
|
|
||||||
+
|
|
||||||
+ if (usb_disabled())
|
|
||||||
+ return -ENODEV;
|
|
||||||
+
|
|
||||||
+ /* We currently always attach SSB_DEV_USB11_HOSTDEV
|
|
||||||
+ * as HOST OHCI. If we want to attach it as Client device,
|
|
||||||
+ * we must branch here and call into the (yet to
|
|
||||||
+ * be written) Client mode driver. Same for remove(). */
|
|
||||||
+
|
|
||||||
+ err = ssb_ohci_attach(dev);
|
|
||||||
+
|
|
||||||
+ return err;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static void ssb_ohci_remove(struct ssb_device *dev)
|
|
||||||
+{
|
|
||||||
+ ssb_ohci_detach(dev);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+#ifdef CONFIG_PM
|
|
||||||
+
|
|
||||||
+static int ssb_ohci_suspend(struct ssb_device *dev, pm_message_t state)
|
|
||||||
+{
|
|
||||||
+ ssb_device_disable(dev, 0);
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int ssb_ohci_resume(struct ssb_device *dev)
|
|
||||||
+{
|
|
||||||
+ struct usb_hcd *hcd = ssb_get_drvdata(dev);
|
|
||||||
+ struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
|
|
||||||
+
|
|
||||||
+ ssb_device_enable(dev, ohcidev->enable_flags);
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+#else /* !CONFIG_PM */
|
|
||||||
+#define ssb_ohci_suspend NULL
|
|
||||||
+#define ssb_ohci_resume NULL
|
|
||||||
+#endif /* CONFIG_PM */
|
|
||||||
+
|
|
||||||
+static const struct ssb_device_id ssb_ohci_table[] = {
|
|
||||||
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
|
|
||||||
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
|
|
||||||
+ SSB_DEVTABLE_END
|
|
||||||
+};
|
|
||||||
+MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
|
|
||||||
+
|
|
||||||
+static struct ssb_driver ssb_ohci_driver = {
|
|
||||||
+ .name = KBUILD_MODNAME,
|
|
||||||
+ .id_table = ssb_ohci_table,
|
|
||||||
+ .probe = ssb_ohci_probe,
|
|
||||||
+ .remove = ssb_ohci_remove,
|
|
||||||
+ .suspend = ssb_ohci_suspend,
|
|
||||||
+ .resume = ssb_ohci_resume,
|
|
||||||
+};
|
|
||||||
@ -1,28 +0,0 @@
|
|||||||
From: Al Viro <viro@ftp.linux.org.uk>
|
|
||||||
Date: Sat, 13 Oct 2007 21:29:47 +0000 (+0100)
|
|
||||||
Subject: Fix ohci-ssb with !CONFIG_PM
|
|
||||||
X-Git-Tag: linux-2.6.24-rc1~57^2~38
|
|
||||||
X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fralf%2Flinux.git;a=commitdiff_plain;h=4735b37cf434175c2b7b36b3b68f1e60e8ec8527;hp=d773b33972a663cfaf066e966f87922a74088a1e
|
|
||||||
|
|
||||||
Fix ohci-ssb with !CONFIG_PM
|
|
||||||
|
|
||||||
ohci_bus_{suspend,resume} exists only if we have CONFIG_PM; do the same
|
|
||||||
thing as other subdrivers...
|
|
||||||
|
|
||||||
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
|
|
||||||
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
|
||||||
---
|
|
||||||
|
|
||||||
--- a/drivers/usb/host/ohci-ssb.c
|
|
||||||
+++ b/drivers/usb/host/ohci-ssb.c
|
|
||||||
@@ -117,8 +117,10 @@
|
|
||||||
.hub_status_data = ohci_hub_status_data,
|
|
||||||
.hub_control = ohci_hub_control,
|
|
||||||
.hub_irq_enable = ohci_rhsc_enable,
|
|
||||||
+#ifdef CONFIG_PM
|
|
||||||
.bus_suspend = ohci_bus_suspend,
|
|
||||||
.bus_resume = ohci_bus_resume,
|
|
||||||
+#endif
|
|
||||||
|
|
||||||
.start_port_reset = ohci_start_port_reset,
|
|
||||||
};
|
|
||||||
@ -1,72 +0,0 @@
|
|||||||
--- a/drivers/usb/host/ohci-ssb.c
|
|
||||||
+++ b/drivers/usb/host/ohci-ssb.c
|
|
||||||
@@ -142,10 +142,59 @@
|
|
||||||
int err = -ENOMEM;
|
|
||||||
u32 tmp, flags = 0;
|
|
||||||
|
|
||||||
- if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
|
|
||||||
+ /*
|
|
||||||
+ * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE
|
|
||||||
+ *
|
|
||||||
+ * The USB core requires a special bit to be set during core
|
|
||||||
+ * reset to enable host (OHCI) mode. Resetting the SB core in
|
|
||||||
+ * pcibios_enable_device() is a hack for compatibility with
|
|
||||||
+ * vanilla usb-ohci so that it does not have to know about
|
|
||||||
+ * SB. A driver that wants to use the USB core in device mode
|
|
||||||
+ * should know about SB and should reset the bit back to 0
|
|
||||||
+ * after calling pcibios_enable_device().
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+ if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
|
|
||||||
flags |= SSB_OHCI_TMSLOW_HOSTMODE;
|
|
||||||
+ ssb_device_enable(dev, flags);
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ /*
|
|
||||||
+ * USB 2.0 special considerations:
|
|
||||||
+ *
|
|
||||||
+ * 1. Since the core supports both OHCI and EHCI functions, it must
|
|
||||||
+ * only be reset once.
|
|
||||||
+ *
|
|
||||||
+ * 2. In addition to the standard SB reset sequence, the Host Control
|
|
||||||
+ * Register must be programmed to bring the USB core and various
|
|
||||||
+ * phy components out of reset.
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+ else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
|
|
||||||
+#warning FIX ME need test for core being up & exit
|
|
||||||
+ ssb_device_enable(dev, 0);
|
|
||||||
+ ssb_write32(dev, 0x200, 0x7ff);
|
|
||||||
+ udelay(1);
|
|
||||||
+ if (dev->id.revision == 1) { // bug in rev 1
|
|
||||||
+
|
|
||||||
+ /* Change Flush control reg */
|
|
||||||
+ tmp = ssb_read32(dev, 0x400);
|
|
||||||
+ tmp &= ~8;
|
|
||||||
+ ssb_write32(dev, 0x400, tmp);
|
|
||||||
+ tmp = ssb_read32(dev, 0x400);
|
|
||||||
+ printk("USB20H fcr: 0x%0x\n", tmp);
|
|
||||||
+
|
|
||||||
+ /* Change Shim control reg */
|
|
||||||
+ tmp = ssb_read32(dev, 0x304);
|
|
||||||
+ tmp &= ~0x100;
|
|
||||||
+ ssb_write32(dev, 0x304, tmp);
|
|
||||||
+ tmp = ssb_read32(dev, 0x304);
|
|
||||||
+ printk("USB20H shim: 0x%0x\n", tmp);
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
+ else
|
|
||||||
+ ssb_device_enable(dev, 0);
|
|
||||||
|
|
||||||
- ssb_device_enable(dev, flags);
|
|
||||||
|
|
||||||
hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
|
|
||||||
dev->dev->bus_id);
|
|
||||||
@@ -235,6 +284,7 @@
|
|
||||||
static const struct ssb_device_id ssb_ohci_table[] = {
|
|
||||||
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
|
|
||||||
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
|
|
||||||
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
|
|
||||||
SSB_DEVTABLE_END
|
|
||||||
};
|
|
||||||
MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
|
|
||||||
@ -1,14 +0,0 @@
|
|||||||
--- a/drivers/usb/host/ohci-ssb.c
|
|
||||||
+++ b/drivers/usb/host/ohci-ssb.c
|
|
||||||
@@ -195,6 +195,11 @@
|
|
||||||
else
|
|
||||||
ssb_device_enable(dev, 0);
|
|
||||||
|
|
||||||
+ /*
|
|
||||||
+ * Set dma mask - 32 bit mask is just an assumption
|
|
||||||
+ */
|
|
||||||
+ if (ssb_dma_set_mask(dev, DMA_32BIT_MASK))
|
|
||||||
+ return -EOPNOTSUPP;
|
|
||||||
|
|
||||||
hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
|
|
||||||
dev->dev->bus_id);
|
|
||||||
@ -1,11 +0,0 @@
|
|||||||
--- a/include/asm-mips/cacheflush.h
|
|
||||||
+++ b/include/asm-mips/cacheflush.h
|
|
||||||
@@ -32,7 +32,7 @@
|
|
||||||
extern void (*flush_cache_all)(void);
|
|
||||||
extern void (*__flush_cache_all)(void);
|
|
||||||
extern void (*flush_cache_mm)(struct mm_struct *mm);
|
|
||||||
-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
|
|
||||||
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
|
|
||||||
extern void (*flush_cache_range)(struct vm_area_struct *vma,
|
|
||||||
unsigned long start, unsigned long end);
|
|
||||||
extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
|
|
||||||
@ -1,67 +0,0 @@
|
|||||||
--- a/arch/mips/mm/init.c
|
|
||||||
+++ b/arch/mips/mm/init.c
|
|
||||||
@@ -205,31 +205,6 @@
|
|
||||||
preempt_check_resched();
|
|
||||||
}
|
|
||||||
|
|
||||||
-void copy_user_highpage(struct page *to, struct page *from,
|
|
||||||
- unsigned long vaddr, struct vm_area_struct *vma)
|
|
||||||
-{
|
|
||||||
- void *vfrom, *vto;
|
|
||||||
-
|
|
||||||
- vto = kmap_atomic(to, KM_USER1);
|
|
||||||
- if (cpu_has_dc_aliases && cpu_use_kmap_coherent && !Page_dcache_dirty(from)) {
|
|
||||||
- vfrom = kmap_coherent(from, vaddr);
|
|
||||||
- copy_page(vto, vfrom);
|
|
||||||
- kunmap_coherent();
|
|
||||||
- } else {
|
|
||||||
- vfrom = kmap_atomic(from, KM_USER0);
|
|
||||||
- copy_page(vto, vfrom);
|
|
||||||
- kunmap_atomic(vfrom, KM_USER0);
|
|
||||||
- }
|
|
||||||
- if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) ||
|
|
||||||
- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
|
||||||
- flush_data_cache_page((unsigned long)vto);
|
|
||||||
- kunmap_atomic(vto, KM_USER1);
|
|
||||||
- /* Make sure this page is cleared on other CPU's too before using it */
|
|
||||||
- smp_wmb();
|
|
||||||
-}
|
|
||||||
-
|
|
||||||
-EXPORT_SYMBOL(copy_user_highpage);
|
|
||||||
-
|
|
||||||
void copy_to_user_page(struct vm_area_struct *vma,
|
|
||||||
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
|
||||||
unsigned long len)
|
|
||||||
--- a/include/asm-mips/page.h
|
|
||||||
+++ b/include/asm-mips/page.h
|
|
||||||
@@ -35,6 +35,7 @@
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
|
|
||||||
#include <linux/pfn.h>
|
|
||||||
+#include <asm/cpu-features.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
@@ -67,13 +68,16 @@
|
|
||||||
flush_data_cache_page((unsigned long)addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
|
||||||
- struct page *to);
|
|
||||||
-struct vm_area_struct;
|
|
||||||
-extern void copy_user_highpage(struct page *to, struct page *from,
|
|
||||||
- unsigned long vaddr, struct vm_area_struct *vma);
|
|
||||||
+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
|
||||||
+ struct page *to)
|
|
||||||
+{
|
|
||||||
+ extern void (*flush_data_cache_page)(unsigned long addr);
|
|
||||||
|
|
||||||
-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
|
|
||||||
+ copy_page(vto, vfrom);
|
|
||||||
+ if (!cpu_has_ic_fills_f_dc ||
|
|
||||||
+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
|
|
||||||
+ flush_data_cache_page((unsigned long)vto);
|
|
||||||
+}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These are used to make use of C type-checking..
|
|
||||||
@ -1,31 +0,0 @@
|
|||||||
--- a/drivers/ide/pci/aec62xx.c
|
|
||||||
+++ b/drivers/ide/pci/aec62xx.c
|
|
||||||
@@ -248,7 +248,14 @@
|
|
||||||
|
|
||||||
static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
|
|
||||||
{
|
|
||||||
- unsigned long dma_base = pci_resource_start(dev, 4);
|
|
||||||
+ unsigned long dma_base;
|
|
||||||
+ int err;
|
|
||||||
+
|
|
||||||
+ err = pci_enable_device(dev);
|
|
||||||
+ if (err)
|
|
||||||
+ return err;
|
|
||||||
+
|
|
||||||
+ dma_base = pci_resource_start(dev, 4);
|
|
||||||
|
|
||||||
if (inb(dma_base + 2) & 0x10) {
|
|
||||||
d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ?
|
|
||||||
@@ -256,7 +263,11 @@
|
|
||||||
d->udma_mask = 0x7f; /* udma0-6 */
|
|
||||||
}
|
|
||||||
|
|
||||||
- return ide_setup_pci_device(dev, d);
|
|
||||||
+ err = ide_setup_pci_device(dev, d);
|
|
||||||
+ if(err)
|
|
||||||
+ pci_disable_device(dev);
|
|
||||||
+
|
|
||||||
+ return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
|
|
||||||
@ -1,117 +0,0 @@
|
|||||||
--- a/scripts/gen_initramfs_list.sh
|
|
||||||
+++ b/scripts/gen_initramfs_list.sh
|
|
||||||
@@ -287,7 +287,7 @@
|
|
||||||
if [ "${is_cpio_compressed}" = "compressed" ]; then
|
|
||||||
cat ${cpio_tfile} > ${output_file}
|
|
||||||
else
|
|
||||||
- cat ${cpio_tfile} | gzip -f -9 - > ${output_file}
|
|
||||||
+ lzma e -lc1 -lp2 -pb2 ${cpio_tfile} ${output_file}
|
|
||||||
fi
|
|
||||||
[ -z ${cpio_file} ] && rm ${cpio_tfile}
|
|
||||||
fi
|
|
||||||
--- a/init/initramfs.c
|
|
||||||
+++ b/init/initramfs.c
|
|
||||||
@@ -441,6 +441,69 @@
|
|
||||||
outcnt = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
+#include <linux/LzmaDecode.h>
|
|
||||||
+static int __init lzma_unzip(void)
|
|
||||||
+{
|
|
||||||
+ unsigned int i; /* temp value */
|
|
||||||
+ unsigned int lc; /* literal context bits */
|
|
||||||
+ unsigned int lp; /* literal pos state bits */
|
|
||||||
+ unsigned int pb; /* pos state bits */
|
|
||||||
+ unsigned int osize; /* uncompressed size */
|
|
||||||
+ unsigned char *workspace;
|
|
||||||
+ unsigned char* outputbuffer;
|
|
||||||
+ unsigned int outsizeProcessed = 0;
|
|
||||||
+ int workspace_size;
|
|
||||||
+ int res;
|
|
||||||
+
|
|
||||||
+ // lzma args
|
|
||||||
+ i = get_byte();
|
|
||||||
+ lc = i % 9, i = i / 9;
|
|
||||||
+ lp = i % 5, pb = i / 5;
|
|
||||||
+
|
|
||||||
+ // skip dictionary size
|
|
||||||
+ for (i = 0; i < 4; i++)
|
|
||||||
+ get_byte();
|
|
||||||
+
|
|
||||||
+ /* read the lower half of uncompressed size in the header */
|
|
||||||
+ osize = ((unsigned int)get_byte()) +
|
|
||||||
+ ((unsigned int)get_byte() << 8) +
|
|
||||||
+ ((unsigned int)get_byte() << 16) +
|
|
||||||
+ ((unsigned int)get_byte() << 24);
|
|
||||||
+
|
|
||||||
+ /* skip rest of the header (upper half of uncompressed size) */
|
|
||||||
+ for (i = 0; i < 4; i++)
|
|
||||||
+ get_byte();
|
|
||||||
+
|
|
||||||
+ workspace_size = ((LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp))) * sizeof(CProb)) + 100;
|
|
||||||
+ printk( KERN_NOTICE "initramfs: LZMA lc=%d,lp=%d,pb=%d,origSize=%d\n",
|
|
||||||
+ lc,lp,pb,osize);
|
|
||||||
+ outputbuffer = kmalloc(osize, GFP_KERNEL);
|
|
||||||
+ if (outputbuffer == 0) {
|
|
||||||
+ printk(KERN_ERR "initramfs: Couldn't allocate lzma output buffer\n");
|
|
||||||
+ return -1;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ workspace = kmalloc(workspace_size, GFP_KERNEL);
|
|
||||||
+ if (workspace == NULL) {
|
|
||||||
+ printk(KERN_ERR "initramfs: Couldn't allocate lzma workspace\n");
|
|
||||||
+ return -1;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ res = LzmaDecode(workspace, workspace_size, lc, lp, pb, inbuf + inptr, insize - inptr, outputbuffer, osize, &outsizeProcessed);
|
|
||||||
+ if( res != 0 ) {
|
|
||||||
+ panic( KERN_ERR "initramfs: Lzma decode failure\n");
|
|
||||||
+ return -1;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ flush_buffer(outputbuffer, outsizeProcessed);
|
|
||||||
+ inptr = insize;
|
|
||||||
+
|
|
||||||
+ kfree(outputbuffer);
|
|
||||||
+ kfree(workspace);
|
|
||||||
+ state = Reset;
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static char * __init unpack_to_rootfs(char *buf, unsigned len, int check_only)
|
|
||||||
{
|
|
||||||
int written;
|
|
||||||
@@ -475,12 +538,28 @@
|
|
||||||
inptr = 0;
|
|
||||||
outcnt = 0; /* bytes in output buffer */
|
|
||||||
bytes_out = 0;
|
|
||||||
- crc = (ulg)0xffffffffL; /* shift register contents */
|
|
||||||
- makecrc();
|
|
||||||
- gunzip();
|
|
||||||
- if (state != Reset)
|
|
||||||
+ if( inbuf[0] == 037 && ((inbuf[1] == 0213) || (inbuf[1] == 0236)))
|
|
||||||
+ {
|
|
||||||
+ printk( KERN_NOTICE "detected gzip initramfs\n");
|
|
||||||
+ crc = (ulg)0xffffffffL; /* shift register contents */
|
|
||||||
+ makecrc();
|
|
||||||
+ gunzip();
|
|
||||||
+ if (state != Reset)
|
|
||||||
error("junk in gzipped archive");
|
|
||||||
- this_header = saved_offset + inptr;
|
|
||||||
+ }
|
|
||||||
+ else if(!memcmp(inbuf+1, "\x00\x00\x80\x00", 4)) /* FIXME: hardcoded dictionary size */
|
|
||||||
+ {
|
|
||||||
+ printk( KERN_NOTICE "detected lzma initramfs\n");
|
|
||||||
+ lzma_unzip();
|
|
||||||
+ }
|
|
||||||
+ else
|
|
||||||
+ {
|
|
||||||
+ // skip forward ?
|
|
||||||
+ crc = (ulg)0xffffffffL; /* shift register contents */
|
|
||||||
+ makecrc();
|
|
||||||
+ gunzip();
|
|
||||||
+ }
|
|
||||||
+ this_header = saved_offset + inptr;
|
|
||||||
buf += inptr;
|
|
||||||
len -= inptr;
|
|
||||||
}
|
|
||||||
@ -1,63 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_pcicore.c
|
|
||||||
+++ b/drivers/ssb/driver_pcicore.c
|
|
||||||
@@ -66,6 +66,7 @@
|
|
||||||
base = &ssb_pcicore_pcibus_iobase;
|
|
||||||
else
|
|
||||||
base = &ssb_pcicore_pcibus_membase;
|
|
||||||
+ res->flags |= IORESOURCE_PCI_FIXED;
|
|
||||||
if (res->end) {
|
|
||||||
size = res->end - res->start + 1;
|
|
||||||
if (*base & (size - 1))
|
|
||||||
@@ -88,10 +89,12 @@
|
|
||||||
|
|
||||||
static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
|
|
||||||
{
|
|
||||||
+ u8 lat;
|
|
||||||
+
|
|
||||||
if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
|
|
||||||
return;
|
|
||||||
|
|
||||||
- ssb_printk(KERN_INFO "PCI: fixing up bridge\n");
|
|
||||||
+ ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
|
|
||||||
|
|
||||||
/* Enable PCI bridge bus mastering and memory space */
|
|
||||||
pci_set_master(dev);
|
|
||||||
@@ -101,7 +104,10 @@
|
|
||||||
pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
|
|
||||||
|
|
||||||
/* Make sure our latency is high enough to handle the devices behind us */
|
|
||||||
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
|
|
||||||
+ lat = 168;
|
|
||||||
+ ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
|
|
||||||
+ pci_name(dev), lat);
|
|
||||||
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
|
|
||||||
}
|
|
||||||
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
|
|
||||||
|
|
||||||
@@ -279,14 +285,14 @@
|
|
||||||
.name = "SSB PCIcore external memory",
|
|
||||||
.start = SSB_PCI_DMA,
|
|
||||||
.end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
|
|
||||||
- .flags = IORESOURCE_MEM,
|
|
||||||
+ .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct resource ssb_pcicore_io_resource = {
|
|
||||||
.name = "SSB PCIcore external I/O",
|
|
||||||
.start = 0x100,
|
|
||||||
.end = 0x7FF,
|
|
||||||
- .flags = IORESOURCE_IO,
|
|
||||||
+ .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct pci_controller ssb_pcicore_controller = {
|
|
||||||
@@ -344,7 +350,8 @@
|
|
||||||
/* Ok, ready to run, register it to the system.
|
|
||||||
* The following needs change, if we want to port hostmode
|
|
||||||
* to non-MIPS platform. */
|
|
||||||
- set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
|
|
||||||
+ ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
|
|
||||||
+ set_io_port_base(ssb_pcicore_controller.io_map_base);
|
|
||||||
/* Give some time to the PCI controller to configure itself with the new
|
|
||||||
* values. Not waiting at this point causes crashes of the machine. */
|
|
||||||
mdelay(10);
|
|
||||||
@ -1,19 +0,0 @@
|
|||||||
The SSB pcicore driver does create some MMIO resource collisions.
|
|
||||||
However, the pcicore PCI-fixup routine fixes these collisions afterwards.
|
|
||||||
Remove this sanity check for now until we find a better solution.
|
|
||||||
--mb
|
|
||||||
--- a/arch/mips/pci/pci.c
|
|
||||||
+++ b/arch/mips/pci/pci.c
|
|
||||||
@@ -177,10 +177,8 @@
|
|
||||||
continue;
|
|
||||||
|
|
||||||
r = &dev->resource[idx];
|
|
||||||
- if (!r->start && r->end) {
|
|
||||||
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
|
|
||||||
- return -EINVAL;
|
|
||||||
- }
|
|
||||||
+ if (!r->start && r->end)
|
|
||||||
+ printk(KERN_WARNING "PCI: Device %s resource collisions detected. Ignoring...\n", pci_name(dev));
|
|
||||||
if (r->flags & IORESOURCE_IO)
|
|
||||||
cmd |= PCI_COMMAND_IO;
|
|
||||||
if (r->flags & IORESOURCE_MEM)
|
|
||||||
@ -1,86 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_chipcommon.c
|
|
||||||
+++ b/drivers/ssb/driver_chipcommon.c
|
|
||||||
@@ -403,6 +403,7 @@
|
|
||||||
unsigned int irq;
|
|
||||||
u32 baud_base, div;
|
|
||||||
u32 i, n;
|
|
||||||
+ unsigned int ccrev = cc->dev->id.revision;
|
|
||||||
|
|
||||||
plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
|
|
||||||
irq = ssb_mips_irq(cc->dev);
|
|
||||||
@@ -414,14 +415,39 @@
|
|
||||||
chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
|
|
||||||
div = 1;
|
|
||||||
} else {
|
|
||||||
- if (cc->dev->id.revision >= 11) {
|
|
||||||
+ if (ccrev == 20) {
|
|
||||||
+ /* BCM5354 uses constant 25MHz clock */
|
|
||||||
+ baud_base = 25000000;
|
|
||||||
+ div = 48;
|
|
||||||
+ /* Set the override bit so we don't divide it */
|
|
||||||
+ chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
||||||
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
||||||
+ | SSB_CHIPCO_CORECTL_UARTCLK0);
|
|
||||||
+ } else if ((ccrev >= 11) && (ccrev != 15)) {
|
|
||||||
/* Fixed ALP clock */
|
|
||||||
baud_base = 20000000;
|
|
||||||
+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
|
||||||
+ /* FIXME: baud_base is different for devices with a PMU */
|
|
||||||
+ SSB_WARN_ON(1);
|
|
||||||
+ }
|
|
||||||
div = 1;
|
|
||||||
+ if (ccrev >= 21) {
|
|
||||||
+ /* Turn off UART clock before switching clocksource. */
|
|
||||||
+ chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
||||||
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
||||||
+ & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
|
|
||||||
+ }
|
|
||||||
/* Set the override bit so we don't divide it */
|
|
||||||
chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
||||||
- SSB_CHIPCO_CORECTL_UARTCLK0);
|
|
||||||
- } else if (cc->dev->id.revision >= 3) {
|
|
||||||
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
||||||
+ | SSB_CHIPCO_CORECTL_UARTCLK0);
|
|
||||||
+ if (ccrev >= 21) {
|
|
||||||
+ /* Re-enable the UART clock. */
|
|
||||||
+ chipco_write32(cc, SSB_CHIPCO_CORECTL,
|
|
||||||
+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
|
||||||
+ | SSB_CHIPCO_CORECTL_UARTCLKEN);
|
|
||||||
+ }
|
|
||||||
+ } else if (ccrev >= 3) {
|
|
||||||
/* Internal backplane clock */
|
|
||||||
baud_base = ssb_clockspeed(bus);
|
|
||||||
div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
|
|
||||||
@@ -433,7 +459,7 @@
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Clock source depends on strapping if UartClkOverride is unset */
|
|
||||||
- if ((cc->dev->id.revision > 0) &&
|
|
||||||
+ if ((ccrev > 0) &&
|
|
||||||
!(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
|
|
||||||
if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
|
|
||||||
SSB_CHIPCO_CAP_UARTCLK_INT) {
|
|
||||||
@@ -455,7 +481,7 @@
|
|
||||||
cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
|
|
||||||
uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
|
|
||||||
/* Offset changed at after rev 0 */
|
|
||||||
- if (cc->dev->id.revision == 0)
|
|
||||||
+ if (ccrev == 0)
|
|
||||||
uart_regs += (i * 8);
|
|
||||||
else
|
|
||||||
uart_regs += (i * 256);
|
|
||||||
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
|
||||||
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
|
||||||
@@ -51,9 +51,12 @@
|
|
||||||
#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
|
|
||||||
#define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */
|
|
||||||
#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
|
|
||||||
+#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
|
|
||||||
+#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
|
|
||||||
#define SSB_CHIPCO_CORECTL 0x0008
|
|
||||||
#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
|
|
||||||
#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
|
||||||
+#define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
|
|
||||||
#define SSB_CHIPCO_BIST 0x000C
|
|
||||||
#define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
|
|
||||||
#define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000
|
|
||||||
@ -1,119 +0,0 @@
|
|||||||
--- a/drivers/ssb/Kconfig
|
|
||||||
+++ b/drivers/ssb/Kconfig
|
|
||||||
@@ -105,6 +105,12 @@
|
|
||||||
|
|
||||||
If unsure, say N
|
|
||||||
|
|
||||||
+# Assumption: We are on embedded, if we compile the MIPS core.
|
|
||||||
+config SSB_EMBEDDED
|
|
||||||
+ bool
|
|
||||||
+ depends on SSB_DRIVER_MIPS
|
|
||||||
+ default y
|
|
||||||
+
|
|
||||||
config SSB_DRIVER_EXTIF
|
|
||||||
bool "SSB Broadcom EXTIF core driver (EXPERIMENTAL)"
|
|
||||||
depends on SSB_DRIVER_MIPS && EXPERIMENTAL
|
|
||||||
--- a/drivers/ssb/Makefile
|
|
||||||
+++ b/drivers/ssb/Makefile
|
|
||||||
@@ -1,5 +1,6 @@
|
|
||||||
# core
|
|
||||||
ssb-y += main.o scan.o
|
|
||||||
+ssb-$(CONFIG_SSB_EMBEDDED) += embedded.o
|
|
||||||
|
|
||||||
# host support
|
|
||||||
ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o
|
|
||||||
--- a/drivers/ssb/driver_extif.c
|
|
||||||
+++ b/drivers/ssb/driver_extif.c
|
|
||||||
@@ -37,6 +37,12 @@
|
|
||||||
return value;
|
|
||||||
}
|
|
||||||
|
|
||||||
+void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
|
||||||
+ u32 ticks)
|
|
||||||
+{
|
|
||||||
+ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
#ifdef CONFIG_SSB_SERIAL
|
|
||||||
static bool serial_exists(u8 *regs)
|
|
||||||
{
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/drivers/ssb/embedded.c
|
|
||||||
@@ -0,0 +1,26 @@
|
|
||||||
+/*
|
|
||||||
+ * Sonics Silicon Backplane
|
|
||||||
+ * Embedded systems support code
|
|
||||||
+ *
|
|
||||||
+ * Copyright 2005-2008, Broadcom Corporation
|
|
||||||
+ * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
|
|
||||||
+ *
|
|
||||||
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+#include <linux/ssb/ssb.h>
|
|
||||||
+#include <linux/ssb/ssb_embedded.h>
|
|
||||||
+
|
|
||||||
+
|
|
||||||
+int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks)
|
|
||||||
+{
|
|
||||||
+ if (ssb_chipco_available(&bus->chipco)) {
|
|
||||||
+ ssb_chipco_watchdog_timer_set(&bus->chipco, ticks);
|
|
||||||
+ return 0;
|
|
||||||
+ }
|
|
||||||
+ if (ssb_extif_available(&bus->extif)) {
|
|
||||||
+ ssb_extif_watchdog_timer_set(&bus->extif, ticks);
|
|
||||||
+ return 0;
|
|
||||||
+ }
|
|
||||||
+ return -ENODEV;
|
|
||||||
+}
|
|
||||||
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
|
||||||
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
|
||||||
@@ -360,6 +360,11 @@
|
|
||||||
u16 fast_pwrup_delay;
|
|
||||||
};
|
|
||||||
|
|
||||||
+static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
|
|
||||||
+{
|
|
||||||
+ return (cc->dev != NULL);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
|
|
||||||
|
|
||||||
#include <linux/pm.h>
|
|
||||||
--- a/include/linux/ssb/ssb_driver_extif.h
|
|
||||||
+++ b/include/linux/ssb/ssb_driver_extif.h
|
|
||||||
@@ -178,6 +178,9 @@
|
|
||||||
u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value);
|
|
||||||
|
|
||||||
+extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
|
||||||
+ u32 ticks);
|
|
||||||
+
|
|
||||||
#ifdef CONFIG_SSB_SERIAL
|
|
||||||
extern int ssb_extif_serial_init(struct ssb_extif *extif,
|
|
||||||
struct ssb_serial_port *ports);
|
|
||||||
@@ -201,5 +204,11 @@
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
+static inline
|
|
||||||
+void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
|
||||||
+ u32 ticks)
|
|
||||||
+{
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
#endif /* CONFIG_SSB_DRIVER_EXTIF */
|
|
||||||
#endif /* LINUX_SSB_EXTIFCORE_H_ */
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/include/linux/ssb/ssb_embedded.h
|
|
||||||
@@ -0,0 +1,10 @@
|
|
||||||
+#ifndef LINUX_SSB_EMBEDDED_H_
|
|
||||||
+#define LINUX_SSB_EMBEDDED_H_
|
|
||||||
+
|
|
||||||
+#include <linux/types.h>
|
|
||||||
+#include <linux/ssb/ssb.h>
|
|
||||||
+
|
|
||||||
+
|
|
||||||
+extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks);
|
|
||||||
+
|
|
||||||
+#endif /* LINUX_SSB_EMBEDDED_H_ */
|
|
||||||
@ -1,13 +0,0 @@
|
|||||||
--- a/drivers/ssb/main.c
|
|
||||||
+++ b/drivers/ssb/main.c
|
|
||||||
@@ -1163,7 +1163,9 @@
|
|
||||||
/* ssb must be initialized after PCI but before the ssb drivers.
|
|
||||||
* That means we must use some initcall between subsys_initcall
|
|
||||||
* and device_initcall. */
|
|
||||||
-fs_initcall(ssb_modinit);
|
|
||||||
+//FIXME on embedded we need to be early to make sure we can register
|
|
||||||
+// a new PCI bus, if needed.
|
|
||||||
+subsys_initcall(ssb_modinit);
|
|
||||||
|
|
||||||
static void __exit ssb_modexit(void)
|
|
||||||
{
|
|
||||||
@ -1,233 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_chipcommon.c
|
|
||||||
+++ b/drivers/ssb/driver_chipcommon.c
|
|
||||||
@@ -361,37 +361,31 @@
|
|
||||||
{
|
|
||||||
return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_chipco_gpio_in);
|
|
||||||
|
|
||||||
u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_chipco_gpio_out);
|
|
||||||
|
|
||||||
u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_chipco_gpio_outen);
|
|
||||||
|
|
||||||
u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_chipco_gpio_control);
|
|
||||||
|
|
||||||
u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_chipco_gpio_intmask);
|
|
||||||
|
|
||||||
u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_chipco_gpio_polarity);
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB_SERIAL
|
|
||||||
int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
|
|
||||||
--- a/drivers/ssb/driver_extif.c
|
|
||||||
+++ b/drivers/ssb/driver_extif.c
|
|
||||||
@@ -122,30 +122,25 @@
|
|
||||||
{
|
|
||||||
return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask;
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_extif_gpio_in);
|
|
||||||
|
|
||||||
u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
|
|
||||||
mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_extif_gpio_out);
|
|
||||||
|
|
||||||
u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
|
|
||||||
mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_extif_gpio_outen);
|
|
||||||
|
|
||||||
u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_extif_gpio_polarity);
|
|
||||||
|
|
||||||
u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
|
|
||||||
{
|
|
||||||
return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
|
|
||||||
}
|
|
||||||
-EXPORT_SYMBOL(ssb_extif_gpio_intmask);
|
|
||||||
--- a/drivers/ssb/embedded.c
|
|
||||||
+++ b/drivers/ssb/embedded.c
|
|
||||||
@@ -11,6 +11,8 @@
|
|
||||||
#include <linux/ssb/ssb.h>
|
|
||||||
#include <linux/ssb/ssb_embedded.h>
|
|
||||||
|
|
||||||
+#include "ssb_private.h"
|
|
||||||
+
|
|
||||||
|
|
||||||
int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks)
|
|
||||||
{
|
|
||||||
@@ -24,3 +26,107 @@
|
|
||||||
}
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
+
|
|
||||||
+u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
|
|
||||||
+{
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ u32 res = 0;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->gpio_lock, flags);
|
|
||||||
+ if (ssb_chipco_available(&bus->chipco))
|
|
||||||
+ res = ssb_chipco_gpio_in(&bus->chipco, mask);
|
|
||||||
+ else if (ssb_extif_available(&bus->extif))
|
|
||||||
+ res = ssb_extif_gpio_in(&bus->extif, mask);
|
|
||||||
+ else
|
|
||||||
+ SSB_WARN_ON(1);
|
|
||||||
+ spin_unlock_irqrestore(&bus->gpio_lock, flags);
|
|
||||||
+
|
|
||||||
+ return res;
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_gpio_in);
|
|
||||||
+
|
|
||||||
+u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ u32 res = 0;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->gpio_lock, flags);
|
|
||||||
+ if (ssb_chipco_available(&bus->chipco))
|
|
||||||
+ res = ssb_chipco_gpio_out(&bus->chipco, mask, value);
|
|
||||||
+ else if (ssb_extif_available(&bus->extif))
|
|
||||||
+ res = ssb_extif_gpio_out(&bus->extif, mask, value);
|
|
||||||
+ else
|
|
||||||
+ SSB_WARN_ON(1);
|
|
||||||
+ spin_unlock_irqrestore(&bus->gpio_lock, flags);
|
|
||||||
+
|
|
||||||
+ return res;
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_gpio_out);
|
|
||||||
+
|
|
||||||
+u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ u32 res = 0;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->gpio_lock, flags);
|
|
||||||
+ if (ssb_chipco_available(&bus->chipco))
|
|
||||||
+ res = ssb_chipco_gpio_outen(&bus->chipco, mask, value);
|
|
||||||
+ else if (ssb_extif_available(&bus->extif))
|
|
||||||
+ res = ssb_extif_gpio_outen(&bus->extif, mask, value);
|
|
||||||
+ else
|
|
||||||
+ SSB_WARN_ON(1);
|
|
||||||
+ spin_unlock_irqrestore(&bus->gpio_lock, flags);
|
|
||||||
+
|
|
||||||
+ return res;
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_gpio_outen);
|
|
||||||
+
|
|
||||||
+u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ u32 res = 0;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->gpio_lock, flags);
|
|
||||||
+ if (ssb_chipco_available(&bus->chipco))
|
|
||||||
+ res = ssb_chipco_gpio_control(&bus->chipco, mask, value);
|
|
||||||
+ spin_unlock_irqrestore(&bus->gpio_lock, flags);
|
|
||||||
+
|
|
||||||
+ return res;
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_gpio_control);
|
|
||||||
+
|
|
||||||
+u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ u32 res = 0;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->gpio_lock, flags);
|
|
||||||
+ if (ssb_chipco_available(&bus->chipco))
|
|
||||||
+ res = ssb_chipco_gpio_intmask(&bus->chipco, mask, value);
|
|
||||||
+ else if (ssb_extif_available(&bus->extif))
|
|
||||||
+ res = ssb_extif_gpio_intmask(&bus->extif, mask, value);
|
|
||||||
+ else
|
|
||||||
+ SSB_WARN_ON(1);
|
|
||||||
+ spin_unlock_irqrestore(&bus->gpio_lock, flags);
|
|
||||||
+
|
|
||||||
+ return res;
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_gpio_intmask);
|
|
||||||
+
|
|
||||||
+u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value)
|
|
||||||
+{
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ u32 res = 0;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->gpio_lock, flags);
|
|
||||||
+ if (ssb_chipco_available(&bus->chipco))
|
|
||||||
+ res = ssb_chipco_gpio_polarity(&bus->chipco, mask, value);
|
|
||||||
+ else if (ssb_extif_available(&bus->extif))
|
|
||||||
+ res = ssb_extif_gpio_polarity(&bus->extif, mask, value);
|
|
||||||
+ else
|
|
||||||
+ SSB_WARN_ON(1);
|
|
||||||
+ spin_unlock_irqrestore(&bus->gpio_lock, flags);
|
|
||||||
+
|
|
||||||
+ return res;
|
|
||||||
+}
|
|
||||||
+EXPORT_SYMBOL(ssb_gpio_polarity);
|
|
||||||
--- a/include/linux/ssb/ssb.h
|
|
||||||
+++ b/include/linux/ssb/ssb.h
|
|
||||||
@@ -283,6 +283,11 @@
|
|
||||||
/* Contents of the SPROM. */
|
|
||||||
struct ssb_sprom sprom;
|
|
||||||
|
|
||||||
+#ifdef CONFIG_SSB_EMBEDDED
|
|
||||||
+ /* Lock for GPIO register access. */
|
|
||||||
+ spinlock_t gpio_lock;
|
|
||||||
+#endif /* EMBEDDED */
|
|
||||||
+
|
|
||||||
/* Internal-only stuff follows. Do not touch. */
|
|
||||||
struct list_head list;
|
|
||||||
#ifdef CONFIG_SSB_DEBUG
|
|
||||||
--- a/include/linux/ssb/ssb_embedded.h
|
|
||||||
+++ b/include/linux/ssb/ssb_embedded.h
|
|
||||||
@@ -7,4 +7,12 @@
|
|
||||||
|
|
||||||
extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks);
|
|
||||||
|
|
||||||
+/* Generic GPIO API */
|
|
||||||
+u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask);
|
|
||||||
+u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value);
|
|
||||||
+u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value);
|
|
||||||
+u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value);
|
|
||||||
+u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value);
|
|
||||||
+u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value);
|
|
||||||
+
|
|
||||||
#endif /* LINUX_SSB_EMBEDDED_H_ */
|
|
||||||
--- a/drivers/ssb/main.c
|
|
||||||
+++ b/drivers/ssb/main.c
|
|
||||||
@@ -571,6 +571,9 @@
|
|
||||||
|
|
||||||
spin_lock_init(&bus->bar_lock);
|
|
||||||
INIT_LIST_HEAD(&bus->list);
|
|
||||||
+#ifdef CONFIG_SSB_EMBEDDED
|
|
||||||
+ spin_lock_init(&bus->gpio_lock);
|
|
||||||
+#endif
|
|
||||||
|
|
||||||
/* Powerup the bus */
|
|
||||||
err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
|
|
||||||
@ -1,108 +0,0 @@
|
|||||||
--- a/drivers/ssb/driver_pcicore.c
|
|
||||||
+++ b/drivers/ssb/driver_pcicore.c
|
|
||||||
@@ -11,6 +11,7 @@
|
|
||||||
#include <linux/ssb/ssb.h>
|
|
||||||
#include <linux/pci.h>
|
|
||||||
#include <linux/delay.h>
|
|
||||||
+#include <linux/ssb/ssb_embedded.h>
|
|
||||||
|
|
||||||
#include "ssb_private.h"
|
|
||||||
|
|
||||||
@@ -27,6 +28,18 @@
|
|
||||||
ssb_write32(pc->dev, offset, value);
|
|
||||||
}
|
|
||||||
|
|
||||||
+static inline
|
|
||||||
+u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
|
|
||||||
+{
|
|
||||||
+ return ssb_read16(pc->dev, offset);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static inline
|
|
||||||
+void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
|
|
||||||
+{
|
|
||||||
+ ssb_write16(pc->dev, offset, value);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
/**************************************************
|
|
||||||
* Code for hostmode operation.
|
|
||||||
**************************************************/
|
|
||||||
@@ -123,8 +136,10 @@
|
|
||||||
u32 addr = 0;
|
|
||||||
u32 tmp;
|
|
||||||
|
|
||||||
- if (unlikely(pc->cardbusmode && dev > 1))
|
|
||||||
+ /* We do only have one cardbus device behind the bridge. */
|
|
||||||
+ if (pc->cardbusmode && (dev >= 1))
|
|
||||||
goto out;
|
|
||||||
+
|
|
||||||
if (bus == 0) {
|
|
||||||
/* Type 0 transaction */
|
|
||||||
if (unlikely(dev >= SSB_PCI_SLOT_MAX))
|
|
||||||
@@ -324,7 +339,16 @@
|
|
||||||
pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
|
|
||||||
udelay(1); /* Assertion time demanded by the PCI standard */
|
|
||||||
|
|
||||||
- /*TODO cardbus mode */
|
|
||||||
+ if (pc->dev->bus->has_cardbus_slot) {
|
|
||||||
+ ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
|
|
||||||
+ pc->cardbusmode = 1;
|
|
||||||
+ /* GPIO 1 resets the bridge */
|
|
||||||
+ ssb_gpio_out(pc->dev->bus, 1, 1);
|
|
||||||
+ ssb_gpio_outen(pc->dev->bus, 1, 1);
|
|
||||||
+ pcicore_write16(pc, SSB_PCICORE_SPROM(0),
|
|
||||||
+ pcicore_read16(pc, SSB_PCICORE_SPROM(0))
|
|
||||||
+ | 0x0400);
|
|
||||||
+ }
|
|
||||||
|
|
||||||
/* 64MB I/O window */
|
|
||||||
pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
|
|
||||||
--- a/drivers/ssb/main.c
|
|
||||||
+++ b/drivers/ssb/main.c
|
|
||||||
@@ -559,6 +559,7 @@
|
|
||||||
goto out;
|
|
||||||
memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
|
|
||||||
memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
|
|
||||||
+ bus->has_cardbus_slot = iv.has_cardbus_slot;
|
|
||||||
out:
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
--- a/include/linux/ssb/ssb.h
|
|
||||||
+++ b/include/linux/ssb/ssb.h
|
|
||||||
@@ -282,6 +282,8 @@
|
|
||||||
struct ssb_boardinfo boardinfo;
|
|
||||||
/* Contents of the SPROM. */
|
|
||||||
struct ssb_sprom sprom;
|
|
||||||
+ /* If the board has a cardbus slot, this is set to true. */
|
|
||||||
+ bool has_cardbus_slot;
|
|
||||||
|
|
||||||
#ifdef CONFIG_SSB_EMBEDDED
|
|
||||||
/* Lock for GPIO register access. */
|
|
||||||
@@ -299,8 +301,13 @@
|
|
||||||
|
|
||||||
/* The initialization-invariants. */
|
|
||||||
struct ssb_init_invariants {
|
|
||||||
+ /* Versioning information about the PCB. */
|
|
||||||
struct ssb_boardinfo boardinfo;
|
|
||||||
+ /* The SPROM information. That's either stored in an
|
|
||||||
+ * EEPROM or NVRAM on the board. */
|
|
||||||
struct ssb_sprom sprom;
|
|
||||||
+ /* If the board has a cardbus slot, this is set to true. */
|
|
||||||
+ bool has_cardbus_slot;
|
|
||||||
};
|
|
||||||
/* Type of function to fetch the invariants. */
|
|
||||||
typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
|
|
||||||
--- a/include/linux/ssb/ssb_driver_pci.h
|
|
||||||
+++ b/include/linux/ssb/ssb_driver_pci.h
|
|
||||||
@@ -51,6 +51,11 @@
|
|
||||||
#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
|
|
||||||
#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
|
|
||||||
#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
|
|
||||||
+#define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
|
|
||||||
+#define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
|
|
||||||
+#define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
|
|
||||||
+#define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
|
|
||||||
+#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
|
|
||||||
|
|
||||||
/* SBtoPCIx */
|
|
||||||
#define SSB_PCICORE_SBTOPCI_MEM 0x00000000
|
|
||||||
@ -1,189 +0,0 @@
|
|||||||
Add support for 8bit reads/writes to SSB.
|
|
||||||
--- a/drivers/ssb/main.c
|
|
||||||
+++ b/drivers/ssb/main.c
|
|
||||||
@@ -507,6 +507,14 @@
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
+static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
|
|
||||||
+{
|
|
||||||
+ struct ssb_bus *bus = dev->bus;
|
|
||||||
+
|
|
||||||
+ offset += dev->core_index * SSB_CORE_SIZE;
|
|
||||||
+ return readb(bus->mmio + offset);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
|
|
||||||
{
|
|
||||||
struct ssb_bus *bus = dev->bus;
|
|
||||||
@@ -523,6 +531,14 @@
|
|
||||||
return readl(bus->mmio + offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
+static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
|
|
||||||
+{
|
|
||||||
+ struct ssb_bus *bus = dev->bus;
|
|
||||||
+
|
|
||||||
+ offset += dev->core_index * SSB_CORE_SIZE;
|
|
||||||
+ writeb(value, bus->mmio + offset);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
|
|
||||||
{
|
|
||||||
struct ssb_bus *bus = dev->bus;
|
|
||||||
@@ -541,8 +557,10 @@
|
|
||||||
|
|
||||||
/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
|
|
||||||
static const struct ssb_bus_ops ssb_ssb_ops = {
|
|
||||||
+ .read8 = ssb_ssb_read8,
|
|
||||||
.read16 = ssb_ssb_read16,
|
|
||||||
.read32 = ssb_ssb_read32,
|
|
||||||
+ .write8 = ssb_ssb_write8,
|
|
||||||
.write16 = ssb_ssb_write16,
|
|
||||||
.write32 = ssb_ssb_write32,
|
|
||||||
};
|
|
||||||
--- a/drivers/ssb/pci.c
|
|
||||||
+++ b/drivers/ssb/pci.c
|
|
||||||
@@ -572,6 +572,19 @@
|
|
||||||
}
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
+static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
|
|
||||||
+{
|
|
||||||
+ struct ssb_bus *bus = dev->bus;
|
|
||||||
+
|
|
||||||
+ if (unlikely(ssb_pci_assert_buspower(bus)))
|
|
||||||
+ return 0xFF;
|
|
||||||
+ if (unlikely(bus->mapped_device != dev)) {
|
|
||||||
+ if (unlikely(ssb_pci_switch_core(bus, dev)))
|
|
||||||
+ return 0xFF;
|
|
||||||
+ }
|
|
||||||
+ return ioread8(bus->mmio + offset);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
|
|
||||||
{
|
|
||||||
struct ssb_bus *bus = dev->bus;
|
|
||||||
@@ -598,6 +611,19 @@
|
|
||||||
return ioread32(bus->mmio + offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
+static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
|
|
||||||
+{
|
|
||||||
+ struct ssb_bus *bus = dev->bus;
|
|
||||||
+
|
|
||||||
+ if (unlikely(ssb_pci_assert_buspower(bus)))
|
|
||||||
+ return;
|
|
||||||
+ if (unlikely(bus->mapped_device != dev)) {
|
|
||||||
+ if (unlikely(ssb_pci_switch_core(bus, dev)))
|
|
||||||
+ return;
|
|
||||||
+ }
|
|
||||||
+ iowrite8(value, bus->mmio + offset);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
|
|
||||||
{
|
|
||||||
struct ssb_bus *bus = dev->bus;
|
|
||||||
@@ -626,8 +652,10 @@
|
|
||||||
|
|
||||||
/* Not "static", as it's used in main.c */
|
|
||||||
const struct ssb_bus_ops ssb_pci_ops = {
|
|
||||||
+ .read8 = ssb_pci_read8,
|
|
||||||
.read16 = ssb_pci_read16,
|
|
||||||
.read32 = ssb_pci_read32,
|
|
||||||
+ .write8 = ssb_pci_write8,
|
|
||||||
.write16 = ssb_pci_write16,
|
|
||||||
.write32 = ssb_pci_write32,
|
|
||||||
};
|
|
||||||
--- a/drivers/ssb/pcmcia.c
|
|
||||||
+++ b/drivers/ssb/pcmcia.c
|
|
||||||
@@ -172,6 +172,22 @@
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
+static u8 ssb_pcmcia_read8(struct ssb_device *dev, u16 offset)
|
|
||||||
+{
|
|
||||||
+ struct ssb_bus *bus = dev->bus;
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ int err;
|
|
||||||
+ u8 value = 0xFF;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->bar_lock, flags);
|
|
||||||
+ err = select_core_and_segment(dev, &offset);
|
|
||||||
+ if (likely(!err))
|
|
||||||
+ value = readb(bus->mmio + offset);
|
|
||||||
+ spin_unlock_irqrestore(&bus->bar_lock, flags);
|
|
||||||
+
|
|
||||||
+ return value;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
|
|
||||||
{
|
|
||||||
struct ssb_bus *bus = dev->bus;
|
|
||||||
@@ -206,6 +222,20 @@
|
|
||||||
return (lo | (hi << 16));
|
|
||||||
}
|
|
||||||
|
|
||||||
+static void ssb_pcmcia_write8(struct ssb_device *dev, u16 offset, u8 value)
|
|
||||||
+{
|
|
||||||
+ struct ssb_bus *bus = dev->bus;
|
|
||||||
+ unsigned long flags;
|
|
||||||
+ int err;
|
|
||||||
+
|
|
||||||
+ spin_lock_irqsave(&bus->bar_lock, flags);
|
|
||||||
+ err = select_core_and_segment(dev, &offset);
|
|
||||||
+ if (likely(!err))
|
|
||||||
+ writeb(value, bus->mmio + offset);
|
|
||||||
+ mmiowb();
|
|
||||||
+ spin_unlock_irqrestore(&bus->bar_lock, flags);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
|
|
||||||
{
|
|
||||||
struct ssb_bus *bus = dev->bus;
|
|
||||||
@@ -238,8 +268,10 @@
|
|
||||||
|
|
||||||
/* Not "static", as it's used in main.c */
|
|
||||||
const struct ssb_bus_ops ssb_pcmcia_ops = {
|
|
||||||
+ .read8 = ssb_pcmcia_read8,
|
|
||||||
.read16 = ssb_pcmcia_read16,
|
|
||||||
.read32 = ssb_pcmcia_read32,
|
|
||||||
+ .write8 = ssb_pcmcia_write8,
|
|
||||||
.write16 = ssb_pcmcia_write16,
|
|
||||||
.write32 = ssb_pcmcia_write32,
|
|
||||||
};
|
|
||||||
--- a/include/linux/ssb/ssb.h
|
|
||||||
+++ b/include/linux/ssb/ssb.h
|
|
||||||
@@ -72,8 +72,10 @@
|
|
||||||
/* Lowlevel read/write operations on the device MMIO.
|
|
||||||
* Internal, don't use that outside of ssb. */
|
|
||||||
struct ssb_bus_ops {
|
|
||||||
+ u8 (*read8)(struct ssb_device *dev, u16 offset);
|
|
||||||
u16 (*read16)(struct ssb_device *dev, u16 offset);
|
|
||||||
u32 (*read32)(struct ssb_device *dev, u16 offset);
|
|
||||||
+ void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
|
|
||||||
void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
|
|
||||||
void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
|
|
||||||
};
|
|
||||||
@@ -344,6 +346,10 @@
|
|
||||||
|
|
||||||
|
|
||||||
/* Device MMIO register read/write functions. */
|
|
||||||
+static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
|
|
||||||
+{
|
|
||||||
+ return dev->ops->read8(dev, offset);
|
|
||||||
+}
|
|
||||||
static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
|
|
||||||
{
|
|
||||||
return dev->ops->read16(dev, offset);
|
|
||||||
@@ -352,6 +358,10 @@
|
|
||||||
{
|
|
||||||
return dev->ops->read32(dev, offset);
|
|
||||||
}
|
|
||||||
+static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
|
|
||||||
+{
|
|
||||||
+ dev->ops->write8(dev, offset, value);
|
|
||||||
+}
|
|
||||||
static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
|
|
||||||
{
|
|
||||||
dev->ops->write16(dev, offset, value);
|
|
||||||
@ -1,159 +0,0 @@
|
|||||||
Allow registering PCI devices after early boot.
|
|
||||||
|
|
||||||
This is an ugly hack and needs to be rewritten before going upstream.
|
|
||||||
--- a/arch/mips/pci/pci.c
|
|
||||||
+++ b/arch/mips/pci/pci.c
|
|
||||||
@@ -21,6 +21,17 @@
|
|
||||||
*/
|
|
||||||
int pci_probe_only;
|
|
||||||
|
|
||||||
+/*
|
|
||||||
+ * Indicate whether PCI-bios init was already done.
|
|
||||||
+ */
|
|
||||||
+static int pcibios_init_done;
|
|
||||||
+
|
|
||||||
+/*
|
|
||||||
+ * The currently used busnumber.
|
|
||||||
+ */
|
|
||||||
+static int next_busno;
|
|
||||||
+static int need_domain_info;
|
|
||||||
+
|
|
||||||
#define PCI_ASSIGN_ALL_BUSSES 1
|
|
||||||
|
|
||||||
unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
|
|
||||||
@@ -75,8 +86,32 @@
|
|
||||||
res->start = start;
|
|
||||||
}
|
|
||||||
|
|
||||||
-void __devinit register_pci_controller(struct pci_controller *hose)
|
|
||||||
+/* Most MIPS systems have straight-forward swizzling needs. */
|
|
||||||
+
|
|
||||||
+static inline u8 bridge_swizzle(u8 pin, u8 slot)
|
|
||||||
+{
|
|
||||||
+ return (((pin - 1) + slot) % 4) + 1;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static u8 common_swizzle(struct pci_dev *dev, u8 *pinp)
|
|
||||||
{
|
|
||||||
+ u8 pin = *pinp;
|
|
||||||
+
|
|
||||||
+ while (dev->bus->parent) {
|
|
||||||
+ pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
|
|
||||||
+ /* Move up the chain of bridges. */
|
|
||||||
+ dev = dev->bus->self;
|
|
||||||
+ }
|
|
||||||
+ *pinp = pin;
|
|
||||||
+
|
|
||||||
+ /* The slot is the slot of the last bridge. */
|
|
||||||
+ return PCI_SLOT(dev->devfn);
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+void register_pci_controller(struct pci_controller *hose)
|
|
||||||
+{
|
|
||||||
+ struct pci_bus *bus;
|
|
||||||
+
|
|
||||||
if (request_resource(&iomem_resource, hose->mem_resource) < 0)
|
|
||||||
goto out;
|
|
||||||
if (request_resource(&ioport_resource, hose->io_resource) < 0) {
|
|
||||||
@@ -84,9 +119,6 @@
|
|
||||||
goto out;
|
|
||||||
}
|
|
||||||
|
|
||||||
- *hose_tail = hose;
|
|
||||||
- hose_tail = &hose->next;
|
|
||||||
-
|
|
||||||
/*
|
|
||||||
* Do not panic here but later - this might hapen before console init.
|
|
||||||
*/
|
|
||||||
@@ -94,41 +126,47 @@
|
|
||||||
printk(KERN_WARNING
|
|
||||||
"registering PCI controller with io_map_base unset\n");
|
|
||||||
}
|
|
||||||
- return;
|
|
||||||
|
|
||||||
-out:
|
|
||||||
- printk(KERN_WARNING
|
|
||||||
- "Skipping PCI bus scan due to resource conflict\n");
|
|
||||||
-}
|
|
||||||
+ if (pcibios_init_done) {
|
|
||||||
+ //TODO
|
|
||||||
|
|
||||||
-/* Most MIPS systems have straight-forward swizzling needs. */
|
|
||||||
+ printk(KERN_INFO "Registering a PCI bus after boot\n");
|
|
||||||
|
|
||||||
-static inline u8 bridge_swizzle(u8 pin, u8 slot)
|
|
||||||
-{
|
|
||||||
- return (((pin - 1) + slot) % 4) + 1;
|
|
||||||
-}
|
|
||||||
+ if (!hose->iommu)
|
|
||||||
+ PCI_DMA_BUS_IS_PHYS = 1;
|
|
||||||
|
|
||||||
-static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
|
|
||||||
-{
|
|
||||||
- u8 pin = *pinp;
|
|
||||||
+ bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
|
|
||||||
+ hose->bus = bus;
|
|
||||||
+ need_domain_info = need_domain_info || hose->index;
|
|
||||||
+ hose->need_domain_info = need_domain_info;
|
|
||||||
+ if (bus) {
|
|
||||||
+ next_busno = bus->subordinate + 1;
|
|
||||||
+ /* Don't allow 8-bit bus number overflow inside the hose -
|
|
||||||
+ reserve some space for bridges. */
|
|
||||||
+ if (next_busno > 224) {
|
|
||||||
+ next_busno = 0;
|
|
||||||
+ need_domain_info = 1;
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
+ if (!pci_probe_only)
|
|
||||||
+ pci_assign_unassigned_resources();
|
|
||||||
+ pci_fixup_irqs(common_swizzle, pcibios_map_irq);
|
|
||||||
+ } else {
|
|
||||||
+ *hose_tail = hose;
|
|
||||||
+ hose_tail = &hose->next;
|
|
||||||
+ }
|
|
||||||
|
|
||||||
- while (dev->bus->parent) {
|
|
||||||
- pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
|
|
||||||
- /* Move up the chain of bridges. */
|
|
||||||
- dev = dev->bus->self;
|
|
||||||
- }
|
|
||||||
- *pinp = pin;
|
|
||||||
+ return;
|
|
||||||
|
|
||||||
- /* The slot is the slot of the last bridge. */
|
|
||||||
- return PCI_SLOT(dev->devfn);
|
|
||||||
+out:
|
|
||||||
+ printk(KERN_WARNING
|
|
||||||
+ "Skipping PCI bus scan due to resource conflict\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
static int __init pcibios_init(void)
|
|
||||||
{
|
|
||||||
struct pci_controller *hose;
|
|
||||||
struct pci_bus *bus;
|
|
||||||
- int next_busno;
|
|
||||||
- int need_domain_info = 0;
|
|
||||||
|
|
||||||
/* Scan all of the recorded PCI controllers. */
|
|
||||||
for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
|
|
||||||
@@ -157,6 +195,7 @@
|
|
||||||
if (!pci_probe_only)
|
|
||||||
pci_assign_unassigned_resources();
|
|
||||||
pci_fixup_irqs(common_swizzle, pcibios_map_irq);
|
|
||||||
+ pcibios_init_done = 1;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
--- a/drivers/ssb/main.c
|
|
||||||
+++ b/drivers/ssb/main.c
|
|
||||||
@@ -1185,9 +1185,7 @@
|
|
||||||
/* ssb must be initialized after PCI but before the ssb drivers.
|
|
||||||
* That means we must use some initcall between subsys_initcall
|
|
||||||
* and device_initcall. */
|
|
||||||
-//FIXME on embedded we need to be early to make sure we can register
|
|
||||||
-// a new PCI bus, if needed.
|
|
||||||
-subsys_initcall(ssb_modinit);
|
|
||||||
+fs_initcall(ssb_modinit);
|
|
||||||
|
|
||||||
static void __exit ssb_modexit(void)
|
|
||||||
{
|
|
||||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user