mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-24 21:09:53 +02:00
fixup sibyte rtc support
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16094 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
kaloz
parent
03ee11b2ff
commit
ef61e721ca
@ -89,7 +89,11 @@ CONFIG_HW_RANDOM=m
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ=250
|
||||
CONFIG_HZ_250=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
# CONFIG_I2C is not set
|
||||
CONFIG_I2C_SIBYTE=y
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_IDE is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
CONFIG_INITRAMFS_ROOT_GID=0
|
||||
@ -163,6 +167,10 @@ CONFIG_RESOURCES_64BIT=y
|
||||
# CONFIG_RFKILL is not set
|
||||
# CONFIG_RIO is not set
|
||||
# CONFIG_RISCOM8 is not set
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_CMOS is not set
|
||||
# CONFIG_RTC_DRV_M41T80_WDT is not set
|
||||
CONFIG_RTC_DRV_M41T80=y
|
||||
CONFIG_SB1250_MAC=y
|
||||
# CONFIG_SB1_CERR_STALL is not set
|
||||
# CONFIG_SB1_CEX_ALWAYS_FATAL is not set
|
||||
|
||||
367
target/linux/sibyte/patches/003-m41t80_smbus.patch
Normal file
367
target/linux/sibyte/patches/003-m41t80_smbus.patch
Normal file
@ -0,0 +1,367 @@
|
||||
--- a/drivers/rtc/rtc-m41t80.c
|
||||
+++ b/drivers/rtc/rtc-m41t80.c
|
||||
@@ -6,6 +6,7 @@
|
||||
* Based on m41t00.c by Mark A. Greer <mgreer@mvista.com>
|
||||
*
|
||||
* 2006 (c) mycable GmbH
|
||||
+ * Copyright (c) 2008 Maciej W. Rozycki
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@@ -38,6 +39,8 @@
|
||||
#define M41T80_REG_DAY 5
|
||||
#define M41T80_REG_MON 6
|
||||
#define M41T80_REG_YEAR 7
|
||||
+#define M41T80_REG_CONTROL 8
|
||||
+#define M41T80_REG_WATCHDOG 9
|
||||
#define M41T80_REG_ALARM_MON 0xa
|
||||
#define M41T80_REG_ALARM_DAY 0xb
|
||||
#define M41T80_REG_ALARM_HOUR 0xc
|
||||
@@ -66,7 +69,7 @@
|
||||
#define M41T80_FEATURE_WD (1 << 3) /* Extra watchdog resolution */
|
||||
#define M41T80_FEATURE_SQ_ALT (1 << 4) /* RSx bits are in reg 4 */
|
||||
|
||||
-#define DRV_VERSION "0.05"
|
||||
+#define DRV_VERSION "0.06"
|
||||
|
||||
static const struct i2c_device_id m41t80_id[] = {
|
||||
{ "m41t62", M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT },
|
||||
@@ -88,31 +91,88 @@ struct m41t80_data {
|
||||
struct rtc_device *rtc;
|
||||
};
|
||||
|
||||
-static int m41t80_get_datetime(struct i2c_client *client,
|
||||
- struct rtc_time *tm)
|
||||
+
|
||||
+static int m41t80_write_block_data(struct i2c_client *client,
|
||||
+ u8 reg, u8 num, u8 *buf)
|
||||
{
|
||||
- u8 buf[M41T80_DATETIME_REG_SIZE], dt_addr[1] = { M41T80_REG_SEC };
|
||||
- struct i2c_msg msgs[] = {
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 1,
|
||||
- .buf = dt_addr,
|
||||
- },
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = I2C_M_RD,
|
||||
- .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC,
|
||||
- .buf = buf + M41T80_REG_SEC,
|
||||
- },
|
||||
- };
|
||||
+ int i, rc;
|
||||
|
||||
- if (i2c_transfer(client->adapter, msgs, 2) < 0) {
|
||||
- dev_err(&client->dev, "read error\n");
|
||||
- return -EIO;
|
||||
+ if (i2c_check_functionality(client->adapter,
|
||||
+ I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
|
||||
+ i = i2c_smbus_write_i2c_block_data(client, reg, num, buf);
|
||||
+ } else {
|
||||
+ for (i = 0; i < num; i++) {
|
||||
+ rc = i2c_smbus_write_byte_data(client, reg + i,
|
||||
+ buf[i]);
|
||||
+ if (rc < 0) {
|
||||
+ i = rc;
|
||||
+ goto out;
|
||||
+ }
|
||||
+ }
|
||||
}
|
||||
+out:
|
||||
+ return i;
|
||||
+}
|
||||
+
|
||||
+static int m41t80_read_block_data(struct i2c_client *client,
|
||||
+ u8 reg, u8 num, u8 *buf)
|
||||
+{
|
||||
+ int i, rc;
|
||||
+
|
||||
+ if (i2c_check_functionality(client->adapter,
|
||||
+ I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
|
||||
+ i = i2c_smbus_read_i2c_block_data(client, reg, num, buf);
|
||||
+ } else {
|
||||
+ for (i = 0; i < num; i++) {
|
||||
+ rc = i2c_smbus_read_byte_data(client, reg + i);
|
||||
+ if (rc < 0) {
|
||||
+ i = rc;
|
||||
+ goto out;
|
||||
+ }
|
||||
+ buf[i] = rc;
|
||||
+ }
|
||||
+ }
|
||||
+out:
|
||||
+ return i;
|
||||
+}
|
||||
+
|
||||
+static int m41t80_get_datetime(struct i2c_client *client, struct rtc_time *tm)
|
||||
+{
|
||||
+ u8 buf[M41T80_DATETIME_REG_SIZE];
|
||||
+ int loops = 2;
|
||||
+ int sec0, sec1;
|
||||
+
|
||||
+ /*
|
||||
+ * Time registers are latched by this chip if an I2C block
|
||||
+ * transfer is used, but with SMBus-style byte accesses
|
||||
+ * this is not the case, so check seconds for a wraparound.
|
||||
+ */
|
||||
+ do {
|
||||
+ if (m41t80_read_block_data(client, M41T80_REG_SEC,
|
||||
+ M41T80_DATETIME_REG_SIZE -
|
||||
+ M41T80_REG_SEC,
|
||||
+ buf + M41T80_REG_SEC) < 0) {
|
||||
+ dev_err(&client->dev, "read error\n");
|
||||
+ return -EIO;
|
||||
+ }
|
||||
+ if (i2c_check_functionality(client->adapter,
|
||||
+ I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
|
||||
+ sec1 = buf[M41T80_REG_SEC];
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ sec0 = buf[M41T80_REG_SEC];
|
||||
+ sec1 = i2c_smbus_read_byte_data(client, M41T80_REG_SEC);
|
||||
+ if (sec1 < 0) {
|
||||
+ dev_err(&client->dev, "read error\n");
|
||||
+ return -EIO;
|
||||
+ }
|
||||
+
|
||||
+ sec0 = bcd2bin(sec0 & 0x7f);
|
||||
+ sec1 = bcd2bin(sec1 & 0x7f);
|
||||
+ } while (sec1 < sec0 && --loops);
|
||||
|
||||
- tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f);
|
||||
+ tm->tm_sec = sec1;
|
||||
tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f);
|
||||
tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f);
|
||||
tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f);
|
||||
@@ -127,39 +187,16 @@ static int m41t80_get_datetime(struct i2
|
||||
/* Sets the given date and time to the real time clock. */
|
||||
static int m41t80_set_datetime(struct i2c_client *client, struct rtc_time *tm)
|
||||
{
|
||||
- u8 wbuf[1 + M41T80_DATETIME_REG_SIZE];
|
||||
- u8 *buf = &wbuf[1];
|
||||
- u8 dt_addr[1] = { M41T80_REG_SEC };
|
||||
- struct i2c_msg msgs_in[] = {
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 1,
|
||||
- .buf = dt_addr,
|
||||
- },
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = I2C_M_RD,
|
||||
- .len = M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC,
|
||||
- .buf = buf + M41T80_REG_SEC,
|
||||
- },
|
||||
- };
|
||||
- struct i2c_msg msgs[] = {
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 1 + M41T80_DATETIME_REG_SIZE,
|
||||
- .buf = wbuf,
|
||||
- },
|
||||
- };
|
||||
+ u8 buf[M41T80_DATETIME_REG_SIZE];
|
||||
|
||||
/* Read current reg values into buf[1..7] */
|
||||
- if (i2c_transfer(client->adapter, msgs_in, 2) < 0) {
|
||||
+ if (m41t80_read_block_data(client, M41T80_REG_SEC,
|
||||
+ M41T80_DATETIME_REG_SIZE - M41T80_REG_SEC,
|
||||
+ buf + M41T80_REG_SEC) < 0) {
|
||||
dev_err(&client->dev, "read error\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
- wbuf[0] = 0; /* offset into rtc's regs */
|
||||
/* Merge time-data and register flags into buf[0..7] */
|
||||
buf[M41T80_REG_SSEC] = 0;
|
||||
buf[M41T80_REG_SEC] =
|
||||
@@ -177,7 +214,8 @@ static int m41t80_set_datetime(struct i2
|
||||
/* assume 20YY not 19YY */
|
||||
buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year % 100);
|
||||
|
||||
- if (i2c_transfer(client->adapter, msgs, 1) != 1) {
|
||||
+ if (m41t80_write_block_data(client, M41T80_REG_SSEC,
|
||||
+ M41T80_DATETIME_REG_SIZE, buf) < 0) {
|
||||
dev_err(&client->dev, "write error\n");
|
||||
return -EIO;
|
||||
}
|
||||
@@ -251,34 +289,11 @@ err:
|
||||
static int m41t80_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t)
|
||||
{
|
||||
struct i2c_client *client = to_i2c_client(dev);
|
||||
- u8 wbuf[1 + M41T80_ALARM_REG_SIZE];
|
||||
- u8 *buf = &wbuf[1];
|
||||
+ u8 buf[M41T80_ALARM_REG_SIZE];
|
||||
u8 *reg = buf - M41T80_REG_ALARM_MON;
|
||||
- u8 dt_addr[1] = { M41T80_REG_ALARM_MON };
|
||||
- struct i2c_msg msgs_in[] = {
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 1,
|
||||
- .buf = dt_addr,
|
||||
- },
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = I2C_M_RD,
|
||||
- .len = M41T80_ALARM_REG_SIZE,
|
||||
- .buf = buf,
|
||||
- },
|
||||
- };
|
||||
- struct i2c_msg msgs[] = {
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 1 + M41T80_ALARM_REG_SIZE,
|
||||
- .buf = wbuf,
|
||||
- },
|
||||
- };
|
||||
|
||||
- if (i2c_transfer(client->adapter, msgs_in, 2) < 0) {
|
||||
+ if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON,
|
||||
+ M41T80_ALARM_REG_SIZE, buf) < 0) {
|
||||
dev_err(&client->dev, "read error\n");
|
||||
return -EIO;
|
||||
}
|
||||
@@ -288,7 +303,6 @@ static int m41t80_rtc_set_alarm(struct d
|
||||
reg[M41T80_REG_ALARM_MIN] = 0;
|
||||
reg[M41T80_REG_ALARM_SEC] = 0;
|
||||
|
||||
- wbuf[0] = M41T80_REG_ALARM_MON; /* offset into rtc's regs */
|
||||
reg[M41T80_REG_ALARM_SEC] |= t->time.tm_sec >= 0 ?
|
||||
bin2bcd(t->time.tm_sec) : 0x80;
|
||||
reg[M41T80_REG_ALARM_MIN] |= t->time.tm_min >= 0 ?
|
||||
@@ -302,7 +316,8 @@ static int m41t80_rtc_set_alarm(struct d
|
||||
else
|
||||
reg[M41T80_REG_ALARM_DAY] |= 0x40;
|
||||
|
||||
- if (i2c_transfer(client->adapter, msgs, 1) != 1) {
|
||||
+ if (m41t80_write_block_data(client, M41T80_REG_ALARM_MON,
|
||||
+ M41T80_ALARM_REG_SIZE, buf) < 0) {
|
||||
dev_err(&client->dev, "write error\n");
|
||||
return -EIO;
|
||||
}
|
||||
@@ -322,24 +337,10 @@ static int m41t80_rtc_read_alarm(struct
|
||||
{
|
||||
struct i2c_client *client = to_i2c_client(dev);
|
||||
u8 buf[M41T80_ALARM_REG_SIZE + 1]; /* all alarm regs and flags */
|
||||
- u8 dt_addr[1] = { M41T80_REG_ALARM_MON };
|
||||
u8 *reg = buf - M41T80_REG_ALARM_MON;
|
||||
- struct i2c_msg msgs[] = {
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 1,
|
||||
- .buf = dt_addr,
|
||||
- },
|
||||
- {
|
||||
- .addr = client->addr,
|
||||
- .flags = I2C_M_RD,
|
||||
- .len = M41T80_ALARM_REG_SIZE + 1,
|
||||
- .buf = buf,
|
||||
- },
|
||||
- };
|
||||
|
||||
- if (i2c_transfer(client->adapter, msgs, 2) < 0) {
|
||||
+ if (m41t80_read_block_data(client, M41T80_REG_ALARM_MON,
|
||||
+ M41T80_ALARM_REG_SIZE + 1, buf) < 0) {
|
||||
dev_err(&client->dev, "read error\n");
|
||||
return -EIO;
|
||||
}
|
||||
@@ -512,26 +513,16 @@ static int boot_flag;
|
||||
*/
|
||||
static void wdt_ping(void)
|
||||
{
|
||||
- unsigned char i2c_data[2];
|
||||
- struct i2c_msg msgs1[1] = {
|
||||
- {
|
||||
- .addr = save_client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 2,
|
||||
- .buf = i2c_data,
|
||||
- },
|
||||
- };
|
||||
- struct m41t80_data *clientdata = i2c_get_clientdata(save_client);
|
||||
+ u8 wdt = 0x80; /* WDS = 1 (0x80) */
|
||||
|
||||
- i2c_data[0] = 0x09; /* watchdog register */
|
||||
+ struct m41t80_data *clientdata = i2c_get_clientdata(save_client);
|
||||
|
||||
if (wdt_margin > 31)
|
||||
- i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */
|
||||
+ /* mulitplier = WD_TIMO / 4, resolution = 4s (0x3) */
|
||||
+ wdt |= (wdt_margin & 0xfc) | 0x3;
|
||||
else
|
||||
- /*
|
||||
- * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02)
|
||||
- */
|
||||
- i2c_data[1] = wdt_margin<<2 | 0x82;
|
||||
+ /* mulitplier = WD_TIMO, resolution = 1s (0x2) */
|
||||
+ wdt |= wdt_margin << 2 | 0x2;
|
||||
|
||||
/*
|
||||
* M41T65 has three bits for watchdog resolution. Don't set bit 7, as
|
||||
@@ -540,7 +531,7 @@ static void wdt_ping(void)
|
||||
if (clientdata->features & M41T80_FEATURE_WD)
|
||||
i2c_data[1] &= ~M41T80_WATCHDOG_RB2;
|
||||
|
||||
- i2c_transfer(save_client->adapter, msgs1, 1);
|
||||
+ i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, wdt);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -550,36 +541,8 @@ static void wdt_ping(void)
|
||||
*/
|
||||
static void wdt_disable(void)
|
||||
{
|
||||
- unsigned char i2c_data[2], i2c_buf[0x10];
|
||||
- struct i2c_msg msgs0[2] = {
|
||||
- {
|
||||
- .addr = save_client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 1,
|
||||
- .buf = i2c_data,
|
||||
- },
|
||||
- {
|
||||
- .addr = save_client->addr,
|
||||
- .flags = I2C_M_RD,
|
||||
- .len = 1,
|
||||
- .buf = i2c_buf,
|
||||
- },
|
||||
- };
|
||||
- struct i2c_msg msgs1[1] = {
|
||||
- {
|
||||
- .addr = save_client->addr,
|
||||
- .flags = 0,
|
||||
- .len = 2,
|
||||
- .buf = i2c_data,
|
||||
- },
|
||||
- };
|
||||
-
|
||||
- i2c_data[0] = 0x09;
|
||||
- i2c_transfer(save_client->adapter, msgs0, 2);
|
||||
-
|
||||
- i2c_data[0] = 0x09;
|
||||
- i2c_data[1] = 0x00;
|
||||
- i2c_transfer(save_client->adapter, msgs1, 1);
|
||||
+ i2c_smbus_read_byte_data(save_client, M41T80_REG_WATCHDOG);
|
||||
+ i2c_smbus_write_byte_data(save_client, M41T80_REG_WATCHDOG, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -772,8 +735,8 @@ static int m41t80_probe(struct i2c_clien
|
||||
struct rtc_time tm;
|
||||
struct m41t80_data *clientdata = NULL;
|
||||
|
||||
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C
|
||||
- | I2C_FUNC_SMBUS_BYTE_DATA)) {
|
||||
+ if (!i2c_check_functionality(client->adapter,
|
||||
+ I2C_FUNC_SMBUS_BYTE_DATA)) {
|
||||
rc = -ENODEV;
|
||||
goto exit;
|
||||
}
|
||||
531
target/linux/sibyte/patches/004-sibyte_rtc_cleanup.patch
Normal file
531
target/linux/sibyte/patches/004-sibyte_rtc_cleanup.patch
Normal file
@ -0,0 +1,531 @@
|
||||
--- a/arch/mips/sibyte/swarm/Makefile
|
||||
+++ b/arch/mips/sibyte/swarm/Makefile
|
||||
@@ -1,4 +1,3 @@
|
||||
-obj-y := platform.o setup.o rtc_xicor1241.o \
|
||||
- rtc_m41t81.o
|
||||
+obj-y := platform.o setup.o
|
||||
|
||||
obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o
|
||||
--- a/arch/mips/sibyte/swarm/rtc_m41t81.c
|
||||
+++ /dev/null
|
||||
@@ -1,233 +0,0 @@
|
||||
-/*
|
||||
- * Copyright (C) 2000, 2001 Broadcom Corporation
|
||||
- *
|
||||
- * Copyright (C) 2002 MontaVista Software Inc.
|
||||
- * Author: jsun@mvista.com or jsun@junsun.net
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or modify it
|
||||
- * under the terms of the GNU General Public License as published by the
|
||||
- * Free Software Foundation; either version 2 of the License, or (at your
|
||||
- * option) any later version.
|
||||
- *
|
||||
- */
|
||||
-#include <linux/bcd.h>
|
||||
-#include <linux/types.h>
|
||||
-#include <linux/time.h>
|
||||
-
|
||||
-#include <asm/time.h>
|
||||
-#include <asm/addrspace.h>
|
||||
-#include <asm/io.h>
|
||||
-
|
||||
-#include <asm/sibyte/sb1250.h>
|
||||
-#include <asm/sibyte/sb1250_regs.h>
|
||||
-#include <asm/sibyte/sb1250_smbus.h>
|
||||
-
|
||||
-
|
||||
-/* M41T81 definitions */
|
||||
-
|
||||
-/*
|
||||
- * Register bits
|
||||
- */
|
||||
-
|
||||
-#define M41T81REG_SC_ST 0x80 /* stop bit */
|
||||
-#define M41T81REG_HR_CB 0x40 /* century bit */
|
||||
-#define M41T81REG_HR_CEB 0x80 /* century enable bit */
|
||||
-#define M41T81REG_CTL_S 0x20 /* sign bit */
|
||||
-#define M41T81REG_CTL_FT 0x40 /* frequency test bit */
|
||||
-#define M41T81REG_CTL_OUT 0x80 /* output level */
|
||||
-#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */
|
||||
-#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */
|
||||
-#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
|
||||
-#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
|
||||
-#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
|
||||
-#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
|
||||
-#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
|
||||
-#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */
|
||||
-#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */
|
||||
-#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */
|
||||
-#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */
|
||||
-#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */
|
||||
-#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */
|
||||
-#define M41T81REG_AHR_HT 0x40 /* halt update bit */
|
||||
-#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */
|
||||
-#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */
|
||||
-#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */
|
||||
-#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */
|
||||
-#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */
|
||||
-#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */
|
||||
-#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */
|
||||
-#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */
|
||||
-
|
||||
-
|
||||
-/*
|
||||
- * Register numbers
|
||||
- */
|
||||
-
|
||||
-#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */
|
||||
-#define M41T81REG_SC 0x01 /* seconds */
|
||||
-#define M41T81REG_MN 0x02 /* minute */
|
||||
-#define M41T81REG_HR 0x03 /* hour/century */
|
||||
-#define M41T81REG_DY 0x04 /* day of week */
|
||||
-#define M41T81REG_DT 0x05 /* date of month */
|
||||
-#define M41T81REG_MO 0x06 /* month */
|
||||
-#define M41T81REG_YR 0x07 /* year */
|
||||
-#define M41T81REG_CTL 0x08 /* control */
|
||||
-#define M41T81REG_WD 0x09 /* watchdog */
|
||||
-#define M41T81REG_AMO 0x0A /* alarm: month */
|
||||
-#define M41T81REG_ADT 0x0B /* alarm: date */
|
||||
-#define M41T81REG_AHR 0x0C /* alarm: hour */
|
||||
-#define M41T81REG_AMN 0x0D /* alarm: minute */
|
||||
-#define M41T81REG_ASC 0x0E /* alarm: second */
|
||||
-#define M41T81REG_FLG 0x0F /* flags */
|
||||
-#define M41T81REG_SQW 0x13 /* square wave register */
|
||||
-
|
||||
-#define M41T81_CCR_ADDRESS 0x68
|
||||
-
|
||||
-#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
|
||||
-
|
||||
-static int m41t81_read(uint8_t addr)
|
||||
-{
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
|
||||
- __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
|
||||
- SMB_CSR(R_SMB_START));
|
||||
-
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
|
||||
- SMB_CSR(R_SMB_START));
|
||||
-
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
|
||||
- /* Clear error bit by writing a 1 */
|
||||
- __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
|
||||
- return -1;
|
||||
- }
|
||||
-
|
||||
- return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
|
||||
-}
|
||||
-
|
||||
-static int m41t81_write(uint8_t addr, int b)
|
||||
-{
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
|
||||
- __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
|
||||
- __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
|
||||
- SMB_CSR(R_SMB_START));
|
||||
-
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
|
||||
- /* Clear error bit by writing a 1 */
|
||||
- __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
|
||||
- return -1;
|
||||
- }
|
||||
-
|
||||
- /* read the same byte again to make sure it is written */
|
||||
- __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
|
||||
- SMB_CSR(R_SMB_START));
|
||||
-
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-int m41t81_set_time(unsigned long t)
|
||||
-{
|
||||
- struct rtc_time tm;
|
||||
- unsigned long flags;
|
||||
-
|
||||
- /* Note we don't care about the century */
|
||||
- rtc_time_to_tm(t, &tm);
|
||||
-
|
||||
- /*
|
||||
- * Note the write order matters as it ensures the correctness.
|
||||
- * When we write sec, 10th sec is clear. It is reasonable to
|
||||
- * believe we should finish writing min within a second.
|
||||
- */
|
||||
-
|
||||
- spin_lock_irqsave(&rtc_lock, flags);
|
||||
- tm.tm_sec = bin2bcd(tm.tm_sec);
|
||||
- m41t81_write(M41T81REG_SC, tm.tm_sec);
|
||||
-
|
||||
- tm.tm_min = bin2bcd(tm.tm_min);
|
||||
- m41t81_write(M41T81REG_MN, tm.tm_min);
|
||||
-
|
||||
- tm.tm_hour = bin2bcd(tm.tm_hour);
|
||||
- tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0);
|
||||
- m41t81_write(M41T81REG_HR, tm.tm_hour);
|
||||
-
|
||||
- /* tm_wday starts from 0 to 6 */
|
||||
- if (tm.tm_wday == 0) tm.tm_wday = 7;
|
||||
- tm.tm_wday = bin2bcd(tm.tm_wday);
|
||||
- m41t81_write(M41T81REG_DY, tm.tm_wday);
|
||||
-
|
||||
- tm.tm_mday = bin2bcd(tm.tm_mday);
|
||||
- m41t81_write(M41T81REG_DT, tm.tm_mday);
|
||||
-
|
||||
- /* tm_mon starts from 0, *ick* */
|
||||
- tm.tm_mon ++;
|
||||
- tm.tm_mon = bin2bcd(tm.tm_mon);
|
||||
- m41t81_write(M41T81REG_MO, tm.tm_mon);
|
||||
-
|
||||
- /* we don't do century, everything is beyond 2000 */
|
||||
- tm.tm_year %= 100;
|
||||
- tm.tm_year = bin2bcd(tm.tm_year);
|
||||
- m41t81_write(M41T81REG_YR, tm.tm_year);
|
||||
- spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
-
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-unsigned long m41t81_get_time(void)
|
||||
-{
|
||||
- unsigned int year, mon, day, hour, min, sec;
|
||||
- unsigned long flags;
|
||||
-
|
||||
- /*
|
||||
- * min is valid if two reads of sec are the same.
|
||||
- */
|
||||
- for (;;) {
|
||||
- spin_lock_irqsave(&rtc_lock, flags);
|
||||
- sec = m41t81_read(M41T81REG_SC);
|
||||
- min = m41t81_read(M41T81REG_MN);
|
||||
- if (sec == m41t81_read(M41T81REG_SC)) break;
|
||||
- spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
- }
|
||||
- hour = m41t81_read(M41T81REG_HR) & 0x3f;
|
||||
- day = m41t81_read(M41T81REG_DT);
|
||||
- mon = m41t81_read(M41T81REG_MO);
|
||||
- year = m41t81_read(M41T81REG_YR);
|
||||
- spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
-
|
||||
- sec = bcd2bin(sec);
|
||||
- min = bcd2bin(min);
|
||||
- hour = bcd2bin(hour);
|
||||
- day = bcd2bin(day);
|
||||
- mon = bcd2bin(mon);
|
||||
- year = bcd2bin(year);
|
||||
-
|
||||
- year += 2000;
|
||||
-
|
||||
- return mktime(year, mon, day, hour, min, sec);
|
||||
-}
|
||||
-
|
||||
-int m41t81_probe(void)
|
||||
-{
|
||||
- unsigned int tmp;
|
||||
-
|
||||
- /* enable chip if it is not enabled yet */
|
||||
- tmp = m41t81_read(M41T81REG_SC);
|
||||
- m41t81_write(M41T81REG_SC, tmp & 0x7f);
|
||||
-
|
||||
- return (m41t81_read(M41T81REG_SC) != -1);
|
||||
-}
|
||||
--- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
|
||||
+++ /dev/null
|
||||
@@ -1,210 +0,0 @@
|
||||
-/*
|
||||
- * Copyright (C) 2000, 2001 Broadcom Corporation
|
||||
- *
|
||||
- * Copyright (C) 2002 MontaVista Software Inc.
|
||||
- * Author: jsun@mvista.com or jsun@junsun.net
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or modify it
|
||||
- * under the terms of the GNU General Public License as published by the
|
||||
- * Free Software Foundation; either version 2 of the License, or (at your
|
||||
- * option) any later version.
|
||||
- */
|
||||
-#include <linux/bcd.h>
|
||||
-#include <linux/types.h>
|
||||
-#include <linux/time.h>
|
||||
-
|
||||
-#include <asm/time.h>
|
||||
-#include <asm/addrspace.h>
|
||||
-#include <asm/io.h>
|
||||
-
|
||||
-#include <asm/sibyte/sb1250.h>
|
||||
-#include <asm/sibyte/sb1250_regs.h>
|
||||
-#include <asm/sibyte/sb1250_smbus.h>
|
||||
-
|
||||
-
|
||||
-/* Xicor 1241 definitions */
|
||||
-
|
||||
-/*
|
||||
- * Register bits
|
||||
- */
|
||||
-
|
||||
-#define X1241REG_SR_BAT 0x80 /* currently on battery power */
|
||||
-#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
|
||||
-#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
|
||||
-#define X1241REG_SR_RTCF 0x01 /* clock failed */
|
||||
-#define X1241REG_BL_BP2 0x80 /* block protect 2 */
|
||||
-#define X1241REG_BL_BP1 0x40 /* block protect 1 */
|
||||
-#define X1241REG_BL_BP0 0x20 /* block protect 0 */
|
||||
-#define X1241REG_BL_WD1 0x10
|
||||
-#define X1241REG_BL_WD0 0x08
|
||||
-#define X1241REG_HR_MIL 0x80 /* military time format */
|
||||
-
|
||||
-/*
|
||||
- * Register numbers
|
||||
- */
|
||||
-
|
||||
-#define X1241REG_BL 0x10 /* block protect bits */
|
||||
-#define X1241REG_INT 0x11 /* */
|
||||
-#define X1241REG_SC 0x30 /* Seconds */
|
||||
-#define X1241REG_MN 0x31 /* Minutes */
|
||||
-#define X1241REG_HR 0x32 /* Hours */
|
||||
-#define X1241REG_DT 0x33 /* Day of month */
|
||||
-#define X1241REG_MO 0x34 /* Month */
|
||||
-#define X1241REG_YR 0x35 /* Year */
|
||||
-#define X1241REG_DW 0x36 /* Day of Week */
|
||||
-#define X1241REG_Y2K 0x37 /* Year 2K */
|
||||
-#define X1241REG_SR 0x3F /* Status register */
|
||||
-
|
||||
-#define X1241_CCR_ADDRESS 0x6F
|
||||
-
|
||||
-#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
|
||||
-
|
||||
-static int xicor_read(uint8_t addr)
|
||||
-{
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
|
||||
- __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
|
||||
- __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
|
||||
- SMB_CSR(R_SMB_START));
|
||||
-
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
|
||||
- SMB_CSR(R_SMB_START));
|
||||
-
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
|
||||
- /* Clear error bit by writing a 1 */
|
||||
- __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
|
||||
- return -1;
|
||||
- }
|
||||
-
|
||||
- return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
|
||||
-}
|
||||
-
|
||||
-static int xicor_write(uint8_t addr, int b)
|
||||
-{
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
|
||||
- __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
|
||||
- __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
|
||||
- SMB_CSR(R_SMB_START));
|
||||
-
|
||||
- while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
- ;
|
||||
-
|
||||
- if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
|
||||
- /* Clear error bit by writing a 1 */
|
||||
- __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
|
||||
- return -1;
|
||||
- } else {
|
||||
- return 0;
|
||||
- }
|
||||
-}
|
||||
-
|
||||
-int xicor_set_time(unsigned long t)
|
||||
-{
|
||||
- struct rtc_time tm;
|
||||
- int tmp;
|
||||
- unsigned long flags;
|
||||
-
|
||||
- rtc_time_to_tm(t, &tm);
|
||||
- tm.tm_year += 1900;
|
||||
-
|
||||
- spin_lock_irqsave(&rtc_lock, flags);
|
||||
- /* unlock writes to the CCR */
|
||||
- xicor_write(X1241REG_SR, X1241REG_SR_WEL);
|
||||
- xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
|
||||
-
|
||||
- /* trivial ones */
|
||||
- tm.tm_sec = bin2bcd(tm.tm_sec);
|
||||
- xicor_write(X1241REG_SC, tm.tm_sec);
|
||||
-
|
||||
- tm.tm_min = bin2bcd(tm.tm_min);
|
||||
- xicor_write(X1241REG_MN, tm.tm_min);
|
||||
-
|
||||
- tm.tm_mday = bin2bcd(tm.tm_mday);
|
||||
- xicor_write(X1241REG_DT, tm.tm_mday);
|
||||
-
|
||||
- /* tm_mon starts from 0, *ick* */
|
||||
- tm.tm_mon ++;
|
||||
- tm.tm_mon = bin2bcd(tm.tm_mon);
|
||||
- xicor_write(X1241REG_MO, tm.tm_mon);
|
||||
-
|
||||
- /* year is split */
|
||||
- tmp = tm.tm_year / 100;
|
||||
- tm.tm_year %= 100;
|
||||
- xicor_write(X1241REG_YR, tm.tm_year);
|
||||
- xicor_write(X1241REG_Y2K, tmp);
|
||||
-
|
||||
- /* hour is the most tricky one */
|
||||
- tmp = xicor_read(X1241REG_HR);
|
||||
- if (tmp & X1241REG_HR_MIL) {
|
||||
- /* 24 hour format */
|
||||
- tm.tm_hour = bin2bcd(tm.tm_hour);
|
||||
- tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f);
|
||||
- } else {
|
||||
- /* 12 hour format, with 0x2 for pm */
|
||||
- tmp = tmp & ~0x3f;
|
||||
- if (tm.tm_hour >= 12) {
|
||||
- tmp |= 0x20;
|
||||
- tm.tm_hour -= 12;
|
||||
- }
|
||||
- tm.tm_hour = bin2bcd(tm.tm_hour);
|
||||
- tmp |= tm.tm_hour;
|
||||
- }
|
||||
- xicor_write(X1241REG_HR, tmp);
|
||||
-
|
||||
- xicor_write(X1241REG_SR, 0);
|
||||
- spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
-
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-unsigned long xicor_get_time(void)
|
||||
-{
|
||||
- unsigned int year, mon, day, hour, min, sec, y2k;
|
||||
- unsigned long flags;
|
||||
-
|
||||
- spin_lock_irqsave(&rtc_lock, flags);
|
||||
- sec = xicor_read(X1241REG_SC);
|
||||
- min = xicor_read(X1241REG_MN);
|
||||
- hour = xicor_read(X1241REG_HR);
|
||||
-
|
||||
- if (hour & X1241REG_HR_MIL) {
|
||||
- hour &= 0x3f;
|
||||
- } else {
|
||||
- if (hour & 0x20)
|
||||
- hour = (hour & 0xf) + 0x12;
|
||||
- }
|
||||
-
|
||||
- day = xicor_read(X1241REG_DT);
|
||||
- mon = xicor_read(X1241REG_MO);
|
||||
- year = xicor_read(X1241REG_YR);
|
||||
- y2k = xicor_read(X1241REG_Y2K);
|
||||
- spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
-
|
||||
- sec = bcd2bin(sec);
|
||||
- min = bcd2bin(min);
|
||||
- hour = bcd2bin(hour);
|
||||
- day = bcd2bin(day);
|
||||
- mon = bcd2bin(mon);
|
||||
- year = bcd2bin(year);
|
||||
- y2k = bcd2bin(y2k);
|
||||
-
|
||||
- year += (y2k * 100);
|
||||
-
|
||||
- return mktime(year, mon, day, hour, min, sec);
|
||||
-}
|
||||
-
|
||||
-int xicor_probe(void)
|
||||
-{
|
||||
- return (xicor_read(X1241REG_SC) != -1);
|
||||
-}
|
||||
--- a/arch/mips/sibyte/swarm/setup.c
|
||||
+++ b/arch/mips/sibyte/swarm/setup.c
|
||||
@@ -56,14 +56,6 @@ extern void sb1250_setup(void);
|
||||
#error invalid SiByte board configuration
|
||||
#endif
|
||||
|
||||
-extern int xicor_probe(void);
|
||||
-extern int xicor_set_time(unsigned long);
|
||||
-extern unsigned long xicor_get_time(void);
|
||||
-
|
||||
-extern int m41t81_probe(void);
|
||||
-extern int m41t81_set_time(unsigned long);
|
||||
-extern unsigned long m41t81_get_time(void);
|
||||
-
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "SiByte " SIBYTE_BOARD_NAME;
|
||||
@@ -79,42 +71,14 @@ int swarm_be_handler(struct pt_regs *reg
|
||||
return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
|
||||
}
|
||||
|
||||
-enum swarm_rtc_type {
|
||||
- RTC_NONE,
|
||||
- RTC_XICOR,
|
||||
- RTC_M4LT81
|
||||
-};
|
||||
-
|
||||
-enum swarm_rtc_type swarm_rtc_type;
|
||||
-
|
||||
unsigned long read_persistent_clock(void)
|
||||
{
|
||||
- switch (swarm_rtc_type) {
|
||||
- case RTC_XICOR:
|
||||
- return xicor_get_time();
|
||||
-
|
||||
- case RTC_M4LT81:
|
||||
- return m41t81_get_time();
|
||||
-
|
||||
- case RTC_NONE:
|
||||
- default:
|
||||
- return mktime(2000, 1, 1, 0, 0, 0);
|
||||
- }
|
||||
+ return mktime(2000, 1, 1, 0, 0, 0);
|
||||
}
|
||||
|
||||
int rtc_mips_set_time(unsigned long sec)
|
||||
{
|
||||
- switch (swarm_rtc_type) {
|
||||
- case RTC_XICOR:
|
||||
- return xicor_set_time(sec);
|
||||
-
|
||||
- case RTC_M4LT81:
|
||||
- return m41t81_set_time(sec);
|
||||
-
|
||||
- case RTC_NONE:
|
||||
- default:
|
||||
- return -1;
|
||||
- }
|
||||
+ return -1;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
@@ -131,11 +95,6 @@ void __init plat_mem_setup(void)
|
||||
|
||||
board_be_handler = swarm_be_handler;
|
||||
|
||||
- if (xicor_probe())
|
||||
- swarm_rtc_type = RTC_XICOR;
|
||||
- if (m41t81_probe())
|
||||
- swarm_rtc_type = RTC_M4LT81;
|
||||
-
|
||||
printk("This kernel optimized for "
|
||||
#ifdef CONFIG_SIMULATION
|
||||
"simulation"
|
||||
Loading…
Reference in New Issue
Block a user