mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 09:56:47 +02:00
fix lantiq uboot to build lzma compressed bootloaders for eval kits
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27487 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
299fdf65d5
commit
f03072225e
@ -112,16 +112,16 @@ endef
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define Package/uboot-lantiq-$(BUILD_VARIANT)/install
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define Package/uboot-lantiq-$(BUILD_VARIANT)/install
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mkdir -p $(1)
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mkdir -p $(1)
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ifneq ($(findstring flash,$(BUILD_VARIANT)),)
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ifneq ($(findstring ramboot,$(BUILD_VARIANT)),)
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dd \
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if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot-bootstrap.bin \
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of=$(1)/u-boot-bootstrap.bin \
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bs=64k conv=sync
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else
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dd \
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dd \
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if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.bin \
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if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.bin \
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of=$(1)/u-boot.bin \
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of=$(1)/u-boot.bin \
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bs=64k conv=sync
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bs=64k conv=sync
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else
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dd \
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if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot-bootstrap.bin \
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of=$(1)/u-boot-bootstrap.bin \
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bs=64k conv=sync
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endif
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endif
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ifneq ($(findstring ramboot,$(BUILD_VARIANT)),)
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ifneq ($(findstring ramboot,$(BUILD_VARIANT)),)
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if [ -e $(DDR_CONFIG_$(BUILD_VARIANT)).conf ]; then \
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if [ -e $(DDR_CONFIG_$(BUILD_VARIANT)).conf ]; then \
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@ -24,19 +24,34 @@
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include $(TOPDIR)/config.mk
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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LIB = $(obj)lib$(BOARD).a
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BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
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BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
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#COBJS := $(BOARD).o
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COBJS-y += danube.o
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COBJS-y += danube.o
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SOBJS = lowlevel_init.o pmuenable.o
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SOBJS = lowlevel_init.o pmuenable.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
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BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
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BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
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SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
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OBJS := $(addprefix $(obj),$(COBJS-y))
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
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BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
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all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
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$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
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#########################################################################
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#########################################################################
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# defines $(obj).depend target
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# defines $(obj).depend target
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@ -26,35 +26,15 @@
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#
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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ifdef CONFIG_LZMA_BOOTSTRAP
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ifdef CONFIG_BOOTSTRAP
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TEXT_BASE = 0x80001000
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ifdef BUILD_BOOTSTRAP
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CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
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CONFIG_SYS_RAMBOOT = y
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$(info BUILD_BOOTSTRAP )
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#TEXT_BASE = 0xB0000000
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TEXT_BASE = 0x80010000
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else # BUILD_BOOTSTRAP
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ifndef TEXT_BASE
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$(info redefine TEXT_BASE = 0x80040000 )
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TEXT_BASE = 0x80040000
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endif
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endif # BUILD_BOOTSTRAP
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else
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else
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ifdef BUILD_BOOTSTRAP
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$(error BUILD_BOOTSTRAP but not enabled in config)
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endif
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ifndef TEXT_BASE
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ifndef TEXT_BASE
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## Standard: boot from ebu
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$(info redefine TEXT_BASE = 0xB0000000 )
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$(info redefine TEXT_BASE = 0xB0000000 )
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TEXT_BASE = 0xB0000000
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TEXT_BASE = 0xB0000000
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## For testing: boot from RAM
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# TEXT_BASE = 0x80100000
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endif
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endif
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endif # CONFIG_LZMA_BOOTSTRAP
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endif
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@ -0,0 +1,48 @@
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/*
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* (C) Copyright 2010 Industrie Dial Face S.p.A.
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* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
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*
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* (C) Copyright 2007
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* Vlad Lungu vlad.lungu@windriver.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/mipsregs.h>
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#include <asm/io.h>
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phys_size_t bootstrap_initdram(int board_type)
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{
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/* Sdram is setup by assembler code */
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/* If memory could be changed, we should return the true value here */
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return CONFIG_SYS_MAX_RAM;
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}
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int bootstrap_checkboard(void)
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{
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return 0;
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}
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int bootstrap_misc_init_r(void)
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{
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set_io_port_base(0);
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return 0;
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}
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@ -0,0 +1,606 @@
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/*
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* Memory sub-system initialization code for Danube board.
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* Andre Messerschmidt
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* Copyright (c) 2005 Infineon Technologies AG
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*
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* Based on Inca-IP code
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* History:
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peng liu May 25, 2006, for PLL setting after reset, 05252006
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#if defined(CONFIG_USE_DDR_RAM)
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#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
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#include "ddr_settings_r111.h"
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#define DDR111
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#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
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#include "ddr_settings_r166.h"
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#define DDR166
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#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
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#include "ddr_settings_e111.h"
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#define DDR111
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#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
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#include "ddr_settings_e166.h"
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#define DDR166
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#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
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#include "ddr_settings_PROMOSDDR400.h"
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#define DDR166
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#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
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#include "ddr_settings_Samsung_166.h"
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#define DDR166
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#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
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#include "ddr_settings_psc_166.h"
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#define DDR166
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#else
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#warning "missing definition for ddr_settings.h, use default!"
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#include "ddr_settings.h"
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#endif
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#endif /* CONFIG_USE_DDR_RAM */
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#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
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#error "missing include of ddr_settings.h"
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#endif
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#define EBU_MODUL_BASE 0xBE105300
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#define EBU_CLC(value) 0x0000(value)
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#define EBU_CON(value) 0x0010(value)
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#define EBU_ADDSEL0(value) 0x0020(value)
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#define EBU_ADDSEL1(value) 0x0024(value)
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#define EBU_ADDSEL2(value) 0x0028(value)
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#define EBU_ADDSEL3(value) 0x002C(value)
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#define EBU_BUSCON0(value) 0x0060(value)
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#define EBU_BUSCON1(value) 0x0064(value)
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#define EBU_BUSCON2(value) 0x0068(value)
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#define EBU_BUSCON3(value) 0x006C(value)
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#define MC_MODUL_BASE 0xBF800000
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#define MC_ERRCAUSE(value) 0x0010(value)
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#define MC_ERRADDR(value) 0x0020(value)
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#define MC_CON(value) 0x0060(value)
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#define MC_SRAM_ENABLE 0x00000004
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#define MC_SDRAM_ENABLE 0x00000002
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#define MC_DDRRAM_ENABLE 0x00000001
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#define MC_SDR_MODUL_BASE 0xBF800200
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#define MC_IOGP(value) 0x0000(value)
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#define MC_CTRLENA(value) 0x0010(value)
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#define MC_MRSCODE(value) 0x0020(value)
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#define MC_CFGDW(value) 0x0030(value)
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#define MC_CFGPB0(value) 0x0040(value)
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#define MC_LATENCY(value) 0x0080(value)
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#define MC_TREFRESH(value) 0x0090(value)
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#define MC_SELFRFSH(value) 0x00A0(value)
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#define MC_DDR_MODUL_BASE 0xBF801000
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#define MC_DC00(value) 0x0000(value)
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#define MC_DC01(value) 0x0010(value)
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#define MC_DC02(value) 0x0020(value)
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#define MC_DC03(value) 0x0030(value)
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#define MC_DC04(value) 0x0040(value)
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#define MC_DC05(value) 0x0050(value)
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#define MC_DC06(value) 0x0060(value)
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#define MC_DC07(value) 0x0070(value)
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#define MC_DC08(value) 0x0080(value)
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#define MC_DC09(value) 0x0090(value)
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#define MC_DC10(value) 0x00A0(value)
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#define MC_DC11(value) 0x00B0(value)
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#define MC_DC12(value) 0x00C0(value)
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#define MC_DC13(value) 0x00D0(value)
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#define MC_DC14(value) 0x00E0(value)
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#define MC_DC15(value) 0x00F0(value)
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#define MC_DC16(value) 0x0100(value)
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#define MC_DC17(value) 0x0110(value)
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#define MC_DC18(value) 0x0120(value)
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#define MC_DC19(value) 0x0130(value)
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#define MC_DC20(value) 0x0140(value)
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#define MC_DC21(value) 0x0150(value)
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#define MC_DC22(value) 0x0160(value)
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#define MC_DC23(value) 0x0170(value)
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#define MC_DC24(value) 0x0180(value)
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#define MC_DC25(value) 0x0190(value)
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#define MC_DC26(value) 0x01A0(value)
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#define MC_DC27(value) 0x01B0(value)
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#define MC_DC28(value) 0x01C0(value)
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#define MC_DC29(value) 0x01D0(value)
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#define MC_DC30(value) 0x01E0(value)
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#define MC_DC31(value) 0x01F0(value)
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#define MC_DC32(value) 0x0200(value)
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#define MC_DC33(value) 0x0210(value)
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#define MC_DC34(value) 0x0220(value)
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#define MC_DC35(value) 0x0230(value)
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#define MC_DC36(value) 0x0240(value)
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#define MC_DC37(value) 0x0250(value)
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#define MC_DC38(value) 0x0260(value)
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#define MC_DC39(value) 0x0270(value)
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#define MC_DC40(value) 0x0280(value)
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#define MC_DC41(value) 0x0290(value)
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#define MC_DC42(value) 0x02A0(value)
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#define MC_DC43(value) 0x02B0(value)
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#define MC_DC44(value) 0x02C0(value)
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#define MC_DC45(value) 0x02D0(value)
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#define MC_DC46(value) 0x02E0(value)
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#define RCU_OFFSET 0xBF203000
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#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
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#define RCU_STS (RCU_OFFSET + 0x0014)
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#define CGU_OFFSET 0xBF103000
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#define PLL0_CFG (CGU_OFFSET + 0x0004)
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#define PLL1_CFG (CGU_OFFSET + 0x0008)
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#define PLL2_CFG (CGU_OFFSET + 0x000C)
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#define CGU_SYS (CGU_OFFSET + 0x0010)
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#define CGU_UPDATE (CGU_OFFSET + 0x0014)
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#define IF_CLK (CGU_OFFSET + 0x0018)
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#define CGU_SMD (CGU_OFFSET + 0x0020)
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#define CGU_CT1SR (CGU_OFFSET + 0x0028)
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#define CGU_CT2SR (CGU_OFFSET + 0x002C)
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#define CGU_PCMCR (CGU_OFFSET + 0x0030)
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#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
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#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
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#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
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#define CLK_MEASURE (CGU_OFFSET + 0x003C)
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//05252006
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#define pll0_35MHz_CONFIG 0x9D861059
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#define pll1_35MHz_CONFIG 0x1A260CD9
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#define pll2_35MHz_CONFIG 0x8000f1e5
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#define pll0_36MHz_CONFIG 0x1000125D
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#define pll1_36MHz_CONFIG 0x1B1E0C99
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#define pll2_36MHz_CONFIG 0x8002f2a1
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//05252006
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//06063001-joelin disable the PCI CFRAME mask -start
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/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
|
||||||
|
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
|
||||||
|
|
||||||
|
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
|
||||||
|
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
|
||||||
|
*/
|
||||||
|
#define PCI_CR_PR_OFFSET 0xBE105400
|
||||||
|
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
|
||||||
|
#define PCI_CONFIG_SPACE 0xB7000000
|
||||||
|
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
|
||||||
|
//06063001-joelin disable the PCI CFRAME mask -end
|
||||||
|
.set noreorder
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void ebu_init(void)
|
||||||
|
*/
|
||||||
|
.globl ebu_init
|
||||||
|
.ent ebu_init
|
||||||
|
ebu_init:
|
||||||
|
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
|
||||||
|
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
|
||||||
|
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
|
||||||
|
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
|
||||||
|
|
||||||
|
li t1, EBU_MODUL_BASE
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL0)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL0
|
||||||
|
sw t2, EBU_ADDSEL0(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL1)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL1
|
||||||
|
sw t2, EBU_ADDSEL1(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL2)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL2
|
||||||
|
sw t2, EBU_ADDSEL2(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL3)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL3
|
||||||
|
sw t2, EBU_ADDSEL3(t1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_EBU_BUSCON0)
|
||||||
|
li t2, CONFIG_EBU_BUSCON0
|
||||||
|
sw t2, EBU_BUSCON0(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_BUSCON1)
|
||||||
|
li t2, CONFIG_EBU_BUSCON1
|
||||||
|
sw t2, EBU_BUSCON1(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_BUSCON2)
|
||||||
|
li t2, CONFIG_EBU_BUSCON2
|
||||||
|
sw t2, EBU_BUSCON2(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_BUSCON3)
|
||||||
|
li t2, CONFIG_EBU_BUSCON3
|
||||||
|
sw t2, EBU_BUSCON3(t1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end ebu_init
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void cgu_init(long)
|
||||||
|
*
|
||||||
|
* a0 has the clock value
|
||||||
|
*/
|
||||||
|
.globl cgu_init
|
||||||
|
.ent cgu_init
|
||||||
|
cgu_init:
|
||||||
|
li t2, CGU_SYS
|
||||||
|
lw t2,0(t2)
|
||||||
|
beq t2,a0,freq_up2date
|
||||||
|
nop
|
||||||
|
|
||||||
|
li t2, RCU_STS
|
||||||
|
lw t2, 0(t2)
|
||||||
|
and t2,0x00020000
|
||||||
|
beq t2,0x00020000,boot_36MHZ
|
||||||
|
nop
|
||||||
|
//05252006
|
||||||
|
li t1, PLL0_CFG
|
||||||
|
li t2, pll0_35MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL1_CFG
|
||||||
|
li t2, pll1_35MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL2_CFG
|
||||||
|
li t2, pll2_35MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, CGU_SYS
|
||||||
|
sw a0,0(t1)
|
||||||
|
li t1, RCU_RST_REQ
|
||||||
|
li t2, 0x40000008
|
||||||
|
sw t2,0(t1)
|
||||||
|
b wait_reset
|
||||||
|
nop
|
||||||
|
boot_36MHZ:
|
||||||
|
li t1, PLL0_CFG
|
||||||
|
li t2, pll0_36MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL1_CFG
|
||||||
|
li t2, pll1_36MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL2_CFG
|
||||||
|
li t2, pll2_36MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, CGU_SYS
|
||||||
|
sw a0,0(t1)
|
||||||
|
li t1, RCU_RST_REQ
|
||||||
|
li t2, 0x40000008
|
||||||
|
sw t2,0(t1)
|
||||||
|
//05252006
|
||||||
|
|
||||||
|
wait_reset:
|
||||||
|
b wait_reset
|
||||||
|
nop
|
||||||
|
freq_up2date:
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end cgu_init
|
||||||
|
|
||||||
|
#ifndef CONFIG_USE_DDR_RAM
|
||||||
|
/*
|
||||||
|
* void sdram_init(long)
|
||||||
|
*
|
||||||
|
* a0 has the clock value
|
||||||
|
*/
|
||||||
|
.globl sdram_init
|
||||||
|
.ent sdram_init
|
||||||
|
sdram_init:
|
||||||
|
|
||||||
|
/* SDRAM Initialization
|
||||||
|
*/
|
||||||
|
li t1, MC_MODUL_BASE
|
||||||
|
|
||||||
|
/* Clear Error log registers */
|
||||||
|
sw zero, MC_ERRCAUSE(t1)
|
||||||
|
sw zero, MC_ERRADDR(t1)
|
||||||
|
|
||||||
|
/* Enable SDRAM module in memory controller */
|
||||||
|
li t3, MC_SDRAM_ENABLE
|
||||||
|
lw t2, MC_CON(t1)
|
||||||
|
or t3, t2, t3
|
||||||
|
sw t3, MC_CON(t1)
|
||||||
|
|
||||||
|
li t1, MC_SDR_MODUL_BASE
|
||||||
|
|
||||||
|
/* disable the controller */
|
||||||
|
li t2, 0
|
||||||
|
sw t2, MC_CTRLENA(t1)
|
||||||
|
|
||||||
|
li t2, 0x822
|
||||||
|
sw t2, MC_IOGP(t1)
|
||||||
|
|
||||||
|
li t2, 0x2
|
||||||
|
sw t2, MC_CFGDW(t1)
|
||||||
|
|
||||||
|
/* Set CAS Latency */
|
||||||
|
li t2, 0x00000020
|
||||||
|
sw t2, MC_MRSCODE(t1)
|
||||||
|
|
||||||
|
/* Set CS0 to SDRAM parameters */
|
||||||
|
li t2, 0x000014d8
|
||||||
|
sw t2, MC_CFGPB0(t1)
|
||||||
|
|
||||||
|
/* Set SDRAM latency parameters */
|
||||||
|
li t2, 0x00036325; /* BC PC100 */
|
||||||
|
sw t2, MC_LATENCY(t1)
|
||||||
|
|
||||||
|
/* Set SDRAM refresh rate */
|
||||||
|
li t2, 0x00000C30
|
||||||
|
sw t2, MC_TREFRESH(t1)
|
||||||
|
|
||||||
|
/* Clear Power-down registers */
|
||||||
|
sw zero, MC_SELFRFSH(t1)
|
||||||
|
|
||||||
|
/* Finally enable the controller */
|
||||||
|
li t2, 1
|
||||||
|
sw t2, MC_CTRLENA(t1)
|
||||||
|
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end sdram_init
|
||||||
|
|
||||||
|
#endif /* !CONFIG_USE_DDR_RAM */
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_DDR_RAM
|
||||||
|
/*
|
||||||
|
* void ddrram_init(long)
|
||||||
|
*
|
||||||
|
* a0 has the clock value
|
||||||
|
*/
|
||||||
|
.globl ddrram_init
|
||||||
|
.ent ddrram_init
|
||||||
|
ddrram_init:
|
||||||
|
|
||||||
|
/* DDR-DRAM Initialization
|
||||||
|
*/
|
||||||
|
li t1, MC_MODUL_BASE
|
||||||
|
|
||||||
|
/* Clear Error log registers */
|
||||||
|
sw zero, MC_ERRCAUSE(t1)
|
||||||
|
sw zero, MC_ERRADDR(t1)
|
||||||
|
|
||||||
|
/* Enable DDR module in memory controller */
|
||||||
|
li t3, MC_DDRRAM_ENABLE
|
||||||
|
lw t2, MC_CON(t1)
|
||||||
|
or t3, t2, t3
|
||||||
|
sw t3, MC_CON(t1)
|
||||||
|
|
||||||
|
li t1, MC_DDR_MODUL_BASE
|
||||||
|
|
||||||
|
/* Write configuration to DDR controller registers */
|
||||||
|
li t2, MC_DC0_VALUE
|
||||||
|
sw t2, MC_DC00(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC1_VALUE
|
||||||
|
sw t2, MC_DC01(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC2_VALUE
|
||||||
|
sw t2, MC_DC02(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC3_VALUE
|
||||||
|
sw t2, MC_DC03(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC4_VALUE
|
||||||
|
sw t2, MC_DC04(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC5_VALUE
|
||||||
|
sw t2, MC_DC05(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC6_VALUE
|
||||||
|
sw t2, MC_DC06(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC7_VALUE
|
||||||
|
sw t2, MC_DC07(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC8_VALUE
|
||||||
|
sw t2, MC_DC08(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC9_VALUE
|
||||||
|
sw t2, MC_DC09(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC10_VALUE
|
||||||
|
sw t2, MC_DC10(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC11_VALUE
|
||||||
|
sw t2, MC_DC11(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC12_VALUE
|
||||||
|
sw t2, MC_DC12(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC13_VALUE
|
||||||
|
sw t2, MC_DC13(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC14_VALUE
|
||||||
|
sw t2, MC_DC14(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC15_VALUE
|
||||||
|
sw t2, MC_DC15(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC16_VALUE
|
||||||
|
sw t2, MC_DC16(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC17_VALUE
|
||||||
|
sw t2, MC_DC17(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC18_VALUE
|
||||||
|
sw t2, MC_DC18(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC19_VALUE
|
||||||
|
sw t2, MC_DC19(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC20_VALUE
|
||||||
|
sw t2, MC_DC20(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC21_VALUE
|
||||||
|
sw t2, MC_DC21(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC22_VALUE
|
||||||
|
sw t2, MC_DC22(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC23_VALUE
|
||||||
|
sw t2, MC_DC23(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC24_VALUE
|
||||||
|
sw t2, MC_DC24(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC25_VALUE
|
||||||
|
sw t2, MC_DC25(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC26_VALUE
|
||||||
|
sw t2, MC_DC26(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC27_VALUE
|
||||||
|
sw t2, MC_DC27(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC28_VALUE
|
||||||
|
sw t2, MC_DC28(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC29_VALUE
|
||||||
|
sw t2, MC_DC29(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC30_VALUE
|
||||||
|
sw t2, MC_DC30(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC31_VALUE
|
||||||
|
sw t2, MC_DC31(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC32_VALUE
|
||||||
|
sw t2, MC_DC32(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC33_VALUE
|
||||||
|
sw t2, MC_DC33(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC34_VALUE
|
||||||
|
sw t2, MC_DC34(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC35_VALUE
|
||||||
|
sw t2, MC_DC35(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC36_VALUE
|
||||||
|
sw t2, MC_DC36(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC37_VALUE
|
||||||
|
sw t2, MC_DC37(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC38_VALUE
|
||||||
|
sw t2, MC_DC38(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC39_VALUE
|
||||||
|
sw t2, MC_DC39(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC40_VALUE
|
||||||
|
sw t2, MC_DC40(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC41_VALUE
|
||||||
|
sw t2, MC_DC41(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC42_VALUE
|
||||||
|
sw t2, MC_DC42(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC43_VALUE
|
||||||
|
sw t2, MC_DC43(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC44_VALUE
|
||||||
|
sw t2, MC_DC44(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC45_VALUE
|
||||||
|
sw t2, MC_DC45(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC46_VALUE
|
||||||
|
sw t2, MC_DC46(t1)
|
||||||
|
|
||||||
|
li t2, 0x00000100
|
||||||
|
sw t2, MC_DC03(t1)
|
||||||
|
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end ddrram_init
|
||||||
|
#endif /* CONFIG_USE_DDR_RAM */
|
||||||
|
|
||||||
|
.globl lowlevel_init
|
||||||
|
.ent lowlevel_init
|
||||||
|
lowlevel_init:
|
||||||
|
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
|
||||||
|
*/
|
||||||
|
move t0, ra
|
||||||
|
/* We rely on the fact that non of the following ..._init() functions
|
||||||
|
* modify t0
|
||||||
|
*/
|
||||||
|
#if defined(DDR166)
|
||||||
|
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
|
||||||
|
li a0,0xe8
|
||||||
|
#elif defined(DDR133)
|
||||||
|
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
|
||||||
|
li a0,0xe9
|
||||||
|
#else /* defined(DDR111) */
|
||||||
|
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
|
||||||
|
li a0,0xea
|
||||||
|
#endif
|
||||||
|
bal cgu_init
|
||||||
|
nop
|
||||||
|
|
||||||
|
bal ebu_init
|
||||||
|
nop
|
||||||
|
|
||||||
|
//06063001-joelin disable the PCI CFRAME mask-start
|
||||||
|
#ifdef DISABLE_CFRAME
|
||||||
|
li t1, PCI_CR_PCI //mw bf103034 80000000
|
||||||
|
li t2, 0x80000000
|
||||||
|
sw t2,0(t1)
|
||||||
|
|
||||||
|
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||||
|
li t2, 0x103
|
||||||
|
sw t2,0(t1)
|
||||||
|
|
||||||
|
li t1, CS_CFM //mw b700006c 0
|
||||||
|
li t2, 0x00
|
||||||
|
sw t2, 0(t1)
|
||||||
|
|
||||||
|
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||||
|
li t2, 0x1000103
|
||||||
|
sw t2, 0(t1)
|
||||||
|
#endif
|
||||||
|
//06063001-joelin disable the PCI CFRAME mask-end
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_DDR_RAM
|
||||||
|
bal ddrram_init
|
||||||
|
nop
|
||||||
|
#else
|
||||||
|
bal sdram_init
|
||||||
|
nop
|
||||||
|
#endif
|
||||||
|
move ra, t0
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end lowlevel_init
|
@ -0,0 +1,74 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010 Industrie Dial Face S.p.A.
|
||||||
|
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
|
||||||
|
*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||||
|
*/
|
||||||
|
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
|
||||||
|
OUTPUT_ARCH(mips)
|
||||||
|
ENTRY(_start)
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0x00000000;
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
*(.text)
|
||||||
|
}
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.data : { *(.data) }
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
_gp = ALIGN(16) +0x7ff0;
|
||||||
|
|
||||||
|
.got : {
|
||||||
|
__got_start = .;
|
||||||
|
*(.got)
|
||||||
|
__got_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
.payload : { *(.payload) }
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
uboot_end_data = .;
|
||||||
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.sbss : { *(.sbss) }
|
||||||
|
.bss : { *(.bss) . = ALIGN(4); }
|
||||||
|
uboot_end = .;
|
||||||
|
}
|
||||||
|
|
@ -24,19 +24,34 @@
|
|||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
|
||||||
|
|
||||||
|
BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
|
||||||
|
|
||||||
#COBJS := $(BOARD).o
|
|
||||||
COBJS-y += ar9.o
|
COBJS-y += ar9.o
|
||||||
|
|
||||||
SOBJS = lowlevel_init.o pmuenable.o
|
SOBJS = lowlevel_init.o pmuenable.o
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
|
||||||
|
BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
|
||||||
|
|
||||||
|
BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
|
||||||
|
|
||||||
|
SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
|
||||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
|
||||||
|
BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
|
||||||
|
|
||||||
|
|
||||||
|
all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
|
||||||
|
|
||||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||||
|
|
||||||
|
$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
|
||||||
|
$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
# defines $(obj).depend target
|
# defines $(obj).depend target
|
||||||
|
@ -26,35 +26,15 @@
|
|||||||
#
|
#
|
||||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||||
|
|
||||||
ifdef CONFIG_LZMA_BOOTSTRAP
|
ifdef CONFIG_BOOTSTRAP
|
||||||
|
TEXT_BASE = 0x80001000
|
||||||
ifdef BUILD_BOOTSTRAP
|
CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
|
||||||
|
CONFIG_SYS_RAMBOOT = y
|
||||||
$(info BUILD_BOOTSTRAP )
|
|
||||||
#TEXT_BASE = 0xB0000000
|
|
||||||
TEXT_BASE = 0x80010000
|
|
||||||
|
|
||||||
else # BUILD_BOOTSTRAP
|
|
||||||
|
|
||||||
ifndef TEXT_BASE
|
|
||||||
$(info redefine TEXT_BASE = 0x80040000 )
|
|
||||||
TEXT_BASE = 0x80040000
|
|
||||||
endif
|
|
||||||
|
|
||||||
endif # BUILD_BOOTSTRAP
|
|
||||||
|
|
||||||
else
|
else
|
||||||
|
|
||||||
ifdef BUILD_BOOTSTRAP
|
|
||||||
$(error BUILD_BOOTSTRAP but not enabled in config)
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifndef TEXT_BASE
|
ifndef TEXT_BASE
|
||||||
## Standard: boot from ebu
|
|
||||||
$(info redefine TEXT_BASE = 0xB0000000 )
|
$(info redefine TEXT_BASE = 0xB0000000 )
|
||||||
TEXT_BASE = 0xB0000000
|
TEXT_BASE = 0xB0000000
|
||||||
## For testing: boot from RAM
|
|
||||||
# TEXT_BASE = 0x80100000
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
endif # CONFIG_LZMA_BOOTSTRAP
|
endif
|
||||||
|
@ -0,0 +1,48 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010 Industrie Dial Face S.p.A.
|
||||||
|
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
|
||||||
|
*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Vlad Lungu vlad.lungu@windriver.com
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <command.h>
|
||||||
|
#include <asm/mipsregs.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
phys_size_t bootstrap_initdram(int board_type)
|
||||||
|
{
|
||||||
|
/* Sdram is setup by assembler code */
|
||||||
|
/* If memory could be changed, we should return the true value here */
|
||||||
|
return CONFIG_SYS_MAX_RAM;
|
||||||
|
}
|
||||||
|
|
||||||
|
int bootstrap_checkboard(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int bootstrap_misc_init_r(void)
|
||||||
|
{
|
||||||
|
set_io_port_base(0);
|
||||||
|
return 0;
|
||||||
|
}
|
@ -0,0 +1,597 @@
|
|||||||
|
/*
|
||||||
|
* Memory sub-system initialization code for Danube board.
|
||||||
|
* Andre Messerschmidt
|
||||||
|
* Copyright (c) 2005 Infineon Technologies AG
|
||||||
|
*
|
||||||
|
* Based on Inca-IP code
|
||||||
|
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
/* History:
|
||||||
|
peng liu May 25, 2006, for PLL setting after reset, 05252006
|
||||||
|
*/
|
||||||
|
#include <config.h>
|
||||||
|
#include <version.h>
|
||||||
|
#include <asm/regdef.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_USE_DDR_RAM)
|
||||||
|
|
||||||
|
#if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
|
||||||
|
# include "ar9_ddr111_settings.h"
|
||||||
|
#elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M)
|
||||||
|
# include "ar9_ddr166_settings.h"
|
||||||
|
#elif defined(CONFIG_CPU_442M_RAM_147M)
|
||||||
|
# include "ar9_ddr166_settings.h"
|
||||||
|
#elif defined(CONFIG_CPU_393M_RAM_196M)
|
||||||
|
# ifdef CONFIG_ETRON_RAM
|
||||||
|
# include "etron_ddr196_settings.h"
|
||||||
|
# else
|
||||||
|
# include "ar9_ddr196_settings.h"
|
||||||
|
# endif
|
||||||
|
#elif defined(CONFIG_CPU_442M_RAM_221M)
|
||||||
|
# include "ar9_ddr221_settings.h"
|
||||||
|
#elif defined(CONFIG_CPU_500M_RAM_250M)
|
||||||
|
# include "ar9_ddr250_settings.h"
|
||||||
|
#else
|
||||||
|
# warning "missing definition for ddr_settings.h, use default!"
|
||||||
|
# include "ar9_ddr_settings.h"
|
||||||
|
#endif
|
||||||
|
#endif /* CONFIG_USE_DDR_RAM */
|
||||||
|
|
||||||
|
#define EBU_MODUL_BASE 0xBE105300
|
||||||
|
#define EBU_CLC(value) 0x0000(value)
|
||||||
|
#define EBU_CON(value) 0x0010(value)
|
||||||
|
#define EBU_ADDSEL0(value) 0x0020(value)
|
||||||
|
#define EBU_ADDSEL1(value) 0x0024(value)
|
||||||
|
#define EBU_ADDSEL2(value) 0x0028(value)
|
||||||
|
#define EBU_ADDSEL3(value) 0x002C(value)
|
||||||
|
#define EBU_BUSCON0(value) 0x0060(value)
|
||||||
|
#define EBU_BUSCON1(value) 0x0064(value)
|
||||||
|
#define EBU_BUSCON2(value) 0x0068(value)
|
||||||
|
#define EBU_BUSCON3(value) 0x006C(value)
|
||||||
|
|
||||||
|
#define MC_MODUL_BASE 0xBF800000
|
||||||
|
#define MC_ERRCAUSE(value) 0x0010(value)
|
||||||
|
#define MC_ERRADDR(value) 0x0020(value)
|
||||||
|
#define MC_CON(value) 0x0060(value)
|
||||||
|
|
||||||
|
#define MC_SRAM_ENABLE 0x00000004
|
||||||
|
#define MC_SDRAM_ENABLE 0x00000002
|
||||||
|
#define MC_DDRRAM_ENABLE 0x00000001
|
||||||
|
|
||||||
|
#define MC_SDR_MODUL_BASE 0xBF800200
|
||||||
|
#define MC_IOGP(value) 0x0000(value)
|
||||||
|
#define MC_CTRLENA(value) 0x0010(value)
|
||||||
|
#define MC_MRSCODE(value) 0x0020(value)
|
||||||
|
#define MC_CFGDW(value) 0x0030(value)
|
||||||
|
#define MC_CFGPB0(value) 0x0040(value)
|
||||||
|
#define MC_LATENCY(value) 0x0080(value)
|
||||||
|
#define MC_TREFRESH(value) 0x0090(value)
|
||||||
|
#define MC_SELFRFSH(value) 0x00A0(value)
|
||||||
|
|
||||||
|
#define MC_DDR_MODUL_BASE 0xBF801000
|
||||||
|
#define MC_DC00(value) 0x0000(value)
|
||||||
|
#define MC_DC01(value) 0x0010(value)
|
||||||
|
#define MC_DC02(value) 0x0020(value)
|
||||||
|
#define MC_DC03(value) 0x0030(value)
|
||||||
|
#define MC_DC04(value) 0x0040(value)
|
||||||
|
#define MC_DC05(value) 0x0050(value)
|
||||||
|
#define MC_DC06(value) 0x0060(value)
|
||||||
|
#define MC_DC07(value) 0x0070(value)
|
||||||
|
#define MC_DC08(value) 0x0080(value)
|
||||||
|
#define MC_DC09(value) 0x0090(value)
|
||||||
|
#define MC_DC10(value) 0x00A0(value)
|
||||||
|
#define MC_DC11(value) 0x00B0(value)
|
||||||
|
#define MC_DC12(value) 0x00C0(value)
|
||||||
|
#define MC_DC13(value) 0x00D0(value)
|
||||||
|
#define MC_DC14(value) 0x00E0(value)
|
||||||
|
#define MC_DC15(value) 0x00F0(value)
|
||||||
|
#define MC_DC16(value) 0x0100(value)
|
||||||
|
#define MC_DC17(value) 0x0110(value)
|
||||||
|
#define MC_DC18(value) 0x0120(value)
|
||||||
|
#define MC_DC19(value) 0x0130(value)
|
||||||
|
#define MC_DC20(value) 0x0140(value)
|
||||||
|
#define MC_DC21(value) 0x0150(value)
|
||||||
|
#define MC_DC22(value) 0x0160(value)
|
||||||
|
#define MC_DC23(value) 0x0170(value)
|
||||||
|
#define MC_DC24(value) 0x0180(value)
|
||||||
|
#define MC_DC25(value) 0x0190(value)
|
||||||
|
#define MC_DC26(value) 0x01A0(value)
|
||||||
|
#define MC_DC27(value) 0x01B0(value)
|
||||||
|
#define MC_DC28(value) 0x01C0(value)
|
||||||
|
#define MC_DC29(value) 0x01D0(value)
|
||||||
|
#define MC_DC30(value) 0x01E0(value)
|
||||||
|
#define MC_DC31(value) 0x01F0(value)
|
||||||
|
#define MC_DC32(value) 0x0200(value)
|
||||||
|
#define MC_DC33(value) 0x0210(value)
|
||||||
|
#define MC_DC34(value) 0x0220(value)
|
||||||
|
#define MC_DC35(value) 0x0230(value)
|
||||||
|
#define MC_DC36(value) 0x0240(value)
|
||||||
|
#define MC_DC37(value) 0x0250(value)
|
||||||
|
#define MC_DC38(value) 0x0260(value)
|
||||||
|
#define MC_DC39(value) 0x0270(value)
|
||||||
|
#define MC_DC40(value) 0x0280(value)
|
||||||
|
#define MC_DC41(value) 0x0290(value)
|
||||||
|
#define MC_DC42(value) 0x02A0(value)
|
||||||
|
#define MC_DC43(value) 0x02B0(value)
|
||||||
|
#define MC_DC44(value) 0x02C0(value)
|
||||||
|
#define MC_DC45(value) 0x02D0(value)
|
||||||
|
#define MC_DC46(value) 0x02E0(value)
|
||||||
|
|
||||||
|
#define RCU_OFFSET 0xBF203000
|
||||||
|
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
|
||||||
|
#define RCU_STS (RCU_OFFSET + 0x0014)
|
||||||
|
|
||||||
|
#define CGU_OFFSET 0xBF103000
|
||||||
|
#define PLL0_CFG (CGU_OFFSET + 0x0004)
|
||||||
|
#define PLL1_CFG (CGU_OFFSET + 0x0008)
|
||||||
|
#define PLL2_CFG (CGU_OFFSET + 0x000C)
|
||||||
|
#define CGU_SYS (CGU_OFFSET + 0x0010)
|
||||||
|
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
|
||||||
|
#define IF_CLK (CGU_OFFSET + 0x0018)
|
||||||
|
#define CGU_SMD (CGU_OFFSET + 0x0020)
|
||||||
|
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
|
||||||
|
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
|
||||||
|
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
|
||||||
|
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
|
||||||
|
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
|
||||||
|
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
|
||||||
|
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
|
||||||
|
|
||||||
|
//05252006
|
||||||
|
#define pll0_35MHz_CONFIG 0x9D861059
|
||||||
|
#define pll1_35MHz_CONFIG 0x1A260CD9
|
||||||
|
#define pll2_35MHz_CONFIG 0x8000f1e5
|
||||||
|
#define pll0_36MHz_CONFIG 0x1000125D
|
||||||
|
#define pll1_36MHz_CONFIG 0x1B1E0C99
|
||||||
|
#define pll2_36MHz_CONFIG 0x8002f2a1
|
||||||
|
//05252006
|
||||||
|
|
||||||
|
//06063001-joelin disable the PCI CFRAME mask -start
|
||||||
|
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
|
||||||
|
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
|
||||||
|
|
||||||
|
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
|
||||||
|
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
|
||||||
|
*/
|
||||||
|
#define PCI_CR_PR_OFFSET 0xBE105400
|
||||||
|
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
|
||||||
|
#define PCI_CONFIG_SPACE 0xB7000000
|
||||||
|
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
|
||||||
|
//06063001-joelin disable the PCI CFRAME mask -end
|
||||||
|
.set noreorder
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void ebu_init(void)
|
||||||
|
*/
|
||||||
|
.globl ebu_init
|
||||||
|
.ent ebu_init
|
||||||
|
ebu_init:
|
||||||
|
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
|
||||||
|
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
|
||||||
|
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
|
||||||
|
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
|
||||||
|
|
||||||
|
li t1, EBU_MODUL_BASE
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL0)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL0
|
||||||
|
sw t2, EBU_ADDSEL0(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL1)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL1
|
||||||
|
sw t2, EBU_ADDSEL1(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL2)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL2
|
||||||
|
sw t2, EBU_ADDSEL2(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_ADDSEL3)
|
||||||
|
li t2, CONFIG_EBU_ADDSEL3
|
||||||
|
sw t2, EBU_ADDSEL3(t1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_EBU_BUSCON0)
|
||||||
|
li t2, CONFIG_EBU_BUSCON0
|
||||||
|
sw t2, EBU_BUSCON0(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_BUSCON1)
|
||||||
|
li t2, CONFIG_EBU_BUSCON1
|
||||||
|
sw t2, EBU_BUSCON1(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_BUSCON2)
|
||||||
|
li t2, CONFIG_EBU_BUSCON2
|
||||||
|
sw t2, EBU_BUSCON2(t1)
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_EBU_BUSCON3)
|
||||||
|
li t2, CONFIG_EBU_BUSCON3
|
||||||
|
sw t2, EBU_BUSCON3(t1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end ebu_init
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void cgu_init(long)
|
||||||
|
*
|
||||||
|
* a0 has the clock value
|
||||||
|
*/
|
||||||
|
.globl cgu_init
|
||||||
|
.ent cgu_init
|
||||||
|
cgu_init:
|
||||||
|
li t2, CGU_SYS
|
||||||
|
lw t2,0(t2)
|
||||||
|
beq t2,a0,freq_up2date
|
||||||
|
nop
|
||||||
|
|
||||||
|
li t2, RCU_STS
|
||||||
|
lw t2, 0(t2)
|
||||||
|
and t2,0x00020000
|
||||||
|
beq t2,0x00020000,boot_36MHZ
|
||||||
|
nop
|
||||||
|
//05252006
|
||||||
|
li t1, PLL0_CFG
|
||||||
|
li t2, pll0_35MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL1_CFG
|
||||||
|
li t2, pll1_35MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL2_CFG
|
||||||
|
li t2, pll2_35MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, CGU_SYS
|
||||||
|
sw a0,0(t1)
|
||||||
|
li t1, RCU_RST_REQ
|
||||||
|
li t2, 0x40000008
|
||||||
|
sw t2,0(t1)
|
||||||
|
b wait_reset
|
||||||
|
nop
|
||||||
|
boot_36MHZ:
|
||||||
|
li t1, PLL0_CFG
|
||||||
|
li t2, pll0_36MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL1_CFG
|
||||||
|
li t2, pll1_36MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, PLL2_CFG
|
||||||
|
li t2, pll2_36MHz_CONFIG
|
||||||
|
sw t2,0(t1)
|
||||||
|
li t1, CGU_SYS
|
||||||
|
sw a0,0(t1)
|
||||||
|
li t1, RCU_RST_REQ
|
||||||
|
li t2, 0x40000008
|
||||||
|
sw t2,0(t1)
|
||||||
|
//05252006
|
||||||
|
|
||||||
|
wait_reset:
|
||||||
|
b wait_reset
|
||||||
|
nop
|
||||||
|
freq_up2date:
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end cgu_init
|
||||||
|
|
||||||
|
#ifndef CONFIG_USE_DDR_RAM
|
||||||
|
/*
|
||||||
|
* void sdram_init(long)
|
||||||
|
*
|
||||||
|
* a0 has the clock value
|
||||||
|
*/
|
||||||
|
.globl sdram_init
|
||||||
|
.ent sdram_init
|
||||||
|
sdram_init:
|
||||||
|
|
||||||
|
/* SDRAM Initialization
|
||||||
|
*/
|
||||||
|
li t1, MC_MODUL_BASE
|
||||||
|
|
||||||
|
/* Clear Error log registers */
|
||||||
|
sw zero, MC_ERRCAUSE(t1)
|
||||||
|
sw zero, MC_ERRADDR(t1)
|
||||||
|
|
||||||
|
/* Enable SDRAM module in memory controller */
|
||||||
|
li t3, MC_SDRAM_ENABLE
|
||||||
|
lw t2, MC_CON(t1)
|
||||||
|
or t3, t2, t3
|
||||||
|
sw t3, MC_CON(t1)
|
||||||
|
|
||||||
|
li t1, MC_SDR_MODUL_BASE
|
||||||
|
|
||||||
|
/* disable the controller */
|
||||||
|
li t2, 0
|
||||||
|
sw t2, MC_CTRLENA(t1)
|
||||||
|
|
||||||
|
li t2, 0x822
|
||||||
|
sw t2, MC_IOGP(t1)
|
||||||
|
|
||||||
|
li t2, 0x2
|
||||||
|
sw t2, MC_CFGDW(t1)
|
||||||
|
|
||||||
|
/* Set CAS Latency */
|
||||||
|
li t2, 0x00000020
|
||||||
|
sw t2, MC_MRSCODE(t1)
|
||||||
|
|
||||||
|
/* Set CS0 to SDRAM parameters */
|
||||||
|
li t2, 0x000014d8
|
||||||
|
sw t2, MC_CFGPB0(t1)
|
||||||
|
|
||||||
|
/* Set SDRAM latency parameters */
|
||||||
|
li t2, 0x00036325; /* BC PC100 */
|
||||||
|
sw t2, MC_LATENCY(t1)
|
||||||
|
|
||||||
|
/* Set SDRAM refresh rate */
|
||||||
|
li t2, 0x00000C30
|
||||||
|
sw t2, MC_TREFRESH(t1)
|
||||||
|
|
||||||
|
/* Clear Power-down registers */
|
||||||
|
sw zero, MC_SELFRFSH(t1)
|
||||||
|
|
||||||
|
/* Finally enable the controller */
|
||||||
|
li t2, 1
|
||||||
|
sw t2, MC_CTRLENA(t1)
|
||||||
|
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end sdram_init
|
||||||
|
|
||||||
|
#endif /* !CONFIG_USE_DDR_RAM */
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_DDR_RAM
|
||||||
|
/*
|
||||||
|
* void ddrram_init(long)
|
||||||
|
*
|
||||||
|
* a0 has the clock value
|
||||||
|
*/
|
||||||
|
.globl ddrram_init
|
||||||
|
.ent ddrram_init
|
||||||
|
ddrram_init:
|
||||||
|
|
||||||
|
/* DDR-DRAM Initialization
|
||||||
|
*/
|
||||||
|
li t1, MC_MODUL_BASE
|
||||||
|
|
||||||
|
/* Clear Error log registers */
|
||||||
|
sw zero, MC_ERRCAUSE(t1)
|
||||||
|
sw zero, MC_ERRADDR(t1)
|
||||||
|
|
||||||
|
/* Enable DDR module in memory controller */
|
||||||
|
li t3, MC_DDRRAM_ENABLE
|
||||||
|
lw t2, MC_CON(t1)
|
||||||
|
or t3, t2, t3
|
||||||
|
sw t3, MC_CON(t1)
|
||||||
|
|
||||||
|
li t1, MC_DDR_MODUL_BASE
|
||||||
|
|
||||||
|
/* Write configuration to DDR controller registers */
|
||||||
|
li t2, MC_DC0_VALUE
|
||||||
|
sw t2, MC_DC00(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC1_VALUE
|
||||||
|
sw t2, MC_DC01(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC2_VALUE
|
||||||
|
sw t2, MC_DC02(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC3_VALUE
|
||||||
|
sw t2, MC_DC03(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC4_VALUE
|
||||||
|
sw t2, MC_DC04(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC5_VALUE
|
||||||
|
sw t2, MC_DC05(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC6_VALUE
|
||||||
|
sw t2, MC_DC06(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC7_VALUE
|
||||||
|
sw t2, MC_DC07(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC8_VALUE
|
||||||
|
sw t2, MC_DC08(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC9_VALUE
|
||||||
|
sw t2, MC_DC09(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC10_VALUE
|
||||||
|
sw t2, MC_DC10(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC11_VALUE
|
||||||
|
sw t2, MC_DC11(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC12_VALUE
|
||||||
|
sw t2, MC_DC12(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC13_VALUE
|
||||||
|
sw t2, MC_DC13(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC14_VALUE
|
||||||
|
sw t2, MC_DC14(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC15_VALUE
|
||||||
|
sw t2, MC_DC15(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC16_VALUE
|
||||||
|
sw t2, MC_DC16(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC17_VALUE
|
||||||
|
sw t2, MC_DC17(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC18_VALUE
|
||||||
|
sw t2, MC_DC18(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC19_VALUE
|
||||||
|
sw t2, MC_DC19(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC20_VALUE
|
||||||
|
sw t2, MC_DC20(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC21_VALUE
|
||||||
|
sw t2, MC_DC21(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC22_VALUE
|
||||||
|
sw t2, MC_DC22(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC23_VALUE
|
||||||
|
sw t2, MC_DC23(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC24_VALUE
|
||||||
|
sw t2, MC_DC24(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC25_VALUE
|
||||||
|
sw t2, MC_DC25(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC26_VALUE
|
||||||
|
sw t2, MC_DC26(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC27_VALUE
|
||||||
|
sw t2, MC_DC27(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC28_VALUE
|
||||||
|
sw t2, MC_DC28(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC29_VALUE
|
||||||
|
sw t2, MC_DC29(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC30_VALUE
|
||||||
|
sw t2, MC_DC30(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC31_VALUE
|
||||||
|
sw t2, MC_DC31(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC32_VALUE
|
||||||
|
sw t2, MC_DC32(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC33_VALUE
|
||||||
|
sw t2, MC_DC33(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC34_VALUE
|
||||||
|
sw t2, MC_DC34(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC35_VALUE
|
||||||
|
sw t2, MC_DC35(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC36_VALUE
|
||||||
|
sw t2, MC_DC36(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC37_VALUE
|
||||||
|
sw t2, MC_DC37(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC38_VALUE
|
||||||
|
sw t2, MC_DC38(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC39_VALUE
|
||||||
|
sw t2, MC_DC39(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC40_VALUE
|
||||||
|
sw t2, MC_DC40(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC41_VALUE
|
||||||
|
sw t2, MC_DC41(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC42_VALUE
|
||||||
|
sw t2, MC_DC42(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC43_VALUE
|
||||||
|
sw t2, MC_DC43(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC44_VALUE
|
||||||
|
sw t2, MC_DC44(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC45_VALUE
|
||||||
|
sw t2, MC_DC45(t1)
|
||||||
|
|
||||||
|
li t2, MC_DC46_VALUE
|
||||||
|
sw t2, MC_DC46(t1)
|
||||||
|
|
||||||
|
li t2, 0x00000100
|
||||||
|
sw t2, MC_DC03(t1)
|
||||||
|
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end ddrram_init
|
||||||
|
#endif /* CONFIG_USE_DDR_RAM */
|
||||||
|
|
||||||
|
.globl lowlevel_init
|
||||||
|
.ent lowlevel_init
|
||||||
|
lowlevel_init:
|
||||||
|
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
|
||||||
|
*/
|
||||||
|
move t0, ra
|
||||||
|
/* We rely on the fact that non of the following ..._init() functions
|
||||||
|
* modify t0
|
||||||
|
*/
|
||||||
|
#if defined(DDR166)
|
||||||
|
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
|
||||||
|
li a0,0xe8
|
||||||
|
#elif defined(DDR133)
|
||||||
|
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
|
||||||
|
li a0,0xe9
|
||||||
|
#else /* defined(DDR111) */
|
||||||
|
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
|
||||||
|
li a0,0xea
|
||||||
|
#endif
|
||||||
|
bal cgu_init
|
||||||
|
nop
|
||||||
|
|
||||||
|
bal ebu_init
|
||||||
|
nop
|
||||||
|
|
||||||
|
//06063001-joelin disable the PCI CFRAME mask-start
|
||||||
|
#ifdef DISABLE_CFRAME
|
||||||
|
li t1, PCI_CR_PCI //mw bf103034 80000000
|
||||||
|
li t2, 0x80000000
|
||||||
|
sw t2,0(t1)
|
||||||
|
|
||||||
|
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||||
|
li t2, 0x103
|
||||||
|
sw t2,0(t1)
|
||||||
|
|
||||||
|
li t1, CS_CFM //mw b700006c 0
|
||||||
|
li t2, 0x00
|
||||||
|
sw t2, 0(t1)
|
||||||
|
|
||||||
|
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||||
|
li t2, 0x1000103
|
||||||
|
sw t2, 0(t1)
|
||||||
|
#endif
|
||||||
|
//06063001-joelin disable the PCI CFRAME mask-end
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_DDR_RAM
|
||||||
|
bal ddrram_init
|
||||||
|
nop
|
||||||
|
#else
|
||||||
|
bal sdram_init
|
||||||
|
nop
|
||||||
|
#endif
|
||||||
|
move ra, t0
|
||||||
|
j ra
|
||||||
|
nop
|
||||||
|
|
||||||
|
.end lowlevel_init
|
@ -0,0 +1,74 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010 Industrie Dial Face S.p.A.
|
||||||
|
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
|
||||||
|
*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||||
|
*/
|
||||||
|
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
|
||||||
|
OUTPUT_ARCH(mips)
|
||||||
|
ENTRY(_start)
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0x00000000;
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
*(.text)
|
||||||
|
}
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.data : { *(.data) }
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
_gp = ALIGN(16) +0x7ff0;
|
||||||
|
|
||||||
|
.got : {
|
||||||
|
__got_start = .;
|
||||||
|
*(.got)
|
||||||
|
__got_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
.payload : { *(.payload) }
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
uboot_end_data = .;
|
||||||
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
.sbss : { *(.sbss) }
|
||||||
|
.bss : { *(.bss) . = ALIGN(4); }
|
||||||
|
uboot_end = .;
|
||||||
|
}
|
||||||
|
|
@ -181,4 +181,12 @@
|
|||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_BOOTSTRAP
|
||||||
|
#define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE
|
||||||
|
#define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE
|
||||||
|
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
#define CONFIG_BOOTSTRAP_LZMA
|
||||||
|
#define CONFIG_BOOTSTRAP_SERIAL
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* __IFX_COMMON_H */
|
#endif /* __IFX_COMMON_H */
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
--- a/MAKEALL
|
--- a/MAKEALL
|
||||||
+++ b/MAKEALL
|
+++ b/MAKEALL
|
||||||
@@ -730,6 +730,12 @@ LIST_arm=" \
|
@@ -730,6 +730,12 @@
|
||||||
## MIPS Systems (default = big endian)
|
## MIPS Systems (default = big endian)
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
@ -13,7 +13,7 @@
|
|||||||
LIST_mips4kc=" \
|
LIST_mips4kc=" \
|
||||||
incaip \
|
incaip \
|
||||||
qemu_mips \
|
qemu_mips \
|
||||||
@@ -761,6 +767,7 @@ LIST_au1xx0=" \
|
@@ -761,6 +767,7 @@
|
||||||
"
|
"
|
||||||
|
|
||||||
LIST_mips=" \
|
LIST_mips=" \
|
||||||
@ -23,7 +23,7 @@
|
|||||||
${LIST_au1xx0} \
|
${LIST_au1xx0} \
|
||||||
--- a/Makefile
|
--- a/Makefile
|
||||||
+++ b/Makefile
|
+++ b/Makefile
|
||||||
@@ -447,7 +447,7 @@ $(obj)include/autoconf.mk: $(obj)include
|
@@ -447,7 +447,7 @@
|
||||||
set -e ; \
|
set -e ; \
|
||||||
: Extract the config macros ; \
|
: Extract the config macros ; \
|
||||||
$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
|
$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
|
||||||
@ -32,7 +32,7 @@
|
|||||||
mv $@.tmp $@
|
mv $@.tmp $@
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
@@ -3370,7 +3370,7 @@ incaip_config: unconfig
|
@@ -3370,7 +3370,7 @@
|
||||||
{ echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h ; \
|
{ echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h ; \
|
||||||
$(XECHO) "... with 150MHz system clock" ; \
|
$(XECHO) "... with 150MHz system clock" ; \
|
||||||
}
|
}
|
||||||
@ -41,7 +41,7 @@
|
|||||||
|
|
||||||
tb0229_config: unconfig
|
tb0229_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) mips mips tb0229
|
@$(MKCONFIG) $(@:_config=) mips mips tb0229
|
||||||
@@ -3411,6 +3411,50 @@ vct_platinumavc_onenand_small_config: un
|
@@ -3411,6 +3411,53 @@
|
||||||
@$(MKCONFIG) -a vct mips mips vct micronas
|
@$(MKCONFIG) -a vct mips mips vct micronas
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
@ -56,8 +56,9 @@
|
|||||||
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
||||||
+ $(XECHO) "... with ramboot configuration" ; \
|
+ $(XECHO) "... with ramboot configuration" ; \
|
||||||
+ }
|
+ }
|
||||||
+ @if [ "$(findstring _DDR,$@)" ] ; then \
|
+ @if [ "$(findstring _DDR,$@)" -a -z "$(findstring ramboot,$@)" ] ; then \
|
||||||
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
|
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
|
||||||
|
+ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \
|
||||||
+ DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \
|
+ DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \
|
||||||
+ case "$${DDR}" in \
|
+ case "$${DDR}" in \
|
||||||
+ 111M|166M|e111M|e166M|promos400|samsung166|psc166) \
|
+ 111M|166M|e111M|e166M|promos400|samsung166|psc166) \
|
||||||
@ -73,11 +74,13 @@
|
|||||||
+ @mkdir -p $(obj)board/infineon/easy50812
|
+ @mkdir -p $(obj)board/infineon/easy50812
|
||||||
+ @[ -z "$(findstring ramboot,$@)" ] || \
|
+ @[ -z "$(findstring ramboot,$@)" ] || \
|
||||||
+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/infineon/easy50812/config.tmp ; \
|
+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/infineon/easy50812/config.tmp ; \
|
||||||
|
+ echo "CONFIG_BOOTSTRAP = 0" >>$(obj)board/infineon/easy50812/config.tmp ; \
|
||||||
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
||||||
+ $(XECHO) "... with ramboot configuration" ; \
|
+ $(XECHO) "... with ramboot configuration" ; \
|
||||||
+ }
|
+ }
|
||||||
+ @if [ "$(findstring _DDR,$@)" ] ; then \
|
+ @if [ "$(findstring _DDR,$@)" -a -z "$(findstring ramboot,$@)" ] ; then \
|
||||||
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
|
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
|
||||||
|
+ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \
|
||||||
+ DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \
|
+ DDR=$(subst DDR,,$(filter DDR%,$(subst _, ,$@))); \
|
||||||
+ case "$${DDR}" in \
|
+ case "$${DDR}" in \
|
||||||
+ 111M|166M|e111M|e166M|promos400|samsung166|psc166) \
|
+ 111M|166M|e111M|e166M|promos400|samsung166|psc166) \
|
||||||
@ -94,7 +97,7 @@
|
|||||||
|
|
||||||
--- a/drivers/net/Makefile
|
--- a/drivers/net/Makefile
|
||||||
+++ b/drivers/net/Makefile
|
+++ b/drivers/net/Makefile
|
||||||
@@ -43,6 +43,7 @@ COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
|
@@ -43,6 +43,7 @@
|
||||||
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
|
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
|
||||||
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
|
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
|
||||||
COBJS-$(CONFIG_GRETH) += greth.o
|
COBJS-$(CONFIG_GRETH) += greth.o
|
||||||
@ -104,7 +107,7 @@
|
|||||||
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
|
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
|
||||||
--- a/drivers/serial/Makefile
|
--- a/drivers/serial/Makefile
|
||||||
+++ b/drivers/serial/Makefile
|
+++ b/drivers/serial/Makefile
|
||||||
@@ -28,6 +28,7 @@ LIB := $(obj)libserial.a
|
@@ -28,6 +28,7 @@
|
||||||
COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
|
COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
|
||||||
COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o
|
COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o
|
||||||
COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
|
COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
|
||||||
@ -114,7 +117,7 @@
|
|||||||
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
|
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
|
||||||
--- a/include/netdev.h
|
--- a/include/netdev.h
|
||||||
+++ b/include/netdev.h
|
+++ b/include/netdev.h
|
||||||
@@ -57,6 +57,7 @@ int fecmxc_initialize (bd_t *bis);
|
@@ -57,6 +57,7 @@
|
||||||
int ftmac100_initialize(bd_t *bits);
|
int ftmac100_initialize(bd_t *bits);
|
||||||
int greth_initialize(bd_t *bis);
|
int greth_initialize(bd_t *bis);
|
||||||
void gt6426x_eth_initialize(bd_t *bis);
|
void gt6426x_eth_initialize(bd_t *bis);
|
||||||
@ -122,7 +125,7 @@
|
|||||||
int inca_switch_initialize(bd_t *bis);
|
int inca_switch_initialize(bd_t *bis);
|
||||||
int kirkwood_egiga_initialize(bd_t *bis);
|
int kirkwood_egiga_initialize(bd_t *bis);
|
||||||
int lan91c96_initialize(u8 dev_num, int base_addr);
|
int lan91c96_initialize(u8 dev_num, int base_addr);
|
||||||
@@ -85,6 +86,7 @@ int uec_standard_init(bd_t *bis);
|
@@ -85,6 +86,7 @@
|
||||||
int uli526x_initialize(bd_t *bis);
|
int uli526x_initialize(bd_t *bis);
|
||||||
int sh_eth_initialize(bd_t *bis);
|
int sh_eth_initialize(bd_t *bis);
|
||||||
int dm9000_initialize(bd_t *bis);
|
int dm9000_initialize(bd_t *bis);
|
||||||
|
@ -5647,13 +5647,11 @@
|
|||||||
|
|
||||||
--- a/common/main.c
|
--- a/common/main.c
|
||||||
+++ b/common/main.c
|
+++ b/common/main.c
|
||||||
@@ -273,6 +273,10 @@ static __inline__ int abortboot(int boot
|
@@ -273,6 +273,8 @@ static __inline__ int abortboot(int boot
|
||||||
|
|
||||||
void main_loop (void)
|
void main_loop (void)
|
||||||
{
|
{
|
||||||
+#ifdef CONFIG_CMD_HTTPD
|
|
||||||
+ int ret;
|
+ int ret;
|
||||||
+#endif
|
|
||||||
+
|
+
|
||||||
#ifndef CONFIG_SYS_HUSH_PARSER
|
#ifndef CONFIG_SYS_HUSH_PARSER
|
||||||
static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
|
static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
|
||||||
|
Loading…
Reference in New Issue
Block a user