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Code

run indent on ar2313 driver

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6366 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd 2007-02-25 20:06:27 +00:00
parent 5f23843ea6
commit f0ba23e399
3 changed files with 673 additions and 639 deletions
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1028
target/linux/atheros-2.6/files/drivers/net/ar2313/ar2313.c
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File diff suppressed because it is too large Load Diff

138
target/linux/atheros-2.6/files/drivers/net/ar2313/ar2313.h
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@ -8,7 +8,7 @@
/* /*
* probe link timer - 5 secs * probe link timer - 5 secs
*/ */
#define LINK_TIMER (5*HZ) #define LINK_TIMER (5*HZ)
#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) #define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) #define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
@ -22,13 +22,13 @@
#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) #define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) #define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
static inline int tx_space (u32 csm, u32 prd) static inline int tx_space(u32 csm, u32 prd)
{ {
return (csm - prd - 1) & (AR2313_DESCR_ENTRIES - 1); return (csm - prd - 1) & (AR2313_DESCR_ENTRIES - 1);
} }
#if MAX_SKB_FRAGS #if MAX_SKB_FRAGS
#define TX_RESERVED (MAX_SKB_FRAGS+1) /* +1 for message header */ #define TX_RESERVED (MAX_SKB_FRAGS+1) /* +1 for message header */
#define tx_ring_full(csm, prd) (tx_space(csm, prd) <= TX_RESERVED) #define tx_ring_full(csm, prd) (tx_space(csm, prd) <= TX_RESERVED)
#else #else
#define tx_ring_full 0 #define tx_ring_full 0
@ -51,16 +51,16 @@ static inline int tx_space (u32 csm, u32 prd)
// New Combo structure for Both Eth0 AND eth1 // New Combo structure for Both Eth0 AND eth1
// //
typedef struct { typedef struct {
volatile unsigned int mac_control; /* 0x00 */ volatile unsigned int mac_control; /* 0x00 */
volatile unsigned int mac_addr[2]; /* 0x04 - 0x08*/ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
volatile unsigned int mii_addr; /* 0x14 */ volatile unsigned int mii_addr; /* 0x14 */
volatile unsigned int mii_data; /* 0x18 */ volatile unsigned int mii_data; /* 0x18 */
volatile unsigned int flow_control; /* 0x1c */ volatile unsigned int flow_control; /* 0x1c */
volatile unsigned int vlan_tag; /* 0x20 */ volatile unsigned int vlan_tag; /* 0x20 */
volatile unsigned int pad[7]; /* 0x24 - 0x3c */ volatile unsigned int pad[7]; /* 0x24 - 0x3c */
volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
} ETHERNET_STRUCT; } ETHERNET_STRUCT;
/******************************************************************** /********************************************************************
@ -68,31 +68,31 @@ typedef struct {
********************************************************************/ ********************************************************************/
typedef struct { typedef struct {
volatile unsigned int wdog_control; /* 0x08 */ volatile unsigned int wdog_control; /* 0x08 */
volatile unsigned int wdog_timer; /* 0x0c */ volatile unsigned int wdog_timer; /* 0x0c */
volatile unsigned int misc_status; /* 0x10 */ volatile unsigned int misc_status; /* 0x10 */
volatile unsigned int misc_mask; /* 0x14 */ volatile unsigned int misc_mask; /* 0x14 */
volatile unsigned int global_status; /* 0x18 */ volatile unsigned int global_status; /* 0x18 */
volatile unsigned int reserved; /* 0x1c */ volatile unsigned int reserved; /* 0x1c */
volatile unsigned int reset_control; /* 0x20 */ volatile unsigned int reset_control; /* 0x20 */
} INTERRUPT; } INTERRUPT;
/******************************************************************** /********************************************************************
* DMA controller * DMA controller
********************************************************************/ ********************************************************************/
typedef struct { typedef struct {
volatile unsigned int bus_mode; /* 0x00 (CSR0) */ volatile unsigned int bus_mode; /* 0x00 (CSR0) */
volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
volatile unsigned int rcv_base; /* 0x0c (CSR3) */ volatile unsigned int rcv_base; /* 0x0c (CSR3) */
volatile unsigned int xmt_base; /* 0x10 (CSR4) */ volatile unsigned int xmt_base; /* 0x10 (CSR4) */
volatile unsigned int status; /* 0x14 (CSR5) */ volatile unsigned int status; /* 0x14 (CSR5) */
volatile unsigned int control; /* 0x18 (CSR6) */ volatile unsigned int control; /* 0x18 (CSR6) */
volatile unsigned int intr_ena; /* 0x1c (CSR7) */ volatile unsigned int intr_ena; /* 0x1c (CSR7) */
volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
} DMA; } DMA;
/* /*
@ -105,59 +105,58 @@ typedef struct {
* Frequently accessed variables are put at the beginning of the * Frequently accessed variables are put at the beginning of the
* struct to help the compiler generate better/shorter code. * struct to help the compiler generate better/shorter code.
*/ */
struct ar2313_private struct ar2313_private {
{
struct net_device *dev; struct net_device *dev;
int version; int version;
u32 mb[2]; u32 mb[2];
volatile ETHERNET_STRUCT *phy_regs; volatile ETHERNET_STRUCT *phy_regs;
volatile ETHERNET_STRUCT *eth_regs; volatile ETHERNET_STRUCT *eth_regs;
volatile DMA *dma_regs; volatile DMA *dma_regs;
volatile u32 *int_regs; volatile u32 *int_regs;
struct ar531x_eth *cfg; struct ar531x_eth *cfg;
spinlock_t lock; /* Serialise access to device */ spinlock_t lock; /* Serialise access to device */
/* /*
* RX and TX descriptors, must be adjacent * RX and TX descriptors, must be adjacent
*/ */
ar2313_descr_t *rx_ring; ar2313_descr_t *rx_ring;
ar2313_descr_t *tx_ring; ar2313_descr_t *tx_ring;
struct sk_buff **rx_skb; struct sk_buff **rx_skb;
struct sk_buff **tx_skb; struct sk_buff **tx_skb;
/* /*
* RX elements * RX elements
*/ */
u32 rx_skbprd; u32 rx_skbprd;
u32 cur_rx; u32 cur_rx;
/* /*
* TX elements * TX elements
*/ */
u32 tx_prd; u32 tx_prd;
u32 tx_csm; u32 tx_csm;
/* /*
* Misc elements * Misc elements
*/ */
int board_idx; int board_idx;
char name[48]; char name[48];
struct net_device_stats stats; struct net_device_stats stats;
struct { struct {
u32 address; u32 address;
u32 length; u32 length;
char *mapping; char *mapping;
} desc; } desc;
struct timer_list link_timer; struct timer_list link_timer;
unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
unsigned short mac; unsigned short mac;
unsigned short link; /* 0 - link down, 1 - link up */ unsigned short link; /* 0 - link down, 1 - link up */
u16 phyData; u16 phyData;
struct tasklet_struct rx_tasklet; struct tasklet_struct rx_tasklet;
@ -168,7 +167,7 @@ struct ar2313_private
/* /*
* Prototypes * Prototypes
*/ */
static int ar2313_init(struct net_device *dev); static int ar2313_init(struct net_device *dev);
#ifdef TX_TIMEOUT #ifdef TX_TIMEOUT
static void ar2313_tx_timeout(struct net_device *dev); static void ar2313_tx_timeout(struct net_device *dev);
#endif #endif
@ -177,17 +176,18 @@ static void ar2313_multicast_list(struct net_device *dev);
#endif #endif
static int ar2313_restart(struct net_device *dev); static int ar2313_restart(struct net_device *dev);
#if DEBUG #if DEBUG
static void ar2313_dump_regs(struct net_device *dev); static void ar2313_dump_regs(struct net_device *dev);
#endif #endif
static void ar2313_load_rx_ring(struct net_device *dev, int bufs); static void ar2313_load_rx_ring(struct net_device *dev, int bufs);
static irqreturn_t ar2313_interrupt(int irq, void *dev_id); static irqreturn_t ar2313_interrupt(int irq, void *dev_id);
static int ar2313_open(struct net_device *dev); static int ar2313_open(struct net_device *dev);
static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev); static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev);
static int ar2313_close(struct net_device *dev); static int ar2313_close(struct net_device *dev);
static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr,
int cmd);
static void ar2313_init_cleanup(struct net_device *dev); static void ar2313_init_cleanup(struct net_device *dev);
static int ar2313_setup_timer(struct net_device *dev); static int ar2313_setup_timer(struct net_device *dev);
static void ar2313_link_timer_fn(unsigned long data); static void ar2313_link_timer_fn(unsigned long data);
static void ar2313_check_link(struct net_device *dev); static void ar2313_check_link(struct net_device *dev);
static struct net_device_stats *ar2313_get_stats(struct net_device *dev); static struct net_device_stats *ar2313_get_stats(struct net_device *dev);
#endif /* _AR2313_H_ */ #endif /* _AR2313_H_ */

146
target/linux/atheros-2.6/files/drivers/net/ar2313/dma.h
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@ -33,65 +33,68 @@
#define DMA_RX_EV2 AR_BIT(5) #define DMA_RX_EV2 AR_BIT(5)
#define DMA_RX_ERR_COL AR_BIT(6) #define DMA_RX_ERR_COL AR_BIT(6)
#define DMA_RX_LONG AR_BIT(7) #define DMA_RX_LONG AR_BIT(7)
#define DMA_RX_LS AR_BIT(8) /* last descriptor */ #define DMA_RX_LS AR_BIT(8) /* last descriptor */
#define DMA_RX_FS AR_BIT(9) /* first descriptor */ #define DMA_RX_FS AR_BIT(9) /* first descriptor */
#define DMA_RX_MF AR_BIT(10) /* multicast frame */ #define DMA_RX_MF AR_BIT(10) /* multicast frame */
#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */ #define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */
#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */ #define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */
#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */ #define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */
#define DMA_RX_ERROR AR_BIT(15) /* error summary */ #define DMA_RX_ERROR AR_BIT(15) /* error summary */
#define DMA_RX_LEN_MASK 0x3fff0000 #define DMA_RX_LEN_MASK 0x3fff0000
#define DMA_RX_LEN_SHIFT 16 #define DMA_RX_LEN_SHIFT 16
#define DMA_RX_FILT AR_BIT(30) #define DMA_RX_FILT AR_BIT(30)
#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */ #define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */
#define DMA_RX1_BSIZE_MASK 0x000007ff #define DMA_RX1_BSIZE_MASK 0x000007ff
#define DMA_RX1_BSIZE_SHIFT 0 #define DMA_RX1_BSIZE_SHIFT 0
#define DMA_RX1_CHAINED AR_BIT(24) #define DMA_RX1_CHAINED AR_BIT(24)
#define DMA_RX1_RER AR_BIT(25) #define DMA_RX1_RER AR_BIT(25)
#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */ #define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */
#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */ #define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */
#define DMA_TX_COL_MASK 0x78 #define DMA_TX_COL_MASK 0x78
#define DMA_TX_COL_SHIFT 3 #define DMA_TX_COL_SHIFT 3
#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */ #define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */
#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */ #define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */
#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */ #define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */
#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */ #define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */
#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */ #define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */
#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */ #define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */
#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */ #define DMA_TX_ERROR AR_BIT(15) /* frame aborted */
#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */ #define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */
#define DMA_TX1_BSIZE_MASK 0x000007ff #define DMA_TX1_BSIZE_MASK 0x000007ff
#define DMA_TX1_BSIZE_SHIFT 0 #define DMA_TX1_BSIZE_SHIFT 0
#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */ #define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */
#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */ #define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */
#define DMA_TX1_FS AR_BIT(29) /* first segment */ #define DMA_TX1_FS AR_BIT(29) /* first segment */
#define DMA_TX1_LS AR_BIT(30) /* last segment */ #define DMA_TX1_LS AR_BIT(30) /* last segment */
#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */ #define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */
#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ #define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */ #define MAC_CONTROL_RE AR_BIT(2) /* receive enable */
#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */ #define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */
#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check*/ #define MAC_CONTROL_DC AR_BIT(5) /* Deferral check */
#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */ #define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */
#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */ #define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */
#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */ #define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */
#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */ #define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */
#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */ #define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */
#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */ #define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */
#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */ #define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */
#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */ #define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */
#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */ #define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */
#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames only) */ #define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames
#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */ only) */
#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */ #define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */
#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */ #define MAC_CONTROL_F AR_BIT(20) /* full-duplex */
#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE SET) */ #define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */
#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */ #define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE
#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid frames) */ SET) */
#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */
#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid
frames) */
#define MII_ADDR_BUSY AR_BIT(0) #define MII_ADDR_BUSY AR_BIT(0)
#define MII_ADDR_WRITE AR_BIT(1) #define MII_ADDR_WRITE AR_BIT(1)
@ -101,40 +104,39 @@
#define FLOW_CONTROL_FCE AR_BIT(1) #define FLOW_CONTROL_FCE AR_BIT(1)
#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */ #define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */
#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */ #define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */
#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ #define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */ #define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */
#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */ #define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */
#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */ #define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */
#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */ #define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */
#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */ #define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */
#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */ #define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */
#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */ #define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */
#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */ #define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */
#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */ #define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */
#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */ #define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */
#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */ #define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */
#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */ #define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */
#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */ #define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */
#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */ #define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */
#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ #define DMA_STATUS_RS_SHIFT 17 /* receive process state */
#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ #define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
#define DMA_STATUS_EB_SHIFT 23 /* error bits */ #define DMA_STATUS_EB_SHIFT 23 /* error bits */
#define DMA_CONTROL_SR AR_BIT(1) /* start receive */ #define DMA_CONTROL_SR AR_BIT(1) /* start receive */
#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */ #define DMA_CONTROL_ST AR_BIT(13) /* start transmit */
#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */ #define DMA_CONTROL_SF AR_BIT(21) /* store and forward */
typedef struct { typedef struct {
volatile unsigned int status; // OWN, Device control and status. volatile unsigned int status; // OWN, Device control and status.
volatile unsigned int devcs; // pkt Control bits + Length volatile unsigned int devcs; // pkt Control bits + Length
volatile unsigned int addr; // Current Address. volatile unsigned int addr; // Current Address.
volatile unsigned int descr; // Next descriptor in chain. volatile unsigned int descr; // Next descriptor in chain.
} ar2313_descr_t; } ar2313_descr_t;
#endif // __ARUBA_DMA_H__ #endif // __ARUBA_DMA_H__