mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 01:01:52 +02:00
run indent on ar2313 driver
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6366 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
nbd
parent
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File diff suppressed because it is too large
Load Diff
@ -8,7 +8,7 @@
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/*
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* probe link timer - 5 secs
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*/
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#define LINK_TIMER (5*HZ)
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#define LINK_TIMER (5*HZ)
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#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
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#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
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@ -22,13 +22,13 @@
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#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
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#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
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static inline int tx_space (u32 csm, u32 prd)
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static inline int tx_space(u32 csm, u32 prd)
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{
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return (csm - prd - 1) & (AR2313_DESCR_ENTRIES - 1);
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}
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#if MAX_SKB_FRAGS
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#define TX_RESERVED (MAX_SKB_FRAGS+1) /* +1 for message header */
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#define TX_RESERVED (MAX_SKB_FRAGS+1) /* +1 for message header */
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#define tx_ring_full(csm, prd) (tx_space(csm, prd) <= TX_RESERVED)
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#else
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#define tx_ring_full 0
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@ -51,16 +51,16 @@ static inline int tx_space (u32 csm, u32 prd)
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// New Combo structure for Both Eth0 AND eth1
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//
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typedef struct {
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volatile unsigned int mac_control; /* 0x00 */
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volatile unsigned int mac_addr[2]; /* 0x04 - 0x08*/
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volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
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volatile unsigned int mii_addr; /* 0x14 */
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volatile unsigned int mii_data; /* 0x18 */
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volatile unsigned int flow_control; /* 0x1c */
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volatile unsigned int vlan_tag; /* 0x20 */
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volatile unsigned int pad[7]; /* 0x24 - 0x3c */
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volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
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volatile unsigned int mac_control; /* 0x00 */
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volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
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volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
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volatile unsigned int mii_addr; /* 0x14 */
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volatile unsigned int mii_data; /* 0x18 */
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volatile unsigned int flow_control; /* 0x1c */
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volatile unsigned int vlan_tag; /* 0x20 */
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volatile unsigned int pad[7]; /* 0x24 - 0x3c */
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volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
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} ETHERNET_STRUCT;
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/********************************************************************
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@ -68,31 +68,31 @@ typedef struct {
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********************************************************************/
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typedef struct {
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volatile unsigned int wdog_control; /* 0x08 */
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volatile unsigned int wdog_timer; /* 0x0c */
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volatile unsigned int misc_status; /* 0x10 */
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volatile unsigned int misc_mask; /* 0x14 */
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volatile unsigned int global_status; /* 0x18 */
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volatile unsigned int reserved; /* 0x1c */
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volatile unsigned int reset_control; /* 0x20 */
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volatile unsigned int wdog_control; /* 0x08 */
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volatile unsigned int wdog_timer; /* 0x0c */
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volatile unsigned int misc_status; /* 0x10 */
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volatile unsigned int misc_mask; /* 0x14 */
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volatile unsigned int global_status; /* 0x18 */
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volatile unsigned int reserved; /* 0x1c */
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volatile unsigned int reset_control; /* 0x20 */
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} INTERRUPT;
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/********************************************************************
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* DMA controller
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********************************************************************/
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typedef struct {
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volatile unsigned int bus_mode; /* 0x00 (CSR0) */
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volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
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volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
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volatile unsigned int rcv_base; /* 0x0c (CSR3) */
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volatile unsigned int xmt_base; /* 0x10 (CSR4) */
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volatile unsigned int status; /* 0x14 (CSR5) */
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volatile unsigned int control; /* 0x18 (CSR6) */
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volatile unsigned int intr_ena; /* 0x1c (CSR7) */
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volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
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volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
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volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
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volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
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volatile unsigned int bus_mode; /* 0x00 (CSR0) */
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volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
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volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
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volatile unsigned int rcv_base; /* 0x0c (CSR3) */
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volatile unsigned int xmt_base; /* 0x10 (CSR4) */
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volatile unsigned int status; /* 0x14 (CSR5) */
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volatile unsigned int control; /* 0x18 (CSR6) */
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volatile unsigned int intr_ena; /* 0x1c (CSR7) */
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volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
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volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
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volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
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volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
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} DMA;
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/*
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@ -105,59 +105,58 @@ typedef struct {
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* Frequently accessed variables are put at the beginning of the
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* struct to help the compiler generate better/shorter code.
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*/
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struct ar2313_private
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{
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struct ar2313_private {
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struct net_device *dev;
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int version;
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u32 mb[2];
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volatile ETHERNET_STRUCT *phy_regs;
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volatile ETHERNET_STRUCT *eth_regs;
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volatile DMA *dma_regs;
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volatile u32 *int_regs;
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int version;
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u32 mb[2];
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volatile ETHERNET_STRUCT *phy_regs;
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volatile ETHERNET_STRUCT *eth_regs;
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volatile DMA *dma_regs;
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volatile u32 *int_regs;
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struct ar531x_eth *cfg;
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spinlock_t lock; /* Serialise access to device */
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spinlock_t lock; /* Serialise access to device */
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/*
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/*
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* RX and TX descriptors, must be adjacent
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*/
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ar2313_descr_t *rx_ring;
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ar2313_descr_t *tx_ring;
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ar2313_descr_t *rx_ring;
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ar2313_descr_t *tx_ring;
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struct sk_buff **rx_skb;
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struct sk_buff **tx_skb;
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struct sk_buff **rx_skb;
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struct sk_buff **tx_skb;
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/*
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/*
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* RX elements
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*/
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u32 rx_skbprd;
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u32 cur_rx;
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u32 rx_skbprd;
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u32 cur_rx;
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/*
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/*
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* TX elements
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*/
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u32 tx_prd;
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u32 tx_csm;
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u32 tx_prd;
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u32 tx_csm;
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/*
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/*
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* Misc elements
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*/
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int board_idx;
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char name[48];
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int board_idx;
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char name[48];
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struct net_device_stats stats;
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struct {
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u32 address;
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u32 length;
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char *mapping;
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u32 address;
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u32 length;
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char *mapping;
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} desc;
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struct timer_list link_timer;
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unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
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unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
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unsigned short mac;
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unsigned short link; /* 0 - link down, 1 - link up */
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unsigned short link; /* 0 - link down, 1 - link up */
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u16 phyData;
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struct tasklet_struct rx_tasklet;
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@ -168,7 +167,7 @@ struct ar2313_private
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/*
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* Prototypes
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*/
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static int ar2313_init(struct net_device *dev);
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static int ar2313_init(struct net_device *dev);
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#ifdef TX_TIMEOUT
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static void ar2313_tx_timeout(struct net_device *dev);
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#endif
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@ -177,17 +176,18 @@ static void ar2313_multicast_list(struct net_device *dev);
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#endif
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static int ar2313_restart(struct net_device *dev);
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#if DEBUG
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static void ar2313_dump_regs(struct net_device *dev);
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static void ar2313_dump_regs(struct net_device *dev);
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#endif
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static void ar2313_load_rx_ring(struct net_device *dev, int bufs);
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static irqreturn_t ar2313_interrupt(int irq, void *dev_id);
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static int ar2313_open(struct net_device *dev);
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static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev);
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static int ar2313_close(struct net_device *dev);
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static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
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static int ar2313_open(struct net_device *dev);
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static int ar2313_start_xmit(struct sk_buff *skb, struct net_device *dev);
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static int ar2313_close(struct net_device *dev);
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static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr,
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int cmd);
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static void ar2313_init_cleanup(struct net_device *dev);
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static int ar2313_setup_timer(struct net_device *dev);
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static int ar2313_setup_timer(struct net_device *dev);
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static void ar2313_link_timer_fn(unsigned long data);
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static void ar2313_check_link(struct net_device *dev);
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static struct net_device_stats *ar2313_get_stats(struct net_device *dev);
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#endif /* _AR2313_H_ */
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#endif /* _AR2313_H_ */
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@ -33,65 +33,68 @@
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#define DMA_RX_EV2 AR_BIT(5)
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#define DMA_RX_ERR_COL AR_BIT(6)
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#define DMA_RX_LONG AR_BIT(7)
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#define DMA_RX_LS AR_BIT(8) /* last descriptor */
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#define DMA_RX_FS AR_BIT(9) /* first descriptor */
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#define DMA_RX_MF AR_BIT(10) /* multicast frame */
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#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */
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#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */
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#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */
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#define DMA_RX_ERROR AR_BIT(15) /* error summary */
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#define DMA_RX_LS AR_BIT(8) /* last descriptor */
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#define DMA_RX_FS AR_BIT(9) /* first descriptor */
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#define DMA_RX_MF AR_BIT(10) /* multicast frame */
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#define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */
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#define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */
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#define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */
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#define DMA_RX_ERROR AR_BIT(15) /* error summary */
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#define DMA_RX_LEN_MASK 0x3fff0000
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#define DMA_RX_LEN_SHIFT 16
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#define DMA_RX_FILT AR_BIT(30)
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#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */
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#define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */
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#define DMA_RX1_BSIZE_MASK 0x000007ff
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#define DMA_RX1_BSIZE_SHIFT 0
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#define DMA_RX1_CHAINED AR_BIT(24)
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#define DMA_RX1_RER AR_BIT(25)
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#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */
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#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */
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#define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */
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#define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */
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#define DMA_TX_COL_MASK 0x78
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#define DMA_TX_COL_SHIFT 3
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#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */
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#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */
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#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */
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#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */
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#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */
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#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */
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#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */
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#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */
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#define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */
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#define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */
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#define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */
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#define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */
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#define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */
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#define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */
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#define DMA_TX_ERROR AR_BIT(15) /* frame aborted */
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#define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */
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#define DMA_TX1_BSIZE_MASK 0x000007ff
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#define DMA_TX1_BSIZE_SHIFT 0
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#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */
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#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */
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#define DMA_TX1_FS AR_BIT(29) /* first segment */
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#define DMA_TX1_LS AR_BIT(30) /* last segment */
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#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */
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#define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */
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#define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */
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#define DMA_TX1_FS AR_BIT(29) /* first segment */
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#define DMA_TX1_LS AR_BIT(30) /* last segment */
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#define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */
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#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
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#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
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#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */
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#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */
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#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check*/
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#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */
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#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */
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#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */
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#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */
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#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */
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#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */
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#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */
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#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */
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#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */
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#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames only) */
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#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */
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#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */
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#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */
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#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE SET) */
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#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */
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#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid frames) */
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#define MAC_CONTROL_RE AR_BIT(2) /* receive enable */
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#define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */
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#define MAC_CONTROL_DC AR_BIT(5) /* Deferral check */
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#define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */
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#define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */
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#define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */
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#define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */
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#define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */
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#define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */
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#define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */
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#define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */
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#define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */
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#define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames
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only) */
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#define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */
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#define MAC_CONTROL_F AR_BIT(20) /* full-duplex */
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#define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */
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#define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE
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SET) */
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#define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */
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#define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid
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frames) */
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#define MII_ADDR_BUSY AR_BIT(0)
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#define MII_ADDR_WRITE AR_BIT(1)
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@ -101,40 +104,39 @@
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#define FLOW_CONTROL_FCE AR_BIT(1)
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#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */
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#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */
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#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
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#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */
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#define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */
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#define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */
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#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
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#define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */
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#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */
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#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */
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#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */
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#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */
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#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */
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#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */
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#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */
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#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */
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#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */
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#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */
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#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */
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#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */
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#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */
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#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
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#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
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#define DMA_STATUS_EB_SHIFT 23 /* error bits */
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#define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */
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#define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */
|
||||
#define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */
|
||||
#define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */
|
||||
#define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */
|
||||
#define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */
|
||||
#define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */
|
||||
#define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */
|
||||
#define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */
|
||||
#define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */
|
||||
#define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */
|
||||
#define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */
|
||||
#define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */
|
||||
#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
|
||||
#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
|
||||
#define DMA_STATUS_EB_SHIFT 23 /* error bits */
|
||||
|
||||
#define DMA_CONTROL_SR AR_BIT(1) /* start receive */
|
||||
#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */
|
||||
#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */
|
||||
#define DMA_CONTROL_SR AR_BIT(1) /* start receive */
|
||||
#define DMA_CONTROL_ST AR_BIT(13) /* start transmit */
|
||||
#define DMA_CONTROL_SF AR_BIT(21) /* store and forward */
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile unsigned int status; // OWN, Device control and status.
|
||||
volatile unsigned int devcs; // pkt Control bits + Length
|
||||
volatile unsigned int addr; // Current Address.
|
||||
volatile unsigned int descr; // Next descriptor in chain.
|
||||
volatile unsigned int status; // OWN, Device control and status.
|
||||
volatile unsigned int devcs; // pkt Control bits + Length
|
||||
volatile unsigned int addr; // Current Address.
|
||||
volatile unsigned int descr; // Next descriptor in chain.
|
||||
} ar2313_descr_t;
|
||||
|
||||
|
||||
#endif // __ARUBA_DMA_H__
|
||||
|
||||
#endif // __ARUBA_DMA_H__
|
||||
|
||||
Loading…
Reference in New Issue
Block a user