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cleaning up olpc patch 1
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10060 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic
354
target/linux/olpc/files/arch/i386/kernel/mfgpt.c
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354
target/linux/olpc/files/arch/i386/kernel/mfgpt.c
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/* Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT)
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*
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* Copyright (C) 2006, Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/* The MFPGT timers on the CS5536 provide us with suitable timers to use
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* as clock event sources - not as good as a HPET or APIC, but certainly
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* better then the PIT. This isn't a general purpose MFGPT driver, but
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* a simplified one designed specifically to act as a clock event source.
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* For full details about the MFGPT, please consult the CS5536 data sheet.
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*/
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/* We are using the 32Khz input clock - its the only one that has the
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* ranges we find desirable. The following table lists the suitable
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* divisors and the associated hz, minimum interval
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* and the maximum interval:
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Divisor Hz Min Delta (S) Max Delta (S)
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1 32000 .0005 2.048
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2 16000 .001 4.096
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4 8000 .002 8.192
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8 4000 .004 16.384
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16 2000 .008 32.768
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32 1000 .016 65.536
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64 500 .032 131.072
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128 250 .064 262.144
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256 125 .128 524.288
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/geode.h>
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#include "do_timer.h"
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#define MFGPT_MAX_TIMERS 8
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#define F_AVAIL 0x01
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static struct mfgpt_timer_t {
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int flags;
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struct module *owner;
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} mfgpt_timers[MFGPT_MAX_TIMERS];
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/* Selected from the table above */
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#define MFGPT_DIVISOR 16
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#define MFGPT_SCALE 4 /* divisor = 2^(scale) */
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#define MFGPT_HZ (32000 / MFGPT_DIVISOR)
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#define MFGPT_PERIODIC (MFGPT_HZ / HZ)
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#ifdef CONFIG_GEODE_MFGPT_TIMER
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static int __init mfgpt_timer_setup(void);
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#else
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#define mfgpt_timer_setup() (0)
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#endif
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/* Allow for disabling of MFGPTs */
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static int disable = 0;
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static int __init mfgpt_disable(char *s)
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{
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disable = 1;
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return 1;
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}
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__setup("nomfgpt", mfgpt_disable);
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/*
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* Check whether any MFGPTs are available for the kernel to use. In most
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* cases, firmware that uses AMD's VSA code will claim all timers during
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* bootup; we certainly don't want to take them if they're already in use.
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* In other cases (such as with VSAless OpenFirmware), the system firmware
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* leaves timers available for us to use.
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*/
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int __init geode_mfgpt_detect(void)
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{
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int count = 0, i;
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u16 val;
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if (disable) {
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printk(KERN_INFO "geode-mfgpt: Skipping MFGPT setup\n");
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return 0;
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}
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for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
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val = geode_mfgpt_read(i, MFGPT_REG_SETUP);
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if (!(val & MFGPT_SETUP_SETUP)) {
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mfgpt_timers[i].flags = F_AVAIL;
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count++;
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}
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}
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/* set up clock event device, if desired */
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i = mfgpt_timer_setup();
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return count;
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}
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int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable)
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{
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u32 msr, mask, value, dummy;
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int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
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if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
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return -EIO;
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/*
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* The register maps for these are described in sections 6.17.1.x of
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* the AMD Geode CS5536 Companion Device Data Book.
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*/
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switch(event) {
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case MFGPT_EVENT_RESET:
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/* XXX: According to the docs, we cannot reset timers above
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* 6; that is, resets for 7 and 8 will be ignored. Is this
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* a problem? */
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msr = MFGPT_NR_MSR;
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mask = 1 << (timer + 24);
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break;
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case MFGPT_EVENT_NMI:
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msr = MFGPT_NR_MSR;
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mask = 1 << (timer + shift);
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break;
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case MFGPT_EVENT_IRQ:
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msr = MFGPT_IRQ_MSR;
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mask = 1 << (timer + shift);
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break;
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default:
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return -EIO;
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}
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rdmsr(msr, value, dummy);
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if (enable)
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value |= mask;
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else
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value &= ~mask;
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wrmsr(msr, value, dummy);
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return 0;
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}
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EXPORT_SYMBOL(geode_mfgpt_toggle_event);
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int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable)
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{
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u32 val, dummy;
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int offset;
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if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
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return -EIO;
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if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
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return -EIO;
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rdmsr(0x51400022, val, dummy);
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offset = (timer % 4) * 4;
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val &= ~((0xF << offset) | (0xF << (offset + 16)));
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if (enable) {
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val |= (irq & 0x0F) << (offset);
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val |= (irq & 0x0F) << (offset + 16);
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}
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wrmsr(0x51400022, val, dummy);
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return 0;
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}
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EXPORT_SYMBOL(geode_mfgpt_set_irq);
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static int mfgpt_get(int timer, struct module *owner)
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{
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mfgpt_timers[timer].flags &= ~F_AVAIL;
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mfgpt_timers[timer].owner = owner;
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printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer);
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return timer;
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}
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int geode_mfgpt_alloc_timer(int timer, int domain, struct module *owner)
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{
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int i;
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if (!geode_get_dev_base(GEODE_DEV_MFGPT))
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return -ENODEV;
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if (timer >= MFGPT_MAX_TIMERS)
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return -EIO;
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if (timer < 0) {
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/* Try to find an available timer */
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for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
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if (mfgpt_timers[i].flags & F_AVAIL)
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return mfgpt_get(i, owner);
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if (i == 5 && domain == MFGPT_DOMAIN_WORKING)
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break;
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}
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}
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else {
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/* If they requested a specific timer, try to honor that */
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if (mfgpt_timers[timer].flags & F_AVAIL)
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return mfgpt_get(timer, owner);
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}
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/* No timers available - too bad */
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return -1;
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}
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EXPORT_SYMBOL(geode_mfgpt_alloc_timer);
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#ifdef CONFIG_GEODE_MFGPT_TIMER
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static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
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static u16 mfgpt_event_clock;
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static int irq = 7;
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static int __init mfgpt_setup(char *str)
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{
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get_option(&str, &irq);
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return 1;
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}
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__setup("mfgpt_irq=", mfgpt_setup);
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static inline void mfgpt_disable_timer(u16 clock)
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{
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u16 val = geode_mfgpt_read(clock, MFGPT_REG_SETUP);
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geode_mfgpt_write(clock, MFGPT_REG_SETUP, val & ~MFGPT_SETUP_CNTEN);
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}
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static int mfgpt_next_event(unsigned long, struct clock_event_device *);
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static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *);
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static struct clock_event_device mfgpt_clockevent = {
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.name = "mfgpt-timer",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = mfgpt_set_mode,
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.set_next_event = mfgpt_next_event,
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.rating = 250,
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.cpumask = CPU_MASK_ALL,
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.shift = 32
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};
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static inline void mfgpt_start_timer(u16 clock, u16 delta)
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{
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geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta);
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geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
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geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
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MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
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}
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static void mfgpt_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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mfgpt_disable_timer(mfgpt_event_clock);
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if (mode == CLOCK_EVT_MODE_PERIODIC)
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mfgpt_start_timer(mfgpt_event_clock, MFGPT_PERIODIC);
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mfgpt_tick_mode = mode;
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}
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static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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mfgpt_start_timer(mfgpt_event_clock, delta);
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return 0;
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}
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/* Assume (foolishly?), that this interrupt was due to our tick */
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static irqreturn_t mfgpt_tick(int irq, void *dev_id)
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{
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if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
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return IRQ_HANDLED;
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/* Turn off the clock */
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mfgpt_disable_timer(mfgpt_event_clock);
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/* Clear the counter */
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geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
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/* Restart the clock in periodic mode */
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if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) {
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geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
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MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
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}
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mfgpt_clockevent.event_handler(&mfgpt_clockevent);
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return IRQ_HANDLED;
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}
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static struct irqaction mfgptirq = {
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.handler = mfgpt_tick,
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.flags = IRQF_DISABLED | IRQF_NOBALANCING,
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.mask = CPU_MASK_NONE,
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.name = "mfgpt-timer"
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};
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static int __init mfgpt_timer_setup(void)
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{
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int timer, ret;
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u16 val;
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timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING, THIS_MODULE);
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if (timer < 0) {
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printk(KERN_ERR "mfgpt-timer: Could not allocate a MFPGT timer\n");
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return -ENODEV;
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}
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mfgpt_event_clock = timer;
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/* Set the clock scale and enable the event mode for CMP2 */
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val = MFGPT_SCALE | (3 << 8);
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geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val);
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/* Set up the IRQ on the MFGPT side */
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if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, irq)) {
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printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq);
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return -EIO;
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}
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/* And register it with the kernel */
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ret = setup_irq(irq, &mfgptirq);
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if (ret) {
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printk(KERN_ERR "mfgpt-timer: Unable to set up the interrupt.\n");
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goto err;
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}
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/* Set up the clock event */
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mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC, 32);
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mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &mfgpt_clockevent);
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mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE, &mfgpt_clockevent);
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printk("mfgpt-timer: registering the MFGT timer as a clock event.\n");
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clockevents_register_device(&mfgpt_clockevent);
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return 0;
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err:
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geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, irq);
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printk(KERN_ERR "mfgpt-timer: Unable to set up the MFGPT clock source\n");
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return -EIO;
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}
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#endif
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