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[ltq-dsl] fix for 3.2.9
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31065 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -40,6 +40,7 @@
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#include <linux/proc_fs.h>
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#include <linux/proc_fs.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/ioctl.h>
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#include <linux/ioctl.h>
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#include <linux/clk.h>
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#include <asm/delay.h>
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#include <asm/delay.h>
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/*
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/*
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@ -107,23 +108,27 @@ static inline void init_pmu(void)
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{
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{
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//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
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//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
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//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
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//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
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/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
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//PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
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//PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
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struct clk *clk = clk_get_sys("ltq_dsl", NULL);
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clk_enable(clk);
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}
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}
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static inline void uninit_pmu(void)
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static inline void uninit_pmu(void)
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{
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{
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PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
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/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
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//PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
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//PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
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//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
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//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/
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struct clk *clk = clk_get_sys("ltq_dsl", NULL);
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clk_disable(clk);
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}
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}
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static inline void reset_ppe(void)
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static inline void reset_ppe(void)
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@ -40,6 +40,7 @@
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#include <linux/proc_fs.h>
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#include <linux/proc_fs.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/ioctl.h>
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#include <linux/ioctl.h>
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#include <linux/clk.h>
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#include <asm/delay.h>
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#include <asm/delay.h>
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/*
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/*
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@ -114,23 +115,27 @@ static inline void init_pmu(void)
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{
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{
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//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
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//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
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//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
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//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
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/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
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struct clk *clk = clk_get_sys("ltq_dsl", NULL);
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clk_enable(clk);
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}
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}
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static inline void uninit_pmu(void)
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static inline void uninit_pmu(void)
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{
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{
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PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
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/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);*/
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//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
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//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
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struct clk *clk = clk_get_sys("ltq_dsl", NULL);
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clk_disable(clk);
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}
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}
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static inline void reset_ppe(void)
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static inline void reset_ppe(void)
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@ -40,6 +40,7 @@
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#include <linux/proc_fs.h>
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#include <linux/proc_fs.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/ioctl.h>
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#include <linux/ioctl.h>
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#include <linux/clk.h>
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#include <asm/delay.h>
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#include <asm/delay.h>
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/*
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/*
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@ -109,23 +110,27 @@ static inline void init_pmu(void)
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{
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{
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//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
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//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
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//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
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//PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
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/* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
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struct clk *clk = clk_get_sys("ltq_dsl", NULL);
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clk_enable(clk);
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}
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}
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static inline void uninit_pmu(void)
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static inline void uninit_pmu(void)
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{
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{
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PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
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/* PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
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PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
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DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);*/
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//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
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//PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
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struct clk *clk = clk_get_sys("ltq_dsl", NULL);
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clk_disable(clk);
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}
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}
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static inline void reset_ppe(void)
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static inline void reset_ppe(void)
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@ -34,6 +34,9 @@
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#define IFX_PMU_MODULE_PPE_EMA (1 << 22)
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#define IFX_PMU_MODULE_PPE_EMA (1 << 22)
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#define IFX_PMU_MODULE_PPE_TOP (1 << 29)
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#define IFX_PMU_MODULE_PPE_TOP (1 << 29)
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extern void ltq_pmu_enable(unsigned int module);
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extern void ltq_pmu_disable(unsigned int module);
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#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) ltq_pmu_enable(b); else ltq_pmu_disable(b);}
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#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) ltq_pmu_enable(b); else ltq_pmu_disable(b);}
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#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
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#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
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