mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 17:54:38 +03:00
[adm5120] define more SWITCH/MPMC constants
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8704 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
parent
5798228110
commit
f9d0242a80
@ -26,6 +26,11 @@
|
||||
#ifndef _ADM5120_MPMC_H_
|
||||
#define _ADM5120_MPMC_H_
|
||||
|
||||
#define MPMC_READ_REG(r) __raw_readl( \
|
||||
(void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
|
||||
#define MPMC_WRITE_REG(r, v) __raw_writel((v), \
|
||||
(void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
|
||||
|
||||
#define MPMC_REG_CTRL 0x0000
|
||||
#define MPMC_REG_STATUS 0x0004
|
||||
#define MPMC_REG_CONF 0x0008
|
||||
@ -46,7 +51,9 @@
|
||||
#define MPMC_REG_SC2 0x0240
|
||||
#define MPMC_REG_SC3 0x0260
|
||||
|
||||
/* Control register bits */
|
||||
#define MPMC_CTRL_AM ( 1 << 1 )
|
||||
#define MPMC_CTRL_DWB ( 1 << 3 )
|
||||
|
||||
/* Dynamic Control register bits */
|
||||
#define MPMC_DC_CE ( 1 << 0 )
|
||||
|
@ -1,4 +1,6 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* ADM5120 ethernet switch definitions
|
||||
*
|
||||
* This header file defines the hardware registers of the ADM5120 SoC
|
||||
@ -23,45 +25,63 @@
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef _ADM5120_SWITCH_H
|
||||
#define _ADM5120_SWITCH_H
|
||||
#ifndef _ADM5120_SWITCH_H_
|
||||
#define _ADM5120_SWITCH_H_
|
||||
|
||||
#define BIT(at) (1 << (at))
|
||||
#define BITMASK(len) ((1 << (len))-1)
|
||||
#define ONEBIT(at) (1 << (at))
|
||||
|
||||
#define SW_READ_REG(r) __raw_readl( \
|
||||
(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
|
||||
#define SW_WRITE_REG(r, v) __raw_writel((v), \
|
||||
(void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
|
||||
|
||||
/* Switch register offsets */
|
||||
#define SWITCH_REG_CODE 0x0000
|
||||
#define SWITCH_REG_SOFT_RESET 0x0004
|
||||
#define SWITCH_REG_MEMCTRL 0x001C
|
||||
#define SWITCH_REG_CPUP_CONF 0x0024
|
||||
#define SWITCH_REG_PORT_CONF0 0x0028
|
||||
#define SWITCH_REG_PORT_CONF1 0x002C
|
||||
#define SWITCH_REG_PORT_CONF2 0x0030
|
||||
#define SWITCH_REG_VLAN_G1 0x0040
|
||||
#define SWITCH_REG_VLAN_G2 0x0044
|
||||
#define SWITCH_REG_SEND_TRIG 0x0048
|
||||
#define SWITCH_REG_MAC_WT0 0x0058
|
||||
#define SWITCH_REG_MAC_WT1 0x005C
|
||||
#define SWITCH_REG_PHY_CNTL0 0x0068
|
||||
#define SWITCH_REG_PHY_CNTL1 0x006C
|
||||
#define SWITCH_REG_PHY_CNTL2 0x007C
|
||||
#define SWITCH_REG_PHY_CNTL3 0x0080
|
||||
#define SWITCH_REG_PRI_CNTL 0x0084
|
||||
#define SWITCH_REG_INT_STATUS 0x00B0
|
||||
#define SWITCH_REG_INT_MASK 0x00B4
|
||||
#define SWITCH_REG_GPIO_CONF0 0x00B8
|
||||
#define SWITCH_REG_GPIO_CONF2 0x00BC
|
||||
#define SWITCH_REG_WDOG0 0x00C0
|
||||
#define SWITCH_REG_WDOG1 0x00C4
|
||||
#define SWITCH_REG_PHY_CNTL4 0x00A0
|
||||
#define SWITCH_REG_SOFT_RESET 0x0004 /* Soft Reset */
|
||||
#define SWITCH_REG_BOOT_DONE 0x0008 /* Boot Done */
|
||||
#define SWITCH_REG_SW_RESET 0x000C /* Switch Reset */
|
||||
#define SWITCH_REG_PHY_STATUS 0x0014 /* PHY Status */
|
||||
#define SWITCH_REG_MEMCTRL 0x001C /* Memory Control */
|
||||
#define SWITCH_REG_CPUP_CONF 0x0024 /* CPU Port Configuration */
|
||||
#define SWITCH_REG_PORT_CONF0 0x0028 /* Port Configuration 0 */
|
||||
#define SWITCH_REG_PORT_CONF1 0x002C /* Port Configuration 1 */
|
||||
#define SWITCH_REG_PORT_CONF2 0x0030 /* Port Configuration 2 */
|
||||
#define SWITCH_REG_VLAN_G1 0x0040 /* VLAN group 1 */
|
||||
#define SWITCH_REG_VLAN_G2 0x0044 /* VLAN group 2 */
|
||||
#define SWITCH_REG_SEND_TRIG 0x0048 /* Send Trigger */
|
||||
#define SWITCH_REG_MAC_WT0 0x0058 /* MAC Write Address 0 */
|
||||
#define SWITCH_REG_MAC_WT1 0x005C /* MAC Write Address 1 */
|
||||
#define SWITCH_REG_BW_CNTL0 0x0060 /* Bandwidth Control 0 */
|
||||
#define SWITCH_REG_BW_CNTL1 0x0064 /* Bandwidth Control 1 */
|
||||
#define SWITCH_REG_PHY_CNTL0 0x0068 /* PHY Control 0 */
|
||||
#define SWITCH_REG_PHY_CNTL1 0x006C /* PHY Control 1 */
|
||||
#define SWITCH_REG_PORT_TH 0x0078 /* Port Threshold */
|
||||
#define SWITCH_REG_PHY_CNTL2 0x007C /* PHY Control 2 */
|
||||
#define SWITCH_REG_PHY_CNTL3 0x0080 /* PHY Control 3 */
|
||||
#define SWITCH_REG_PRI_CNTL 0x0084 /* Priority Control */
|
||||
#define SWITCH_REG_PHY_CNTL4 0x00A0 /* PHY Control 4 */
|
||||
#define SWITCH_REG_EMPTY_CNT 0x00A4 /* Empty Count */
|
||||
#define SWITCH_REG_PORT_CNTLS 0x00A8 /* Port Control Select */
|
||||
#define SWITCH_REG_PORT_CNTL 0x00AC /* Port Control */
|
||||
#define SWITCH_REG_INT_STATUS 0x00B0 /* Interrupt Status */
|
||||
#define SWITCH_REG_INT_MASK 0x00B4 /* Interrupt Mask */
|
||||
#define SWITCH_REG_GPIO_CONF0 0x00B8 /* GPIO Configuration 0 */
|
||||
#define SWITCH_REG_GPIO_CONF2 0x00BC /* GPIO Configuration 1 */
|
||||
#define SWITCH_REG_WDOG0 0x00C0 /* Watchdog 0 */
|
||||
#define SWITCH_REG_WDOG1 0x00C4 /* Watchdog 1 */
|
||||
|
||||
#define SWITCH_REG_SEND_HBADDR 0x00D0
|
||||
#define SWITCH_REG_SEND_LBADDR 0x00D4
|
||||
#define SWITCH_REG_RECV_HBADDR 0x00D8
|
||||
#define SWITCH_REG_RECV_LBADDR 0x00DC
|
||||
#define SWITCH_REG_SHDA 0x00D0 /* Send High Descriptors Address */
|
||||
#define SWITCH_REG_SLDA 0x00D4 /* Send Low Descriptors Address */
|
||||
#define SWITCH_REG_RHDA 0x00D8 /* Receive High Descriptor Address */
|
||||
#define SWITCH_REG_RLDA 0x00DC /* Receive Low Descriptor Address */
|
||||
#define SWITCH_REG_SHWA 0x00E0 /* Send High Working Address */
|
||||
#define SWITCH_REG_SLWA 0x00E4 /* Send Low Working Address */
|
||||
#define SWITCH_REG_RHWA 0x00E8 /* Receive High Working Address */
|
||||
#define SWITCH_REG_RLWA 0x00EC /* Receive Low Working Address */
|
||||
|
||||
#define SWITCH_REG_TIMER_INT 0x00F0
|
||||
#define SWITCH_REG_TIMER 0x00F4
|
||||
#define SWITCH_REG_TIMER_INT 0x00F0 /* Timer */
|
||||
#define SWITCH_REG_TIMER 0x00F4 /* Timer Interrupt */
|
||||
|
||||
#define SWITCH_REG_PORT0_LED 0x0100
|
||||
#define SWITCH_REG_PORT1_LED 0x0104
|
||||
@ -79,7 +99,7 @@
|
||||
#define CODE_CLKS_200 1 /* 200 MHz */
|
||||
#define CODE_CLKS_225 2 /* 225 MHz */
|
||||
#define CODE_CLKS_250 3 /* 250 MHz */
|
||||
#define CODE_NAB ONEBIT(24) /* NAND boot */
|
||||
#define CODE_NAB BIT(24) /* NAND boot */
|
||||
#define CODE_PK_MASK BITMASK(1) /* Package type */
|
||||
#define CODE_PK_SHIFT 29
|
||||
#define CODE_PK_BGA 0 /* BGA package */
|
||||
@ -92,7 +112,7 @@
|
||||
#define MEMCTRL_SDRS_16M 0x03
|
||||
#define MEMCTRL_SDRS_64M 0x04
|
||||
#define MEMCTRL_SDRS_128M 0x05
|
||||
#define MEMCTRL_SDR1_ENABLE ONEBIT(5) /* enable SDRAM bank 1 */
|
||||
#define MEMCTRL_SDR1_ENABLE BIT(5) /* enable SDRAM bank 1 */
|
||||
|
||||
#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
|
||||
#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
|
||||
@ -103,6 +123,91 @@
|
||||
#define MEMCTRL_SRS_2M 0x03 /* 2MB */
|
||||
#define MEMCTRL_SRS_4M 0x04 /* 4MB */
|
||||
|
||||
/* Port bits used in various registers */
|
||||
#define SWITCH_PORT_PHY0 BIT(0)
|
||||
#define SWITCH_PORT_PHY1 BIT(1)
|
||||
#define SWITCH_PORT_PHY2 BIT(2)
|
||||
#define SWITCH_PORT_PHY3 BIT(3)
|
||||
#define SWITCH_PORT_PHY4 BIT(4)
|
||||
#define SWITCH_PORT_MII BIT(5)
|
||||
#define SWITCH_PORT_CPU BIT(6)
|
||||
|
||||
/* Port bit shorthands */
|
||||
#define SWITCH_PORTS_PHY 0x1F /* phy ports */
|
||||
#define SWITCH_PORTS_NOCPU 0x3F /* physical ports */
|
||||
#define SWITCH_PORTS_ALL 0x7F /* all ports */
|
||||
|
||||
/* CPUP_CONF register bits */
|
||||
#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */
|
||||
#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */
|
||||
#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */
|
||||
|
||||
/* PORT_CONF0 register bits */
|
||||
#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */
|
||||
#define PORT_CONF0_EMCP_SHIFT 8 /* Enable All MC Packets */
|
||||
#define PORT_CONF0_BP_SHIFT 16 /* Enable Back Pressure */
|
||||
|
||||
/* PORT_CONF1 register bits */
|
||||
#define PORT_CONF1_DISL_SHIFT 0 /* Disable Learning */
|
||||
#define PORT_CONF1_BS_SHIFT 6 /* Blocking State */
|
||||
#define PORT_CONF1_BM_SHIFT 12 /* Blocking Mode */
|
||||
|
||||
/* SEND_TRIG register bits */
|
||||
#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */
|
||||
#define SEND_TRIG_STH BIT(1) /* Send Trigger High */
|
||||
|
||||
/* BW_CNTL0/BW_CNTL1 register bits */
|
||||
#define BW_CNTL_DISABLE 0x00
|
||||
#define BW_CNTL_64K 0x01
|
||||
#define BW_CNTL_128K 0x02
|
||||
#define BW_CNTL_256K 0x03
|
||||
#define BW_CNTL_512K 0x04
|
||||
#define BW_CNTL_1M 0x05
|
||||
#define BW_CNTL_4M 0x06
|
||||
#define BW_CNTL_10M 0x07
|
||||
|
||||
#define P4TBC_SHIFT 0
|
||||
#define P4RBC_SHIFT 4
|
||||
#define P5TBC_SHIFT 8
|
||||
#define P5RBC_SHIFT 12
|
||||
|
||||
/* PHY_CNTL0 register bits */
|
||||
#define PHY_CNTL0_PHYA_MASK BITMASK(5)
|
||||
#define PHY_CNTL0_PHYR_MASK BITMASK(5)
|
||||
#define PHY_CNTL0_PHYR_SHIFT 8
|
||||
#define PHY_CNTL0_WC BIT(13) /* Write Command */
|
||||
#define PHY_CNTL0_RC BIT(14) /* Read Command */
|
||||
#define PHY_CNTL0_WTD_MASK BIT(16) /* Read Command */
|
||||
#define PHY_CNTL0_WTD_SHIFT 16
|
||||
|
||||
/* PHY_CNTL1 register bits */
|
||||
#define PHY_CNTL1_WOD BIT(0) /* Write Operation Done */
|
||||
#define PHY_CNTL1_ROD BIT(1) /* Read Operation Done */
|
||||
#define PHY_CNTL1_RD_MASK BITMASK(16)
|
||||
#define PHY_CNTL1_RD_SHIFT 16
|
||||
|
||||
/* PHY_CNTL2 register bits */
|
||||
#define PHY_CNTL2_ANE_SHIFT 0 /* Auto Negotiation Enable */
|
||||
#define PHY_CNTL2_SC_SHIFT 5 /* Speed Control */
|
||||
#define PHY_CNTL2_DC_SHIFT 10 /* Duplex Control */
|
||||
#define PHY_CNTL2_FNCV_SHIFT 15 /* Recommended FC Value */
|
||||
#define PHY_CNTL2_PHYR_SHIFT 20 /* PHY reset */
|
||||
#define PHY_CNTL2_AMDIX_SHIFT 25 /* Auto MDIX enable */
|
||||
/* PHY_CNTL2_RMAE is bad in datasheet */
|
||||
#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */
|
||||
|
||||
/* PORT_TH register bits */
|
||||
#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */
|
||||
#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */
|
||||
#define PORT_TH_CPUT_MASK BITMASK(8)
|
||||
#define PORT_TH_CPUHT_SHIFT 16 /* CPU Hold Threshold */
|
||||
#define PORT_TH_CPUHT_MASK BITMASK(8)
|
||||
#define PORT_TH_CPURT_SHIFT 24 /* CPU Release Threshold */
|
||||
#define PORT_TH_CPURT_MASK BITMASK(8)
|
||||
|
||||
/* EMPTY_CNT register bits */
|
||||
#define EMPTY_CNT_EBGB_MASK BITMASK(9) /* Empty Blocks in the Global Buffer */
|
||||
|
||||
/* GPIO_CONF0 register bits */
|
||||
#define GPIO_CONF0_MASK BITMASK(8)
|
||||
#define GPIO_CONF0_IM_SHIFT 0
|
||||
@ -114,14 +219,39 @@
|
||||
#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
|
||||
#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
|
||||
|
||||
/* INT_STATUS/INT_MASK register bits */
|
||||
#define SWITCH_INT_SHD BIT(0) /* Send High Done */
|
||||
#define SWITCH_INT_SLD BIT(1) /* Send Low Done */
|
||||
#define SWITCH_INT_RHD BIT(2) /* Receive High Done */
|
||||
#define SWITCH_INT_RLD BIT(3) /* Receive Low Done */
|
||||
#define SWITCH_INT_HDF BIT(4) /* High Descriptor Full */
|
||||
#define SWITCH_INT_LDF BIT(5) /* Low Descriptor Full */
|
||||
#define SWITCH_INT_P0QF BIT(6) /* Port0 Queue Full */
|
||||
#define SWITCH_INT_P1QF BIT(7) /* Port1 Queue Full */
|
||||
#define SWITCH_INT_P2QF BIT(8) /* Port2 Queue Full */
|
||||
#define SWITCH_INT_P3QF BIT(9) /* Port3 Queue Full */
|
||||
#define SWITCH_INT_P4QF BIT(10) /* Port4 Queue Full */
|
||||
#define SWITCH_INT_P5QF BIT(11) /* Port5 Queue Full */
|
||||
#define SWITCH_INT_CPQF BIT(13) /* CPU Queue Full */
|
||||
#define SWITCH_INT_GQF BIT(14) /* Global Queue Full */
|
||||
#define SWITCH_INT_MD BIT(15) /* Must Drop */
|
||||
#define SWITCH_INT_BCS BIT(16) /* BC Storm */
|
||||
#define SWITCH_INT_PSC BIT(18) /* Port Status Change */
|
||||
#define SWITCH_INT_ID BIT(19) /* Intruder Detected */
|
||||
#define SWITCH_INT_W0TE BIT(20) /* Watchdog 0 Timer Expired */
|
||||
#define SWITCH_INT_W1TE BIT(21) /* Watchdog 1 Timer Expired */
|
||||
#define SWITCH_INT_RDE BIT(22) /* Receive Descriptor Error */
|
||||
#define SWITCH_INT_SDE BIT(23) /* Send Descriptor Error */
|
||||
#define SWITCH_INT_CPUH BIT(24) /* CPU Hold */
|
||||
|
||||
/* TIMER_INT register bits */
|
||||
#define TIMER_INT_TOS ONEBIT(1) /* time-out status */
|
||||
#define TIMER_INT_TOM ONEBIT(16) /* mask time-out interrupt */
|
||||
#define TIMER_INT_TOS BIT(0) /* time-out status */
|
||||
#define TIMER_INT_TOM BIT(16) /* mask time-out interrupt */
|
||||
|
||||
/* TIMER register bits */
|
||||
#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */
|
||||
#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */
|
||||
#define TIMER_TE ONEBIT(16) /* timer enable bit */
|
||||
#define TIMER_TE BIT(16) /* timer enable bit */
|
||||
|
||||
/* PORTx_LED register bits */
|
||||
#define LED_MODE_MASK BITMASK(4)
|
||||
@ -145,4 +275,4 @@
|
||||
#define LED1_IV_SHIFT 13 /* LED1 input value shift */
|
||||
#define LED2_IV_SHIFT 14 /* LED2 input value shift */
|
||||
|
||||
#endif /* _ADM5120_SWITCH_H */
|
||||
#endif /* _ADM5120_SWITCH_H_ */
|
||||
|
Loading…
Reference in New Issue
Block a user