From f9d4873d3a8123c3253f81967d405e2df771682f Mon Sep 17 00:00:00 2001 From: Xiangfu Liu Date: Thu, 25 Feb 2010 00:47:23 +0800 Subject: [PATCH] [u-boot] remove useless files --- .../0001-add-xburst-platform-files.patch | 3324 +---------------- .../patches/0002-add-xburst-support.patch | 194 +- 2 files changed, 78 insertions(+), 3440 deletions(-) diff --git a/target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch b/target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch index 3fd509916..e2741e478 100644 --- a/target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch +++ b/target/linux/xburst/image/u-boot/patches/0001-add-xburst-platform-files.patch @@ -7,50 +7,34 @@ From: Xiangfu Liu board/qi_lb60/Makefile | 38 board/qi_lb60/config.mk | 31 - board/qi_lb60/flash.c | 50 - board/qi_lb60/qi_lb60.c | 107 + + board/qi_lb60/qi_lb60.c | 122 + board/qi_lb60/u-boot-nand.lds | 63 board/qi_lb60/u-boot.lds | 63 - cpu/mips/jz4740.c | 574 ++++ - cpu/mips/jz4740_cpm_test.c | 98 + + cpu/mips/jz4740.c | 571 ++++ cpu/mips/jz4740_nand.c | 199 ++ - cpu/mips/jz_cs8900.c | 397 +++ - cpu/mips/jz_cs8900.h | 258 ++ - cpu/mips/jz_eth.c | 376 +++ - cpu/mips/jz_eth.h | 267 ++ cpu/mips/jz_i2c.c | 234 ++ - cpu/mips/jz_lcd.c | 643 +++++ - cpu/mips/jz_lcd.h | 1020 ++++++++ cpu/mips/jz_mmc.c | 1404 +++++++++++ cpu/mips/jz_mmc.h | 113 + - cpu/mips/jz_serial.c | 167 + + cpu/mips/jz_serial.c | 159 + cpu/mips/mmc_protocol.h | 273 ++ cpu/mips/qi_lb60_gpm940b0.c | 420 +++ cpu/mips/qi_lb60_gpm940b0.h | 212 ++ cpu/mips/usb_boot.S | 880 +++++++ include/asm-mips/jz4740.h | 4880 +++++++++++++++++++++++++++++++++++++ - include/configs/qi_lb60.h | 213 ++ + include/configs/qi_lb60.h | 215 ++ nand_spl/board/qi_lb60/Makefile | 104 + nand_spl/board/qi_lb60/config.mk | 34 nand_spl/board/qi_lb60/u-boot.lds | 63 - nand_spl/nand_boot_jz4740.c | 456 +++ - 29 files changed, 13637 insertions(+), 0 deletions(-) + nand_spl/nand_boot_jz4740.c | 438 +++ + 21 files changed, 10516 insertions(+), 0 deletions(-) create mode 100644 board/qi_lb60/Makefile create mode 100644 board/qi_lb60/config.mk - create mode 100644 board/qi_lb60/flash.c create mode 100644 board/qi_lb60/qi_lb60.c create mode 100644 board/qi_lb60/u-boot-nand.lds create mode 100644 board/qi_lb60/u-boot.lds create mode 100644 cpu/mips/jz4740.c - create mode 100644 cpu/mips/jz4740_cpm_test.c create mode 100644 cpu/mips/jz4740_nand.c - create mode 100644 cpu/mips/jz_cs8900.c - create mode 100644 cpu/mips/jz_cs8900.h - create mode 100644 cpu/mips/jz_eth.c - create mode 100644 cpu/mips/jz_eth.h create mode 100644 cpu/mips/jz_i2c.c - create mode 100644 cpu/mips/jz_lcd.c - create mode 100644 cpu/mips/jz_lcd.h create mode 100644 cpu/mips/jz_mmc.c create mode 100644 cpu/mips/jz_mmc.h create mode 100644 cpu/mips/jz_serial.c @@ -147,68 +131,12 @@ index 0000000..858e6a2 +# RAM version +TEXT_BASE = 0x80100000 +endif -diff --git a/board/qi_lb60/flash.c b/board/qi_lb60/flash.c -new file mode 100644 -index 0000000..891c604 ---- /dev/null -+++ b/board/qi_lb60/flash.c -@@ -0,0 +1,50 @@ -+/* -+ * (C) Copyright 2009 PI -+ * xiangfu liu, -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 3 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include -+ -+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -+ -+/* -+ * flash_init() -+ * -+ * sets up flash_info and returns size of FLASH (bytes) -+ */ -+unsigned long flash_init (void) -+{ -+ return (0); -+} -+ -+int flash_erase (flash_info_t * info, int s_first, int s_last) -+{ -+ printf ("flash_erase not implemented\n"); -+ return 0; -+} -+ -+void flash_print_info (flash_info_t * info) -+{ -+ printf ("flash_print_info not implemented\n"); -+} -+ -+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -+{ -+ printf ("write_buff not implemented\n"); -+ return (-1); -+} diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c new file mode 100644 -index 0000000..54625c3 +index 0000000..aa7b85b --- /dev/null +++ b/board/qi_lb60/qi_lb60.c -@@ -0,0 +1,107 @@ +@@ -0,0 +1,122 @@ +/* + * Authors: Xiangfu Liu + * @@ -223,6 +151,8 @@ index 0000000..54625c3 +#include +#include + ++DECLARE_GLOBAL_DATA_PTR; ++ +static void gpio_init(void) +{ + /* @@ -236,11 +166,6 @@ index 0000000..54625c3 + __gpio_as_sdram_32bit(); + + /* -+ * Initialize UART0 pins -+ */ -+ __gpio_as_uart0(); -+ -+ /* + * Initialize LCD pins + */ + __gpio_as_lcd_18bit(); @@ -254,17 +179,31 @@ index 0000000..54625c3 + * Initialize Other pins + */ + unsigned int i; -+ for (i = 0; i < 8; i++) { -+ __gpio_as_output(GPIO_KEYOUT_BASE + i); -+ __gpio_set_pin(GPIO_KEYOUT_BASE + i); -+ } -+ + for (i = 0; i < 7; i++){ + __gpio_as_input(GPIO_KEYIN_BASE + i); + __gpio_enable_pull(GPIO_KEYIN_BASE + i); + } -+ /* __gpio_as_input( GPIO_KEYIN_8 ); */ -+ /* __gpio_enable_pull( GPIO_KEYIN_8 ); */ ++ ++ for (i = 0; i < 8; i++) { ++ __gpio_as_output(GPIO_KEYOUT_BASE + i); ++ __gpio_clear_pin(GPIO_KEYOUT_BASE + i); ++ } ++ ++ /* ++ * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the ++ * same gpio, init the gpio as uart0 cause a keyboard bug. so for ++ * end user we disable the uart0 ++ */ ++ if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){ ++ /* if pressed [S] */ ++ printf("[S] pressed, enable UART0\n"); ++ gd->boot_option = 5; ++ __gpio_as_uart0(); ++ } else { ++ printf("[S] not pressed, disable UART0\n"); ++ __gpio_as_input(GPIO_KEYIN_8); ++ __gpio_enable_pull(GPIO_KEYIN_8); ++ } + + __gpio_as_output(GPIO_AUDIO_POP); + __gpio_set_pin(GPIO_AUDIO_POP); @@ -284,6 +223,11 @@ index 0000000..54625c3 + + __gpio_as_input(GPIO_USB_DETECT); + __gpio_enable_pull(GPIO_USB_DETECT); ++ ++ if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) { ++ printf("[M] pressed, boot from sd card\n"); ++ gd->boot_option = 1; ++ } +} + +static void cpm_init(void) @@ -309,7 +253,6 @@ index 0000000..54625c3 + +int checkboard (void) +{ -+ DECLARE_GLOBAL_DATA_PTR; + + printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n", + gd->cpu_clk/1000000); @@ -456,10 +399,10 @@ index 0000000..a15a96e +} diff --git a/cpu/mips/jz4740.c b/cpu/mips/jz4740.c new file mode 100644 -index 0000000..87e0ccf +index 0000000..c32d15e --- /dev/null +++ b/cpu/mips/jz4740.c -@@ -0,0 +1,574 @@ +@@ -0,0 +1,571 @@ +/* + * Jz4740 common routines + * @@ -484,7 +427,6 @@ index 0000000..87e0ccf + +#include + -+#ifdef CONFIG_JZ4740 +#include +#include +#include @@ -1032,112 +974,7 @@ index 0000000..87e0ccf +#endif /* CONFIG_NAND_SPL */ + +/* End of timer routine. */ -+ -+#endif /* CONFIG_JZ4740 */ -diff --git a/cpu/mips/jz4740_cpm_test.c b/cpu/mips/jz4740_cpm_test.c -new file mode 100644 -index 0000000..70ebbf0 ---- /dev/null -+++ b/cpu/mips/jz4740_cpm_test.c -@@ -0,0 +1,98 @@ -+#include -+ -+#ifdef CONFIG_JZ4740 -+#include -+#include -+#include -+#include /* virt_to_phys() */ -+#define JZ4740_CPM_TEST -+ -+ -+ -+int cpm_value; -+void mdelay(int dly) -+{ -+ udelay(dly * 1000); -+} -+ -+int myatoi(char *string) -+{ -+ int res = 0; -+ while (*string>='0' && *string <='9') -+ { -+ res *= 10; -+ res += *string-'0'; -+ string++; -+ } -+ -+ return res; -+} -+ -+int myhatoi(char *string) -+{ -+ int res = 0; -+ -+ if ( *string != '0' || *(string+1) != 'x' ) { -+ return 0; -+ } -+ -+ string += 2; -+ -+ while ( *string ) -+ { -+ res *= 16; -+ if (*string>='0' && *string <='9') -+ res += *string-'0'; -+ else if (*string>='a' && *string <='f') -+ res += *string-'a' + 10; -+ else -+ return res; -+ -+ string++; -+ } -+ -+ return res; -+} -+ -+int atoi( char * string ) -+{ -+ if ( *string == '0' && *(string+1) == 'x' ) { -+ return myhatoi(string); -+ } -+ else -+ return myatoi(string); -+} -+ -+void cpm_add_test(void) -+{ -+ pll_add_test(cpm_value); -+ /* sdram_add_test(cpm_value); */ -+ calc_clocks_add_test(); -+} -+ -+int do_jz_cpmtest_function(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -+{ -+ -+ if ( !strncmp(argv[1], "add", 3 ) ) { -+ if ( argc == 3 ) { -+ cpm_value = atoi( argv[2] ); -+ printf("cpm value:%d\n",cpm_value); -+ if((cpm_value >= 999) || (cpm_value <= 100)) { -+ printf("param is wrong!\n"); -+ } -+ cpm_value *= 1000000; -+ cpm_add_test(); -+ } -+ } else { -+ printf("command is wrong!\n"); -+ } -+ return 0; -+} -+ -+U_BOOT_CMD( -+ cpm, 4, 1, do_jz_cpmtest_function, -+ "cpm:\t - Usage: cpmtest [add][cpm_value]\n", -+ NULL -+ ); -+ -+#endif /* CONFIG_JZ4740 */ +\ No newline at end of file diff --git a/cpu/mips/jz4740_nand.c b/cpu/mips/jz4740_nand.c new file mode 100644 index 0000000..c1d1511 @@ -1343,1328 +1180,6 @@ index 0000000..c1d1511 + return 0; +} +#endif /* (CONFIG_SYS_CMD_NAND) */ -diff --git a/cpu/mips/jz_cs8900.c b/cpu/mips/jz_cs8900.c -new file mode 100644 -index 0000000..0ddd5ff ---- /dev/null -+++ b/cpu/mips/jz_cs8900.c -@@ -0,0 +1,397 @@ -+/* -+ * Cirrus Logic CS8900A Ethernet -+ * -+ * (C) 2003 Wolfgang Denk, wd@denx.de -+ * Extension to synchronize ethaddr environment variable -+ * against value in EEPROM -+ * -+ * (C) Copyright 2002 -+ * Sysgo Real-Time Solutions, GmbH -+ * Marius Groeger -+ * -+ * Copyright (C) 1999 Ben Williamson -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is loaded into SRAM in bootstrap mode, where it waits -+ * for commands on UART1 to read and write memory, jump to code etc. -+ * A design goal for this program is to be entirely independent of the -+ * target board. Anything with a CL-PS7111 or EP7211 should be able to run -+ * this code in bootstrap mode. All the board specifics can be handled on -+ * the host. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+#include -+#ifndef CONFIG_FPGA -+#if defined(CONFIG_JZ4740) || defined(CONFIG_JZ4750) -+#include -+#include -+#if defined(CONFIG_JZ4740) -+#include -+#elif defined(CONFIG_JZ4750) -+#include -+#endif -+#include -+struct eth_device *dev; -+#define CS8900_BASE ((u32)(dev->iobase)) -+#define CONFIG_DRIVER_CS8900 -+#define CS8900_BUS16 -+#include -+#include -+ -+#include "jz_cs8900.h" -+ -+#ifdef CONFIG_DRIVER_CS8900 -+ -+#if (CONFIG_COMMANDS & CFG_CMD_NET) -+ -+#undef DEBUG -+ -+/* packet page register access functions */ -+ -+#ifdef CS8900_BUS32 -+/* we don't need 16 bit initialisation on 32 bit bus */ -+#define get_reg_init_bus(x) get_reg((x)) -+#else -+static unsigned short get_reg_init_bus (int regno) -+{ -+ /* force 16 bit busmode */ -+ volatile unsigned char c; -+ /* c = CS8900_BUS16_0; */ -+ /* c = CS8900_BUS16_1; */ -+ /* c = CS8900_BUS16_0; */ -+ /* c = CS8900_BUS16_1; */ -+ /* c = CS8900_BUS16_0; */ -+ -+ CS8900_PPTR = regno; -+ /* udelay(100); */ -+ -+ return (unsigned short) CS8900_PDATA; -+} -+#endif -+ -+static unsigned short get_reg (int regno) -+{ -+ CS8900_PPTR = regno; -+ return (unsigned short) CS8900_PDATA; -+} -+ -+ -+static void put_reg (int regno, unsigned short val) -+{ -+ CS8900_PPTR = regno; -+ CS8900_PDATA = val; -+} -+ -+static void eth_reset (void) -+{ -+ int tmo; -+ unsigned short us; -+ -+ /* reset NIC */ -+ put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset); -+ -+ /* wait for 200ms */ -+ udelay (200000); -+ /* Wait until the chip is reset */ -+ -+ tmo = get_timer (0) + 1 * CONFIG_SYS_HZ; -+ while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0) -+ && tmo < get_timer (0)) -+ /*NOP*/; -+} -+ -+static void eth_reginit (void) -+{ -+ /* receive only error free packets addressed to this card */ -+ put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK); -+ /* do not generate any interrupts on receive operations */ -+ put_reg (PP_RxCFG, 0); -+ /* do not generate any interrupts on transmit operations */ -+ put_reg (PP_TxCFG, 0); -+ /* do not generate any interrupts on buffer operations */ -+ put_reg (PP_BufCFG, 0); -+ /* enable transmitter/receiver mode */ -+ put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx); -+} -+ -+static void cs8900_get_enetaddr (uchar * addr) -+{ -+ int i; -+ unsigned char env_enetaddr[6]; -+ char *tmp = getenv ("ethaddr"); -+ char *end; -+ -+ for (i=0; i<6; i++) { -+ env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; -+ if (tmp) -+ tmp = (*end) ? end+1 : end; -+ } -+ -+ /* verify chip id */ -+ if (get_reg_init_bus (PP_ChipID) != 0x630e) -+ return; -+ eth_reset (); -+ if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) == -+ (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) { -+ -+ /* Load the MAC from EEPROM */ -+ for (i = 0; i < 6 / 2; i++) { -+ unsigned int Addr; -+ -+ Addr = get_reg (PP_IA + i * 2); -+ addr[i * 2] = Addr & 0xFF; -+ addr[i * 2 + 1] = Addr >> 8; -+ } -+ -+ if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && -+ memcmp(env_enetaddr, addr, 6) != 0) { -+ printf ("\nWarning: MAC addresses don't match:\n"); -+ printf ("\tHW MAC address: " -+ "%02X:%02X:%02X:%02X:%02X:%02X\n", -+ addr[0], addr[1], -+ addr[2], addr[3], -+ addr[4], addr[5] ); -+ printf ("\t\"ethaddr\" value: " -+ "%02X:%02X:%02X:%02X:%02X:%02X\n", -+ env_enetaddr[0], env_enetaddr[1], -+ env_enetaddr[2], env_enetaddr[3], -+ env_enetaddr[4], env_enetaddr[5]) ; -+ debug ("### Set MAC addr from environment\n"); -+ memcpy (addr, env_enetaddr, 6); -+ } -+ if (!tmp) { -+ char ethaddr[20]; -+ sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", -+ addr[0], addr[1], -+ addr[2], addr[3], -+ addr[4], addr[5]) ; -+ debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr); -+ setenv ("ethaddr", ethaddr); -+ } -+ -+ } -+} -+ -+static void jz_eth_halt (struct eth_device *dev) -+{ -+ /* disable transmitter/receiver mode */ -+ put_reg (PP_LineCTL, 0); -+ -+ /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */ -+ get_reg_init_bus (PP_ChipID); -+} -+ -+static int jz_eth_init (struct eth_device* dev, bd_t * bd) -+{ -+ u16 id; -+ -+ dev = dev; -+ -+ -+ /* verify chip id */ -+ id = get_reg_init_bus (PP_ChipID); -+ if (id != 0x630e) { -+ printf ("CS8900 jz_eth_init error!\n"); -+ return 0; -+ } -+ -+ eth_reset (); -+ /* set the ethernet address */ -+ /* printf("MAC = %02x:%02x:%02x:%02x:%02x:%02x\r\n", */ -+ /* bd->bi_enetaddr[5],bd->bi_enetaddr[4], */ -+ /* bd->bi_enetaddr[3],bd->bi_enetaddr[2], */ -+ /* bd->bi_enetaddr[1],bd->bi_enetaddr[0]); */ -+ -+ put_reg (PP_IA + 0, bd->bi_enetaddr[0] | (bd->bi_enetaddr[1] << 8)); -+ put_reg (PP_IA + 2, bd->bi_enetaddr[2] | (bd->bi_enetaddr[3] << 8)); -+ put_reg (PP_IA + 4, bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8)); -+ -+ eth_reginit (); -+ return 0; -+} -+ -+/* Get a data block via Ethernet */ -+static int jz_eth_rx (struct eth_device* dev) -+{ -+ int i; -+ unsigned short rxlen; -+ unsigned short *addr; -+ unsigned short status; -+ dev = dev; -+ status = get_reg (PP_RER); -+ -+ if ((status & PP_RER_RxOK) == 0) -+ return 0; -+ -+ status = CS8900_RTDATA; /* stat */ -+ rxlen = CS8900_RTDATA; /* len */ -+ -+#ifdef DEBUG -+ if (rxlen > PKTSIZE_ALIGN + PKTALIGN) -+ printf ("packet too big!\n"); -+#endif -+ for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0; -+ i--) -+ *addr++ = CS8900_RTDATA; -+ if (rxlen & 1) -+ *addr++ = CS8900_RTDATA; -+ -+ /* Pass the packet up to the protocol layers. */ -+ NetReceive (NetRxPackets[0], rxlen); -+ -+ return rxlen; -+} -+ -+/* Send a data block via Ethernet. */ -+static int jz_eth_send (struct eth_device* dev,volatile void *packet, int length) -+{ -+ volatile unsigned short *addr; -+ int tmo; -+ unsigned short s; -+ dev = dev; -+ -+retry: -+ /* initiate a transmit sequence */ -+ CS8900_TxCMD = PP_TxCmd_TxStart_Full; -+ CS8900_TxLEN = length; -+ -+ /* Test to see if the chip has allocated memory for the packet */ -+ if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) { -+ /* Oops... this should not happen! */ -+#ifdef DEBUG -+ printf ("cs: unable to send packet; retrying...\n"); -+#endif -+ for (tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; get_timer (0) < tmo;) -+ /*NOP*/; -+ eth_reset (); -+ eth_reginit (); -+ goto retry; -+ } -+ -+ /* Write the contents of the packet */ -+ /* assume even number of bytes */ -+ for (addr = packet; length > 0; length -= 2) -+ CS8900_RTDATA = *addr++; -+ -+ /* wait for transfer to succeed */ -+ tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; -+ while ((s = get_reg (PP_TER) & ~0x1F) == 0) { -+ if (get_timer (0) >= tmo) -+ break; -+ } -+ -+ /* nothing */ ; -+ if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) { -+#ifdef DEBUG -+ printf ("\ntransmission error %#x\n", s); -+#endif -+ } -+ -+ return 0; -+} -+ -+static void cs8900_e2prom_ready(void) -+{ -+ while(get_reg(PP_SelfST) & SI_BUSY); -+} -+ -+/***********************************************************/ -+/* read a 16-bit word out of the EEPROM */ -+/***********************************************************/ -+ -+static int cs8900_e2prom_read(unsigned char addr, unsigned short *value) -+{ -+ cs8900_e2prom_ready(); -+ put_reg(PP_EECMD, EEPROM_READ_CMD | addr); -+ cs8900_e2prom_ready(); -+ *value = get_reg(PP_EEData); -+ -+ return 0; -+} -+ -+ -+/***********************************************************/ -+/* write a 16-bit word into the EEPROM */ -+/***********************************************************/ -+ -+static int cs8900_e2prom_write(unsigned char addr, unsigned short value) -+{ -+ cs8900_e2prom_ready(); -+ put_reg(PP_EECMD, EEPROM_WRITE_EN); -+ cs8900_e2prom_ready(); -+ put_reg(PP_EEData, value); -+ put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr); -+ cs8900_e2prom_ready(); -+ put_reg(PP_EECMD, EEPROM_WRITE_DIS); -+ cs8900_e2prom_ready(); -+ -+ return 0; -+} -+int jz_enet_initialize(bd_t *bis) -+{ -+ -+ u32 reg; -+ -+ dev = (struct eth_device *) malloc(sizeof *dev); -+ memset(dev, 0, sizeof *dev); -+ -+#if defined(CONFIG_JZ4740) -+#define RD_N_PIN (32 + 29) -+#define WE_N_PIN (32 + 30) -+#define CS4_PIN (32 + 28) -+ __gpio_as_func0(CS4_PIN); -+ __gpio_as_func0(RD_N_PIN); -+ __gpio_as_func0(WE_N_PIN); -+ -+ reg = REG_EMC_SMCR4; -+ reg = (reg & (~EMC_SMCR_BW_MASK)) | EMC_SMCR_BW_16BIT; -+ REG_EMC_SMCR4 = reg; -+ dev->iobase = 0xa8000000; -+ -+#elif defined(CONFIG_JZ4750) -+#define RD_N_PIN (32*2 +25) -+#define WE_N_PIN (32*2 +26) -+#define CS3_PIN (32*2 +23) -+ __gpio_as_func0(CS3_PIN); -+ __gpio_as_func0(RD_N_PIN); -+ __gpio_as_func0(WE_N_PIN); -+ -+ reg = REG_EMC_SMCR3; -+ reg = (reg & (~EMC_SMCR_BW_MASK)) | EMC_SMCR_BW_16BIT; -+ REG_EMC_SMCR3 = reg; -+ dev->iobase = 0xac000000; -+#endif -+ -+ sprintf(dev->name, "JZ ETHERNET"); -+ dev->priv = 0; -+ dev->init = jz_eth_init; -+ dev->halt = jz_eth_halt; -+ dev->send = jz_eth_send; -+ dev->recv = jz_eth_rx; -+ -+ eth_register(dev); -+ -+ return 1; -+} -+ -+ -+#endif /* COMMANDS & CFG_NET */ -+ -+#endif /* CONFIG_DRIVER_CS8900 */ -+#endif /* defined(CONFIG_JZ4740) || defined(CONFIG_JZ4750) */ -+#endif /* !CONFIG_FPGA */ -diff --git a/cpu/mips/jz_cs8900.h b/cpu/mips/jz_cs8900.h -new file mode 100644 -index 0000000..5f6fdec ---- /dev/null -+++ b/cpu/mips/jz_cs8900.h -@@ -0,0 +1,258 @@ -+/* -+ * Cirrus Logic CS8900A Ethernet -+ * -+ * (C) Copyright 2002 -+ * Sysgo Real-Time Solutions, GmbH -+ * Marius Groeger -+ * -+ * Copyright (C) 1999 Ben Williamson -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is loaded into SRAM in bootstrap mode, where it waits -+ * for commands on UART1 to read and write memory, jump to code etc. -+ * A design goal for this program is to be entirely independent of the -+ * target board. Anything with a CL-PS7111 or EP7211 should be able to run -+ * this code in bootstrap mode. All the board specifics can be handled on -+ * the host. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+ -+#ifdef CONFIG_DRIVER_CS8900 -+ -+/* although the registers are 16 bit, they are 32-bit aligned on the -+ EDB7111. so we have to read them as 32-bit registers and ignore the -+ upper 16-bits. i'm not sure if this holds for the EDB7211. */ -+ -+#ifdef CS8900_BUS16 -+ /* 16 bit aligned registers, 16 bit wide */ -+ #define CS8900_REG u16 -+ #define CS8900_OFF 0x02 -+ #define CS8900_BUS16_0 *(volatile u8 *)(CS8900_BASE+0x00) -+ #define CS8900_BUS16_1 *(volatile u8 *)(CS8900_BASE+0x01) -+#elif defined(CS8900_BUS32) -+ /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ -+ #define CS8900_REG u32 -+ #define CS8900_OFF 0x04 -+#else -+ #error unknown bussize ... -+#endif -+ -+#define CS8900_RTDATA *(volatile CS8900_REG *)(CS8900_BASE+0x00*CS8900_OFF) -+#define CS8900_TxCMD *(volatile CS8900_REG *)(CS8900_BASE+0x02*CS8900_OFF) -+#define CS8900_TxLEN *(volatile CS8900_REG *)(CS8900_BASE+0x03*CS8900_OFF) -+#define CS8900_ISQ *(volatile CS8900_REG *)(CS8900_BASE+0x04*CS8900_OFF) -+#define CS8900_PPTR *(volatile CS8900_REG *)(CS8900_BASE+0x05*CS8900_OFF) -+#define CS8900_PDATA *(volatile CS8900_REG *)(CS8900_BASE+0x06*CS8900_OFF) -+ -+ -+#define ISQ_RxEvent 0x04 -+#define ISQ_TxEvent 0x08 -+#define ISQ_BufEvent 0x0C -+#define ISQ_RxMissEvent 0x10 -+#define ISQ_TxColEvent 0x12 -+#define ISQ_EventMask 0x3F -+ -+/* packet page register offsets */ -+ -+/* bus interface registers */ -+#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */ -+#define PP_ChipRev 0x0002 /* Chip revision, model codes */ -+ -+#define PP_IntReg 0x0022 /* Interrupt configuration */ -+#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */ -+#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */ -+#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */ -+#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */ -+ -+/* status and control registers */ -+ -+#define PP_RxCFG 0x0102 /* Receiver configuration */ -+#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */ -+#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */ -+#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */ -+#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */ -+#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */ -+#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */ -+#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */ -+#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */ -+#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */ -+ -+#define PP_RxCTL 0x0104 /* Receiver control */ -+#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */ -+#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */ -+#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */ -+#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */ -+#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */ -+#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */ -+#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */ -+#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */ -+#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */ -+ -+#define PP_TxCFG 0x0106 /* Transmit configuration */ -+#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */ -+#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */ -+#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */ -+#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */ -+#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */ -+#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */ -+#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */ -+ -+#define PP_TxCmd 0x0108 /* Transmit command status */ -+#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */ -+#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */ -+#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */ -+#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */ -+#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */ -+#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */ -+#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */ -+#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */ -+ -+#define PP_BufCFG 0x010A /* Buffer configuration */ -+#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */ -+#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */ -+#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */ -+#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */ -+#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */ -+#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */ -+#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */ -+#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */ -+#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */ -+ -+#define PP_LineCTL 0x0112 /* Line control */ -+#define PP_LineCTL_Rx 0x0040 /* Enable receiver */ -+#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */ -+#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */ -+#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */ -+#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */ -+#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */ -+#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */ -+#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */ -+ -+#define PP_SelfCTL 0x0114 /* Chip self control */ -+#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */ -+#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */ -+#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */ -+#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */ -+#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */ -+#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */ -+#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */ -+#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */ -+ -+#define PP_BusCTL 0x0116 /* Bus control */ -+#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */ -+#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */ -+#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */ -+#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */ -+#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */ -+#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */ -+#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */ -+#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */ -+ -+#define PP_TestCTL 0x0118 /* Test control */ -+#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */ -+#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */ -+#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */ -+#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */ -+#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */ -+ -+#define PP_ISQ 0x0120 /* Interrupt Status Queue */ -+ -+#define PP_RER 0x0124 /* Receive event */ -+#define PP_RER_IAHash 0x0040 /* Frame hash match */ -+#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */ -+#define PP_RER_RxOK 0x0100 /* Frame received with no errors */ -+#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */ -+#define PP_RER_IA 0x0400 /* Frame address matched IA */ -+#define PP_RER_Broadcast 0x0800 /* Broadcast frame */ -+#define PP_RER_CRC 0x1000 /* Frame had CRC error */ -+#define PP_RER_RUNT 0x2000 /* Runt frame */ -+#define PP_RER_EXTRA 0x4000 /* Frame was too long */ -+ -+#define PP_TER 0x0128 /* Transmit event */ -+#define PP_TER_CRS 0x0040 /* Carrier lost */ -+#define PP_TER_SQE 0x0080 /* Signal Quality Error */ -+#define PP_TER_TxOK 0x0100 /* Packet sent without error */ -+#define PP_TER_Late 0x0200 /* Out of window */ -+#define PP_TER_Jabber 0x0400 /* Stuck transmit? */ -+#define PP_TER_NumCollisions 0x7800 /* Number of collisions */ -+#define PP_TER_16Collisions 0x8000 /* > 16 collisions */ -+ -+#define PP_BER 0x012C /* Buffer event */ -+#define PP_BER_SWint 0x0040 /* Software interrupt */ -+#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */ -+#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */ -+#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */ -+#define PP_BER_RxMiss 0x0400 /* Received frame missed */ -+#define PP_BER_Rx128 0x0800 /* 128 bytes received */ -+#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */ -+ -+#define PP_RxMiss 0x0130 /* Receiver miss counter */ -+ -+#define PP_TxCol 0x0132 /* Transmit collision counter */ -+ -+#define PP_LineSTAT 0x0134 /* Line status */ -+#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */ -+#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */ -+#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */ -+#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */ -+#define PP_LineSTAT_CRS 0x4000 /* Frame being received */ -+ -+#define PP_SelfSTAT 0x0136 /* Chip self status */ -+#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */ -+#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */ -+#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */ -+#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */ -+#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */ -+#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */ -+#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */ -+ -+#define PP_BusSTAT 0x0138 /* Bus status */ -+#define PP_BusSTAT_TxBid 0x0080 /* Tx error */ -+#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */ -+ -+#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */ -+ -+/* initiate transmit registers */ -+ -+#define PP_TxCommand 0x0144 /* Tx Command */ -+#define PP_TxLength 0x0146 /* Tx Length */ -+ -+ -+/* address filter registers */ -+ -+#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */ -+#define PP_IA 0x0158 /* Individual address (MAC) */ -+ -+/* EEPROM Kram */ -+#define SI_BUSY 0x0100 -+#define PP_SelfST 0x0136 /* Self State register */ -+#define PP_EECMD 0x0040 /* NVR Interface Command register */ -+#define PP_EEData 0x0042 /* NVR Interface Data Register */ -+#define EEPROM_WRITE_EN 0x00F0 -+#define EEPROM_WRITE_DIS 0x0000 -+#define EEPROM_WRITE_CMD 0x0100 -+#define EEPROM_READ_CMD 0x0200 -+#define EEPROM_ERASE_CMD 0x0300 -+ -+static int cs8900_e2prom_read(uchar, ushort *); -+static int cs8900_e2prom_write(uchar, ushort); -+ -+#endif /* CONFIG_DRIVER_CS8900 */ -diff --git a/cpu/mips/jz_eth.c b/cpu/mips/jz_eth.c -new file mode 100644 -index 0000000..1ef2516 ---- /dev/null -+++ b/cpu/mips/jz_eth.c -@@ -0,0 +1,376 @@ -+/* Jz ethernet support -+ * -+ * Copyright (c) 2005 -+ * Ingenic Semiconductor, -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+#include -+ -+#if defined(CONFIG_JZ4730) || defined(CONFIG_JZ5730) || defined(CONFIG_FPGA) -+ -+#include -+#include -+#include -+#include -+#include -+#if defined(CONFIG_JZ4730) -+#include -+#endif -+#if defined(CONFIG_JZ4740) -+#include -+#endif -+#if defined(CONFIG_JZ4750) -+#include -+#endif -+#if defined(CONFIG_JZ4750D) -+#include -+#endif -+#if defined(CONFIG_JZ5730) -+#include -+#endif -+ -+#include "jz_eth.h" -+ -+#define MAX_WAIT 1000 -+ -+/* Tx and Rx Descriptor */ -+typedef struct { -+ u32 status; -+ u32 ctrl; -+ u32 addr; -+ u32 next; -+} eth_desc_t; -+ -+#define NUM_RX_DESCS 16 -+#define NUM_TX_DESCS 4 -+ -+static eth_desc_t rx_desc[NUM_RX_DESCS]; -+static eth_desc_t tx_desc[NUM_TX_DESCS]; -+ -+static int next_rx; -+static int next_tx; -+ -+static u32 full_duplex, phy_mode; -+ -+static inline void reset_eth(void) -+{ -+ int i; -+ -+ jz_writel(ETH_BMR, jz_readl(ETH_BMR) | BMR_SWR); -+ -+ for (i = 0; i < MAX_WAIT; i++) { -+ if(!(jz_readl(ETH_BMR) & BMR_SWR)) -+ break; -+ udelay(1); -+ } -+ -+ if (i == MAX_WAIT) -+ printf("Reset eth timeout\n"); -+} -+ -+static inline void enable_eth(void) -+{ -+ jz_writel(ETH_OMR, jz_readl(ETH_OMR) | OMR_ST | OMR_SR); -+} -+ -+static inline void disable_eth(void) -+{ -+ jz_writel(ETH_OMR, jz_readl(ETH_OMR) & ~(OMR_ST | OMR_SR)); -+} -+ -+#define MII_CMD_ADDR(id, offset) (((id) << 11) | ((offset) << 6)) -+#define MII_CMD_READ(id, offset) (MII_CMD_ADDR(id, offset)) -+#define MII_CMD_WRITE(id, offset) (MII_CMD_ADDR(id, offset) | 0x2) -+ -+static u32 mii_read(int phy_id, int offset) -+{ -+ int i; -+ u32 mii_cmd = MII_CMD_READ(phy_id, offset); -+ -+ jz_writel(ETH_MIAR, mii_cmd); -+ -+ /* wait for completion */ -+ for (i = 0; i < MAX_WAIT; i++) { -+ if (!(jz_readl(ETH_MIAR) & 0x1)) -+ break; -+ udelay(1); -+ } -+ -+ if (i == MAX_WAIT) { -+ printf("MII wait timeout\n"); -+ return 0; -+ } -+ -+ return jz_readl(ETH_MIDR) & 0x0000ffff; -+} -+ -+static int autonet_complete(int phy_id) -+{ -+ int i; -+ -+ for (i = 0; i < MAX_WAIT; i++) { -+ if (mii_read(phy_id, MII_SR) & 0x0020) -+ break; /* auto negotiation completed */ -+ udelay(500); -+ } -+ -+ if (i == MAX_WAIT) -+ return -1; /* auto negotiation error */ -+ else -+ return 0; -+} -+ -+static int search_phy(int phy_id) -+{ -+ unsigned int r; -+ r = mii_read(phy_id, 1); -+ if (r!=0 && r!=0xffff) -+ return 1; -+ return 0; -+} -+ -+static void config_phy(int phy_id) -+{ -+ u32 mii_reg5; -+ -+ full_duplex = 0; -+ -+ mii_reg5 = mii_read(phy_id, MII_ANLPA); -+ -+ if (mii_reg5 != 0xffff) { -+ mii_reg5 = mii_read(phy_id, MII_ANLPA); -+ if ((mii_reg5 & 0x0100) || (mii_reg5 & 0x01C0) == 0x0040) -+ full_duplex = 1; -+ -+ phy_mode = mii_reg5 >> 5; -+ -+ printf("ETH: setting %s %s-duplex based on MII tranceiver #%d\n", -+ (phy_mode & MII_ANLPA_100M) ? "100Mbps" : "10Mbps", -+ full_duplex ? "full" : "half", phy_id); -+ } -+} -+ -+static void config_mac(void) -+{ -+ u32 omr, mcr; -+ -+ /* Set MAC address */ -+#define ea eth_get_dev()->enetaddr -+ jz_writel(ETH_MALR, (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]); -+ jz_writel(ETH_MAHR, (ea[5] << 8) | ea[4]); -+ -+ jz_writel(ETH_HTLR, 0); -+ jz_writel(ETH_HTHR, 0); -+ -+ /* Assert the MCR_PS bit in CSR */ -+ if (phy_mode & MII_ANLPA_100M) -+ omr = OMR_SF; -+ else -+ omr = OMR_TTM | OMR_SF; -+ -+ mcr = MCR_TE | MCR_RE | MCR_DBF | MCR_LCC; -+ -+ if (full_duplex) -+ mcr |= MCR_FDX; -+ -+ /* Set the Operation Mode (OMR) and Mac Control (MCR) registers */ -+ jz_writel(ETH_OMR, omr); -+ jz_writel(ETH_MCR, mcr); -+ -+ /* Set the Programmable Burst Length (BMR.PBL, value 1 or 4 is validate) */ -+ jz_writel(ETH_BMR, DMA_BURST << 8); -+ -+ /* Reset csr8 */ -+ jz_readl(ETH_MFCR); /* missed frams counter */ -+} -+ -+/*--------------------------------------------------------------------------- -+ * ETH interface routines -+ *--------------------------------------------------------------------------*/ -+ -+static int jz_send(struct eth_device* dev, volatile void *packet, int length) -+{ -+ volatile eth_desc_t *desc = -+ (volatile eth_desc_t *)((unsigned int)(tx_desc + next_tx) | 0xa0000000); -+ int i; -+ -+ /* tx fifo should always be idle */ -+ desc->addr = virt_to_phys(packet); -+ desc->ctrl |= TD_LS | TD_FS | length; -+ desc->status = T_OWN; -+ -+ jz_flush_dcache(); -+ jz_sync(); -+ -+ /* Start the tx */ -+ jz_writel(ETH_TPDR, 1); -+ -+ i = 0; -+ while (desc->status & T_OWN) { -+ if(i > MAX_WAIT) { -+ printf("ETH TX timeout\n"); -+ break; -+ } -+ udelay(1); -+ i++; -+ } -+ -+ /* Clear done bits */ -+ jz_writel(ETH_SR, DMA_TX_DEFAULT); -+ -+ desc->status = 0; -+ desc->addr = 0; -+ desc->ctrl &= ~(TD_LS | TD_FS); -+ -+ next_tx++; -+ if (next_tx >= NUM_TX_DESCS){ -+ next_tx=0; -+ } -+ -+ return (desc->status); -+} -+ -+static int jz_recv(struct eth_device* dev) -+{ -+ volatile eth_desc_t *desc; -+ int length; -+ u32 status; -+ -+ for(;;) { -+ desc = (volatile eth_desc_t *)((unsigned int)(rx_desc + next_rx) | 0xa0000000); -+ -+ status = desc->status; -+ -+ if (status & R_OWN) { -+ /* Nothing has been received */ -+ return(-1); -+ } -+ -+ length = ((status & RD_FL) >> 16); /* with 4-byte CRC value */ -+ -+ if (status & RD_ES) { -+ printf("ETH RX error 0x%x\n", status); -+ } -+ else { -+ /* Pass the packet up to the protocol layers. */ -+ NetReceive(NetRxPackets[next_rx], length - 4); -+ } -+ -+ /* Clear done bits */ -+ jz_writel(ETH_SR, DMA_RX_DEFAULT); -+ -+ desc->status = R_OWN; -+ -+ jz_flush_dcache(); -+ jz_sync(); -+ -+ next_rx++; -+ if (next_rx >= NUM_RX_DESCS) { -+ next_rx = 0; -+ } -+ } /* for */ -+ -+ return(0); /* Does anyone use this? */ -+} -+ -+static int jz_init(struct eth_device* dev, bd_t * bd) -+{ -+ int i, phyid = -1; -+ -+ /* Reset ethernet unit */ -+ reset_eth(); -+ -+ /* Disable interrupts: we don't use ethernet interrupts */ -+ jz_writel(ETH_IER, 0); -+ -+ for (i=0;i<32;i++) -+ if (search_phy(i)) { -+ phyid = i; -+ break; -+ } -+ -+ if (phyid == -1) -+ printf("Can't locate any PHY\n"); -+ -+ /* Start Auto Negotiation of PHY 0 and check it */ -+ if (autonet_complete(phyid)) -+ printf("ETH Auto-Negotiation failed\n"); -+ -+ /* Configure PHY */ -+ config_phy(phyid); -+ -+ /* Configure MAC */ -+ config_mac(); -+ -+ /* Setup the Rx&Tx descriptors */ -+ for (i = 0; i < NUM_RX_DESCS; i++) { -+ rx_desc[i].status = R_OWN; -+ rx_desc[i].ctrl = PKTSIZE_ALIGN | RD_RCH; -+ rx_desc[i].addr = virt_to_phys(NetRxPackets[i]); -+ rx_desc[i].next = virt_to_phys(rx_desc + i + 1); -+ } -+ rx_desc[NUM_RX_DESCS - 1].next = virt_to_phys(rx_desc); /* The last links to the first */ -+ rx_desc[NUM_RX_DESCS - 1].ctrl |= RD_RER; /* Set the Receive End Of Ring flag */ -+ -+ for (i = 0; i < NUM_TX_DESCS; i++) { -+ tx_desc[i].status = 0; -+ tx_desc[i].ctrl = TD_TCH; -+ tx_desc[i].addr = 0; -+ tx_desc[i].next = virt_to_phys(tx_desc + i + 1); -+ } -+ tx_desc[NUM_TX_DESCS - 1].next = virt_to_phys(tx_desc); /* The last links to the first */ -+ tx_desc[NUM_TX_DESCS - 1].ctrl |= TD_TER; /* Set the Transmit End Of Ring flag */ -+ -+ jz_flush_dcache(); -+ -+ jz_writel(ETH_RAR, virt_to_phys(rx_desc)); -+ jz_writel(ETH_TAR, virt_to_phys(tx_desc)); -+ -+ next_rx = next_tx = 0; -+ -+ /* Enable ETH */ -+ enable_eth(); -+ -+ return (1); -+} -+ -+static void jz_halt(struct eth_device *dev) -+{ -+ disable_eth(); -+} -+ -+int jz_enet_initialize(bd_t *bis) -+{ -+ struct eth_device *dev; -+ -+ dev = (struct eth_device *) malloc(sizeof *dev); -+ memset(dev, 0, sizeof *dev); -+ -+ sprintf(dev->name, "JZ ETHERNET"); -+ dev->iobase = 0; -+ dev->priv = 0; -+ dev->init = jz_init; -+ dev->halt = jz_halt; -+ dev->send = jz_send; -+ dev->recv = jz_recv; -+ -+ eth_register(dev); -+ -+ return 1; -+} -+ -+#endif /* CONFIG_JZ4730 || CONFIG_JZ5730 */ -diff --git a/cpu/mips/jz_eth.h b/cpu/mips/jz_eth.h -new file mode 100644 -index 0000000..8a235eb ---- /dev/null -+++ b/cpu/mips/jz_eth.h -@@ -0,0 +1,267 @@ -+#ifndef __JZ_ETH_H__ -+#define __JZ_ETH_H__ -+ -+#define ETH_BASE 0xB3100000 -+ -+#define ETH_BMR (ETH_BASE + 0x1000) -+#define ETH_TPDR (ETH_BASE + 0x1004) -+#define ETH_RPDR (ETH_BASE + 0x1008) -+#define ETH_RAR (ETH_BASE + 0x100C) -+#define ETH_TAR (ETH_BASE + 0x1010) -+#define ETH_SR (ETH_BASE + 0x1014) -+#define ETH_OMR (ETH_BASE + 0x1018) -+#define ETH_IER (ETH_BASE + 0x101C) -+#define ETH_MFCR (ETH_BASE + 0x1020) -+#define ETH_CTAR (ETH_BASE + 0x1050) -+#define ETH_CRAR (ETH_BASE + 0x1054) -+#define ETH_MCR (ETH_BASE + 0x0000) -+#define ETH_MAHR (ETH_BASE + 0x0004) -+#define ETH_MALR (ETH_BASE + 0x0008) -+#define ETH_HTHR (ETH_BASE + 0x000C) -+#define ETH_HTLR (ETH_BASE + 0x0010) -+#define ETH_MIAR (ETH_BASE + 0x0014) -+#define ETH_MIDR (ETH_BASE + 0x0018) -+#define ETH_FCR (ETH_BASE + 0x001C) -+#define ETH_VTR1 (ETH_BASE + 0x0020) -+#define ETH_VTR2 (ETH_BASE + 0x0024) -+#define ETH_WKFR (ETH_BASE + 0x0028) -+#define ETH_PMTR (ETH_BASE + 0x002C) -+ -+/* Bus Mode Register (DMA_BMR) */ -+#define BMR_PBL 0x00003f00 /* Programmable Burst Length */ -+#define BMR_DSL 0x0000007c /* Descriptor Skip Length */ -+#define BMR_BAR 0x00000002 /* Bus ARbitration */ -+#define BMR_SWR 0x00000001 /* Software Reset */ -+ -+#define DMA_BURST 4 -+ -+/* Status Register (DMA_STS) */ -+#define STS_BE 0x03800000 /* Bus Error Bits */ -+#define STS_TS 0x00700000 /* Transmit Process State */ -+#define STS_RS 0x000e0000 /* Receive Process State */ -+ -+#define TS_STOP 0x00000000 /* Stopped */ -+#define TS_FTD 0x00100000 /* Running Fetch Transmit Descriptor */ -+#define TS_WEOT 0x00200000 /* Running Wait for End Of Transmission */ -+#define TS_QDAT 0x00300000 /* Running Queue skb data into TX FIFO */ -+#define TS_RES 0x00400000 /* Reserved */ -+#define TS_SPKT 0x00500000 /* Reserved */ -+#define TS_SUSP 0x00600000 /* Suspended */ -+#define TS_CLTD 0x00700000 /* Running Close Transmit Descriptor */ -+ -+#define RS_STOP 0x00000000 /* Stopped */ -+#define RS_FRD 0x00020000 /* Running Fetch Rx Descriptor */ -+#define RS_CEOR 0x00040000 /* Running Check for End of Rx Packet */ -+#define RS_WFRP 0x00060000 /* Running Wait for Rx Packet */ -+#define RS_SUSP 0x00080000 /* Suspended */ -+#define RS_CLRD 0x000a0000 /* Running Close Rx Descriptor */ -+#define RS_FLUSH 0x000c0000 /* Running Flush RX FIFO */ -+#define RS_QRFS 0x000e0000 /* Running Queue RX FIFO into RX Skb */ -+ -+/* Operation Mode Register (DMA_OMR) */ -+#define OMR_TTM 0x00400000 /* Transmit Threshold Mode */ -+#define OMR_SF 0x00200000 /* Store and Forward */ -+#define OMR_TR 0x0000c000 /* Threshold Control Bits */ -+#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ -+#define OMR_SR 0x00000002 /* Start/Stop Receive */ -+ -+#define TR_18 0x00000000 /* Threshold set to 18 (32) bytes */ -+#define TR_24 0x00004000 /* Threshold set to 24 (64) bytes */ -+#define TR_32 0x00008000 /* Threshold set to 32 (128) bytes */ -+#define TR_40 0x0000c000 /* Threshold set to 40 (256) bytes */ -+ -+/* Missed Frames Counters (DMA_MFC) */ -+#define MFC_CNT1 0xffff0000 /* Missed Frames Counter Bits by */ -+ /* application */ -+#define MFC_CNT2 0x0000ffff /* Missed Frames Counter Bits by */ -+ /* controller */ -+ -+/* Mac control Register (MAC_MCR) */ -+#define MCR_RA 0x80000000 /* Receive All */ -+#define MCR_HBD 0x10000000 /* HeartBeat Disable */ -+#define MCR_PS 0x08000000 /* Port Select */ -+#define MCR_DRO 0x00800000 /* Receive own Disable */ -+#define MCR_OM 0x00600000 /* Operating(loopback) Mode */ -+#define MCR_FDX 0x00100000 /* Full Duplex Mode */ -+#define MCR_PM 0x00080000 /* Pass All Multicast */ -+#define MCR_PR 0x00040000 /* Promiscuous Mode */ -+#define MCR_IF 0x00020000 /* Inverse Filtering */ -+#define MCR_PB 0x00010000 /* Pass Bad Frames */ -+#define MCR_HO 0x00008000 /* Hash Only Filtering Mode */ -+#define MCR_HP 0x00002000 /* Hash/Perfect Receive Filtering Mode */ -+#define MCR_LCC 0x00001000 /* Late Collision control */ -+#define MCR_DBF 0x00000800 /* Boardcast frame Disable */ -+#define MCR_DTRY 0x00000400 /* Retry Disable */ -+#define MCR_ASTP 0x00000100 /* Automatic pad stripping */ -+#define MCR_BOLMT 0x000000c0 /* Back off Limit */ -+#define MCR_DC 0x00000020 /* Deferral check */ -+#define MCR_TE 0x00000008 /* Transmitter enable */ -+#define MCR_RE 0x00000004 /* Receiver enable */ -+ -+#define MCR_MII_10 ( OMR_TTM | MCR_PS) -+#define MCR_MII_100 ( MCR_HBD | MCR_PS) -+ -+/* Constants for the intr mask and intr status registers. (DMA_SIS and DMA_IER) */ -+#define DMA_INT_NI 0x00010000 /* Normal interrupt summary */ -+#define DMA_INT_AI 0x00008000 /* Abnormal interrupt summary */ -+#define DMA_INT_ER 0x00004000 /* Early receive interrupt */ -+#define DMA_INT_FB 0x00002000 /* Fatal bus error */ -+#define DMA_INT_ET 0x00000400 /* Early transmit interrupt */ -+#define DMA_INT_RW 0x00000200 /* Receive watchdog timeout */ -+#define DMA_INT_RS 0x00000100 /* Receive stop */ -+#define DMA_INT_RU 0x00000080 /* Receive buffer unavailble */ -+#define DMA_INT_RI 0x00000040 /* Receive interrupt */ -+#define DMA_INT_UN 0x00000020 /* Underflow */ -+#define DMA_INT_TJ 0x00000008 /* Transmit jabber timeout */ -+#define DMA_INT_TU 0x00000004 /* Transmit buffer unavailble */ -+#define DMA_INT_TS 0x00000002 /* Transmit stop */ -+#define DMA_INT_TI 0x00000001 /* Transmit interrupt */ -+ -+#define DMA_TX_DEFAULT ( DMA_INT_TI | DMA_INT_TS | DMA_INT_TU | DMA_INT_TJ | DMA_INT_FB ) -+ -+#define DMA_RX_DEFAULT ( DMA_INT_RI | DMA_INT_RS | DMA_INT_RU | DMA_INT_RW | DMA_INT_FB ) -+ -+#define DMA_ENABLE (DMA_INT_NI | DMA_INT_AI) -+ -+ -+/* Receive Descriptor Bit Summary */ -+#define R_OWN 0x80000000 /* Own Bit */ -+#define RD_FF 0x40000000 /* Filtering Fail */ -+#define RD_FL 0x3fff0000 /* Frame Length */ -+#define RD_ES 0x00008000 /* Error Summary */ -+#define RD_DE 0x00004000 /* Descriptor Error */ -+#define RD_LE 0x00001000 /* Length Error */ -+#define RD_RF 0x00000800 /* Runt Frame */ -+#define RD_MF 0x00000400 /* Multicast Frame */ -+#define RD_FS 0x00000200 /* First Descriptor */ -+#define RD_LS 0x00000100 /* Last Descriptor */ -+#define RD_TL 0x00000080 /* Frame Too Long */ -+#define RD_CS 0x00000040 /* Collision Seen */ -+#define RD_FT 0x00000020 /* Frame Type */ -+#define RD_RJ 0x00000010 /* Receive Watchdog timeout */ -+#define RD_RE 0x00000008 /* Report on MII Error */ -+#define RD_DB 0x00000004 /* Dribbling Bit */ -+#define RD_CE 0x00000002 /* CRC Error */ -+ -+#define RD_RER 0x02000000 /* Receive End Of Ring */ -+#define RD_RCH 0x01000000 /* Second Address Chained */ -+#define RD_RBS2 0x003ff800 /* Buffer 2 Size */ -+#define RD_RBS1 0x000007ff /* Buffer 1 Size */ -+ -+/* Transmit Descriptor Bit Summary */ -+#define T_OWN 0x80000000 /* Own Bit */ -+#define TD_ES 0x00008000 /* Frame Aborted (error summary) */ -+#define TD_LO 0x00000800 /* Loss Of Carrier */ -+#define TD_NC 0x00000400 /* No Carrier */ -+#define TD_LC 0x00000200 /* Late Collision */ -+#define TD_EC 0x00000100 /* Excessive Collisions */ -+#define TD_HF 0x00000080 /* Heartbeat Fail */ -+#define TD_CC 0x0000003c /* Collision Counter */ -+#define TD_UF 0x00000002 /* Underflow Error */ -+#define TD_DE 0x00000001 /* Deferred */ -+ -+#define TD_IC 0x80000000 /* Interrupt On Completion */ -+#define TD_LS 0x40000000 /* Last Segment */ -+#define TD_FS 0x20000000 /* First Segment */ -+#define TD_FT1 0x10000000 /* Filtering Type */ -+#define TD_SET 0x08000000 /* Setup Packet */ -+#define TD_AC 0x04000000 /* Add CRC Disable */ -+#define TD_TER 0x02000000 /* Transmit End Of Ring */ -+#define TD_TCH 0x01000000 /* Second Address Chained */ -+#define TD_DPD 0x00800000 /* Disabled Padding */ -+#define TD_FT0 0x00400000 /* Filtering Type */ -+#define TD_TBS2 0x003ff800 /* Buffer 2 Size */ -+#define TD_TBS1 0x000007ff /* Buffer 1 Size */ -+ -+#define PERFECT_F 0x00000000 -+#define HASH_F TD_FT0 -+#define INVERSE_F TD_FT1 -+#define HASH_O_F (TD_FT1 | TD_F0) -+ -+/* ------------------------------------------------------------------------ */ -+/* MII Registers and Definitions */ -+/* ------------------------------------------------------------------------ */ -+#define MII_CR 0x00 /* MII Management Control Register */ -+#define MII_SR 0x01 /* MII Management Status Register */ -+#define MII_ID0 0x02 /* PHY Identifier Register 0 */ -+#define MII_ID1 0x03 /* PHY Identifier Register 1 */ -+#define MII_ANA 0x04 /* Auto Negotiation Advertisement */ -+#define MII_ANLPA 0x05 /* Auto Negotiation Link Partner Ability */ -+#define MII_ANE 0x06 /* Auto Negotiation Expansion */ -+#define MII_ANP 0x07 /* Auto Negotiation Next Page TX */ -+ -+/* MII Management Control Register */ -+#define MII_CR_RST 0x8000 /* RESET the PHY chip */ -+#define MII_CR_LPBK 0x4000 /* Loopback enable */ -+#define MII_CR_SPD 0x2000 /* 0: 10Mb/s; 1: 100Mb/s */ -+#define MII_CR_10 0x0000 /* Set 10Mb/s */ -+#define MII_CR_100 0x2000 /* Set 100Mb/s */ -+#define MII_CR_ASSE 0x1000 /* Auto Speed Select Enable */ -+#define MII_CR_PD 0x0800 /* Power Down */ -+#define MII_CR_ISOL 0x0400 /* Isolate Mode */ -+#define MII_CR_RAN 0x0200 /* Restart Auto Negotiation */ -+#define MII_CR_FDM 0x0100 /* Full Duplex Mode */ -+#define MII_CR_CTE 0x0080 /* Collision Test Enable */ -+ -+/* MII Management Status Register */ -+#define MII_SR_T4C 0x8000 /* 100BASE-T4 capable */ -+#define MII_SR_TXFD 0x4000 /* 100BASE-TX Full Duplex capable */ -+#define MII_SR_TXHD 0x2000 /* 100BASE-TX Half Duplex capable */ -+#define MII_SR_TFD 0x1000 /* 10BASE-T Full Duplex capable */ -+#define MII_SR_THD 0x0800 /* 10BASE-T Half Duplex capable */ -+#define MII_SR_ASSC 0x0020 /* Auto Speed Selection Complete*/ -+#define MII_SR_RFD 0x0010 /* Remote Fault Detected */ -+#define MII_SR_ANC 0x0008 /* Auto Negotiation capable */ -+#define MII_SR_LKS 0x0004 /* Link Status */ -+#define MII_SR_JABD 0x0002 /* Jabber Detect */ -+#define MII_SR_XC 0x0001 /* Extended Capabilities */ -+ -+/* MII Management Auto Negotiation Advertisement Register */ -+#define MII_ANA_TAF 0x03e0 /* Technology Ability Field */ -+#define MII_ANA_T4AM 0x0200 /* T4 Technology Ability Mask */ -+#define MII_ANA_TXAM 0x0180 /* TX Technology Ability Mask */ -+#define MII_ANA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */ -+#define MII_ANA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */ -+#define MII_ANA_100M 0x0380 /* 100Mb Technology Ability Mask */ -+#define MII_ANA_10M 0x0060 /* 10Mb Technology Ability Mask */ -+#define MII_ANA_CSMA 0x0001 /* CSMA-CD Capable */ -+ -+/* MII Management Auto Negotiation Remote End Register */ -+#define MII_ANLPA_NP 0x8000 /* Next Page (Enable) */ -+#define MII_ANLPA_ACK 0x4000 /* Remote Acknowledge */ -+#define MII_ANLPA_RF 0x2000 /* Remote Fault */ -+#define MII_ANLPA_TAF 0x03e0 /* Technology Ability Field */ -+#define MII_ANLPA_T4AM 0x0200 /* T4 Technology Ability Mask */ -+#define MII_ANLPA_TXAM 0x0180 /* TX Technology Ability Mask */ -+#define MII_ANLPA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */ -+#define MII_ANLPA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */ -+#define MII_ANLPA_100M 0x0380 /* 100Mb Technology Ability Mask */ -+#define MII_ANLPA_10M 0x0060 /* 10Mb Technology Ability Mask */ -+#define MII_ANLPA_CSMA 0x0001 /* CSMA-CD Capable */ -+ -+/* Media / mode state machine definitions */ -+/* User selectable: */ -+#define TP 0x0040 /* 10Base-T (now equiv to _10Mb) */ -+#define TP_NW 0x0002 /* 10Base-T with Nway */ -+#define BNC 0x0004 /* Thinwire */ -+#define AUI 0x0008 /* Thickwire */ -+#define BNC_AUI 0x0010 /* BNC/AUI on DC21040 indistinguishable */ -+#define _10Mb 0x0040 /* 10Mb/s Ethernet */ -+#define _100Mb 0x0080 /* 100Mb/s Ethernet */ -+#define AUTO 0x4000 /* Auto sense the media or speed */ -+ -+/* Internal states */ -+#define NC 0x0000 /* No Connection */ -+#define ANS 0x0020 /* Intermediate AutoNegotiation State */ -+#define SPD_DET 0x0100 /* Parallel speed detection */ -+#define INIT 0x0200 /* Initial state */ -+#define EXT_SIA 0x0400 /* External SIA for motherboard chip */ -+#define ANS_SUSPECT 0x0802 /* Suspect the ANS (TP) port is down */ -+#define TP_SUSPECT 0x0803 /* Suspect the TP port is down */ -+#define BNC_AUI_SUSPECT 0x0804 /* Suspect the BNC or AUI port is down */ -+#define EXT_SIA_SUSPECT 0x0805 /* Suspect the EXT SIA port is down */ -+#define BNC_SUSPECT 0x0806 /* Suspect the BNC port is down */ -+#define AUI_SUSPECT 0x0807 /* Suspect the AUI port is down */ -+#define MII 0x1000 /* MII on the 21143 */ -+ -+#endif /* __JZ_ETH_H__ */ diff --git a/cpu/mips/jz_i2c.c b/cpu/mips/jz_i2c.c new file mode 100644 index 0000000..9f3faee @@ -2905,1681 +1420,6 @@ index 0000000..9f3faee +#endif /* CONFIG_JZ4730 || CONFIG_JZ4740 || CONFIG_JZ5730 */ + + -diff --git a/cpu/mips/jz_lcd.c b/cpu/mips/jz_lcd.c -new file mode 100644 -index 0000000..36361ba ---- /dev/null -+++ b/cpu/mips/jz_lcd.c -@@ -0,0 +1,643 @@ -+/* -+ * JzRISC lcd controller -+ * -+ * xiangfu liu -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+/* -+ * Fallowing macro may be used: -+ * CONFIG_LCD : LCD support -+ * LCD_BPP : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 -+ * CONFIG_LCD_LOGO : show logo -+ */ -+ -+#include -+#include -+#include -+ -+#include /* virt_to_phys() */ -+ -+#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD) -+ -+#if defined(CONFIG_JZ4730) -+#include -+#endif -+#if defined(CONFIG_JZ4740) -+#include -+#endif -+#if defined(CONFIG_JZ5730) -+#include -+#endif -+ -+#include "jz_lcd.h" -+ -+ -+struct jzfb_info { -+ unsigned int cfg; /* panel mode and pin usage etc. */ -+ unsigned int w; -+ unsigned int h; -+ unsigned int bpp; /* bit per pixel */ -+ unsigned int fclk; /* frame clk */ -+ unsigned int hsw; /* hsync width, in pclk */ -+ unsigned int vsw; /* vsync width, in line count */ -+ unsigned int elw; /* end of line, in pclk */ -+ unsigned int blw; /* begin of line, in pclk */ -+ unsigned int efw; /* end of frame, in line count */ -+ unsigned int bfw; /* begin of frame, in line count */ -+}; -+ -+static struct jzfb_info jzfb = { -+#if defined(CONFIG_JZLCD_SHARP_LQ035Q7) -+ MODE_TFT_SHARP | PCLK_N | VSYNC_N, -+ 240, 320, 16, 60, 1, 2, 1, 2, 0, 6 -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTS350Q1) -+ MODE_TFT_SAMSUNG | PCLK_N, -+ 240, 320, 16, 60, 1, 2, (254-240), 0, 7, 0 -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTV350QVF04) -+ MODE_TFT_GEN | HSYNC_N | VSYNC_N, -+ 320, 240, 16, 70, 19, 4, 20, 14, 18, 6 -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTP400WQF01) -+ MODE_TFT_GEN | HSYNC_N | VSYNC_N, -+ 480, 272, 16, 60, 41, 10, 2, 2, 2, 2 -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTP400WQF02_18BIT) -+ MODE_TFT_GEN | MODE_TFT_18BIT | HSYNC_N | VSYNC_N, /* MODE_TFT_18BIT: JZ4740@ version */ -+ 480, 272, 32, 60, 41, 10, 2, 2, 2, 2 -+#endif -+#if defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW) -+ MODE_TFT_GEN | HSYNC_N | VSYNC_N | PCLK_N, -+ 320, 240, 16, 85, 30, 3, 38, 20, 11, 8 -+#endif -+#if defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW_SERIAL) -+ MODE_8BIT_SERIAL_TFT | HSYNC_N | VSYNC_N | PCLK_N, -+ /* serial mode 280 lines, parallel mode 240 lines */ -+ 320, 280, 32, 60, (30*3), 3, (20*3), (38*3), 46, 23 -+#endif -+#if defined(CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E) -+ MODE_TFT_GEN | HSYNC_N | VSYNC_N | PCLK_N | DE_N, -+ /* 240, 320, 16, 60, 3, 3, 3, 3, 3, 3 */ /* 240x320 */ -+ 320, 240, 16, 60, 3, 3, 3, 3, 3, 85 /* 320x240 */ -+#endif -+#if defined(CONFIG_JZLCD_HYNIX_HT10X21) -+ MODE_TFT_GEN | PCLK_N, -+ 1024, 768, 16, 45, 1, 1, 75, 0, 3, 0 -+#endif -+#if defined(CONFIG_JZLCD_TOSHIBA_LTM084P363) -+ MODE_TFT_GEN | PCLK_N, -+ 800, ,600, 16, 50, 1, 2, 199, 0, 2, 0 -+#endif -+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) -+ -+ #if defined(CONFIG_PAVO) -+ MODE_TFT_GEN | HSYNC_N | VSYNC_N | MODE_TFT_18BIT | PCLK_N, -+ 320, 240, 18, 110, 1, 1, 10, 50, 10, 13 -+ #elif defined(CONFIG_QI_LB60) -+ MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, -+ 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 -+ #else /* defined(CONFIG_JZLCD_FOXCONN_PT035TN01) && (!defined(CONFIG_PAVO)) */ -+ MODE_TFT_GEN | HSYNC_N | VSYNC_N | PCLK_N, -+ 320, 240, 16, 110, 1, 1, 10, 50, 10, 13 -+ #endif -+ -+#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 */ -+#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL) -+ MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, -+ 320, 240, 32, 60, 1, 1, 10, 50, 10, 13 -+#endif -+#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42) -+ MODE_TFT_SHARP | PCLK_N, -+ 800, 600, 16, 50, 1, 1, 255, 0, 34, 0 -+#endif -+#if defined(CONFIG_JZLCD_CSTN_800x600) -+ MODE_STN_COLOR_DUAL | STN_DAT_PIN8, -+ 800, 600, 16, 30, 8, 1, 0, 0, 0, 0 -+#endif -+#if defined(CONFIG_JZLCD_CSTN_320x240) -+ MODE_STN_COLOR_SINGLE | STN_DAT_PIN8, -+ 320, 240, 16, 120, 8, 1, 8, 0, 0, 0 -+#endif -+#if defined(CONFIG_JZLCD_MSTN_640x480) -+ MODE_STN_MONO_DUAL | STN_DAT_PIN4, -+ 640, 480, 8, 110, 4, 1, 4, 0, 0, 0 -+#endif -+#if defined(CONFIG_JZLCD_MSTN_320x240) -+ MODE_STN_MONO_SINGLE | STN_DAT_PIN4, -+ 320, 240, 8, 110, 4, 1, 4, 0, 0, 0 -+#endif -+#if defined(CONFIG_JZLCD_MSTN_480x320) -+ MODE_STN_MONO_SINGLE | STN_DAT_PIN8 -+#if defined(CONFIG_JZLCD_MSTN_INVERSE) -+ | DATA_INVERSE -+#endif -+ , 480, 320, 8, 65, 8, 1, 8, 0, 0, 0 -+#endif -+#if defined(CONFIG_JZLCD_MSTN_240x128) -+ MODE_STN_MONO_SINGLE | STN_DAT_PIN1 -+#if defined(CONFIG_JZLCD_MSTN_INVERSE) -+ | DATA_INVERSE -+#endif -+ , 240, 128, 8, 100, 1, 1, 1, 0, 0, 0 -+#endif -+}; -+ -+/************************************************************************/ -+ -+vidinfo_t panel_info = { -+#if defined(CONFIG_JZLCD_SHARP_LQ035Q7) -+ 240, 320, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTS350Q1) -+ 240, 320, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTV350QVF04) -+ 320, 240, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTP400WQF01) -+ 480, 272, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_SAMSUNG_LTP400WQF02_18BIT) -+ 480, 272, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW) -+ 320, 240, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW_SERIAL) -+ 320, 280, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E) -+ 320, 240, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) -+ 320, 240, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL) -+ 320, 240, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_HYNIX_HT10X21) -+ 1024, 768, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_TOSHIBA_LTM084P363) -+ 800, 600, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42) -+ 800, 600, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_CSTN_800x600) -+ 800, 600, LCD_BPP, -+#endif -+#if defined(CONFIG_JZLCD_CSTN_320x240) -+ 320, 240, LCD_BPP, -+#endif -+}; -+ -+/*----------------------------------------------------------------------*/ -+ -+int lcd_line_length; -+ -+int lcd_color_fg; -+int lcd_color_bg; -+ -+/* -+ * Frame buffer memory information -+ */ -+void *lcd_base; /* Start of framebuffer memory */ -+void *lcd_console_address; /* Start of console buffer */ -+ -+short console_col; -+short console_row; -+ -+/*----------------------------------------------------------------------*/ -+ -+void lcd_ctrl_init (void *lcdbase); -+ -+void lcd_enable (void); -+void lcd_disable (void); -+ -+/*----------------------------------------------------------------------*/ -+ -+static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); -+static void jz_lcd_desc_init(vidinfo_t *vid); -+static int jz_lcd_hw_init( vidinfo_t *vid ); -+extern int flush_cache_all(void); -+ -+#if LCD_BPP == LCD_COLOR8 -+void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); -+#endif -+#if LCD_BPP == LCD_MONOCHROME -+void lcd_initcolregs (void); -+#endif -+ -+/*-----------------------------------------------------------------------*/ -+ -+void lcd_ctrl_init (void *lcdbase) -+{ -+ __lcd_display_pin_init(); -+ -+ jz_lcd_init_mem(lcdbase, &panel_info); -+ jz_lcd_desc_init(&panel_info); -+ jz_lcd_hw_init(&panel_info); -+ -+ __lcd_display_on() ; -+} -+ -+/*----------------------------------------------------------------------*/ -+#if LCD_BPP == LCD_COLOR8 -+void -+lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -+{ -+} -+#endif -+/*----------------------------------------------------------------------*/ -+ -+#if LCD_BPP == LCD_MONOCHROME -+static -+void lcd_initcolregs (void) -+{ -+} -+#endif -+ -+/* -+ * Before enabled lcd controller, lcd registers should be configured correctly. -+ */ -+ -+void lcd_enable (void) -+{ -+ REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ -+ REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ -+} -+ -+void lcd_disable (void) -+{ -+ REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ -+ /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ -+} -+ -+static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) -+{ -+ u_long palette_mem_size; -+ struct jz_fb_info *fbi = &vid->jz_fb; -+ int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; -+ -+ fbi->screen = (u_long)lcdbase; -+ fbi->palette_size = 256; -+ palette_mem_size = fbi->palette_size * sizeof(u16); -+ -+ debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); -+ /* locate palette and descs at end of page following fb */ -+ fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; -+ -+ return 0; -+} -+ -+static void jz_lcd_desc_init(vidinfo_t *vid) -+{ -+ struct jz_fb_info * fbi; -+ fbi = &vid->jz_fb; -+ fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); -+ fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); -+ fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); -+ -+ #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) -+ -+ /* populate descriptors */ -+ fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); -+ fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); -+ fbi->dmadesc_fblow->fidr = 0; -+ fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; -+ -+ fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ -+ -+ fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); -+ fbi->dmadesc_fbhigh->fidr = 0; -+ fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ -+ -+ fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); -+ fbi->dmadesc_palette->fidr = 0; -+ fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); -+ -+ if( NBITS(vid->vl_bpix) < 12) -+ { -+ /* assume any mode with <12 bpp is palette driven */ -+ fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); -+ fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); -+ /* flips back and forth between pal and fbhigh */ -+ fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); -+ } else { -+ /* palette shouldn't be loaded in true-color mode */ -+ fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); -+ fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ -+ } -+ -+ flush_cache_all(); -+} -+ -+static int jz_lcd_hw_init(vidinfo_t *vid) -+{ -+ struct jz_fb_info *fbi = &vid->jz_fb; -+ unsigned int val = 0; -+ unsigned int pclk; -+ unsigned int stnH; -+#if defined(CONFIG_MIPS_JZ4740) -+ int pll_div; -+#endif -+ -+ /* Setting Control register */ -+ switch (jzfb.bpp) { -+ case 1: -+ val |= LCD_CTRL_BPP_1; -+ break; -+ case 2: -+ val |= LCD_CTRL_BPP_2; -+ break; -+ case 4: -+ val |= LCD_CTRL_BPP_4; -+ break; -+ case 8: -+ val |= LCD_CTRL_BPP_8; -+ break; -+ case 15: -+ val |= LCD_CTRL_RGB555; -+ case 16: -+ val |= LCD_CTRL_BPP_16; -+ break; -+#if defined(CONFIG_MIPS_JZ4740) -+ case 17 ... 32: -+ val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ -+ break; -+#endif -+ default: -+ printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); -+ val |= LCD_CTRL_BPP_16; -+ break; -+ } -+ -+ switch (jzfb.cfg & MODE_MASK) { -+ case MODE_STN_MONO_DUAL: -+ case MODE_STN_COLOR_DUAL: -+ case MODE_STN_MONO_SINGLE: -+ case MODE_STN_COLOR_SINGLE: -+ switch (jzfb.bpp) { -+ case 1: -+ /* val |= LCD_CTRL_PEDN; */ -+ case 2: -+ val |= LCD_CTRL_FRC_2; -+ break; -+ case 4: -+ val |= LCD_CTRL_FRC_4; -+ break; -+ case 8: -+ default: -+ val |= LCD_CTRL_FRC_16; -+ break; -+ } -+ break; -+ } -+ -+ val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ -+ val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ -+ -+ switch (jzfb.cfg & MODE_MASK) { -+ case MODE_STN_MONO_DUAL: -+ case MODE_STN_COLOR_DUAL: -+ case MODE_STN_MONO_SINGLE: -+ case MODE_STN_COLOR_SINGLE: -+ switch (jzfb.cfg & STN_DAT_PINMASK) { -+#define align2(n) (n)=((((n)+1)>>1)<<1) -+#define align4(n) (n)=((((n)+3)>>2)<<2) -+#define align8(n) (n)=((((n)+7)>>3)<<3) -+ case STN_DAT_PIN1: -+ /* Do not adjust the hori-param value. */ -+ break; -+ case STN_DAT_PIN2: -+ align2(jzfb.hsw); -+ align2(jzfb.elw); -+ align2(jzfb.blw); -+ break; -+ case STN_DAT_PIN4: -+ align4(jzfb.hsw); -+ align4(jzfb.elw); -+ align4(jzfb.blw); -+ break; -+ case STN_DAT_PIN8: -+ align8(jzfb.hsw); -+ align8(jzfb.elw); -+ align8(jzfb.blw); -+ break; -+ } -+ break; -+ } -+ -+ REG_LCD_CTRL = val; -+ -+ switch (jzfb.cfg & MODE_MASK) { -+ case MODE_STN_MONO_DUAL: -+ case MODE_STN_COLOR_DUAL: -+ case MODE_STN_MONO_SINGLE: -+ case MODE_STN_COLOR_SINGLE: -+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || -+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) -+ stnH = jzfb.h >> 1; -+ else -+ stnH = jzfb.h; -+ -+ REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; -+ REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); -+ -+ /* Screen setting */ -+ REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); -+ REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); -+ REG_LCD_DAV = (0 << 16) | (stnH); -+ -+ /* AC BIAs signal */ -+ REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); -+ -+ break; -+ -+ case MODE_TFT_GEN: -+ case MODE_TFT_SHARP: -+ case MODE_TFT_CASIO: -+ case MODE_TFT_SAMSUNG: -+ case MODE_8BIT_SERIAL_TFT: -+ case MODE_TFT_18BIT: -+ REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; -+ REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; -+#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42) -+ REG_LCD_DAV = (0 << 16) | ( jzfb.h ); -+#else -+ REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); -+#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/ -+ REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); -+ REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ -+ | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); -+ break; -+ } -+ -+ switch (jzfb.cfg & MODE_MASK) { -+ case MODE_TFT_SAMSUNG: -+ { -+ unsigned int total, tp_s, tp_e, ckv_s, ckv_e; -+ unsigned int rev_s, rev_e, inv_s, inv_e; -+ -+ pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * -+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ -+ -+ total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; -+ tp_s = jzfb.blw + jzfb.w + 1; -+ tp_e = tp_s + 1; -+ /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ -+ ckv_s = tp_s - pclk/(1000000000/4100); -+ ckv_e = tp_s + total; -+ rev_s = tp_s - 11; /* -11.5 clk */ -+ rev_e = rev_s + total; -+ inv_s = tp_s; -+ inv_e = inv_s + total; -+ REG_LCD_CLS = (tp_s << 16) | tp_e; -+ REG_LCD_PS = (ckv_s << 16) | ckv_e; -+ REG_LCD_SPL = (rev_s << 16) | rev_e; -+ REG_LCD_REV = (inv_s << 16) | inv_e; -+ jzfb.cfg |= STFT_REVHI | STFT_SPLHI; -+ break; -+ } -+ case MODE_TFT_SHARP: -+ { -+ unsigned int total, cls_s, cls_e, ps_s, ps_e; -+ unsigned int spl_s, spl_e, rev_s, rev_e; -+ total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; -+#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42) -+ spl_s = 1; -+ spl_e = spl_s + 1; -+ cls_s = 0; -+ cls_e = total - 60; /* > 4us (pclk = 80ns) */ -+ ps_s = cls_s; -+ ps_e = cls_e; -+ rev_s = total - 40; /* > 3us (pclk = 80ns) */ -+ rev_e = rev_s + total; -+ jzfb.cfg |= STFT_PSHI; -+#else /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/ -+ spl_s = total - 5; /* LD */ -+ spl_e = total -3; -+ cls_s = 32; /* CKV */ -+ cls_e = 145; -+ ps_s = 0; /* OEV */ -+ ps_e = 45; -+ rev_s = 0; /* POL */ -+ rev_e = 0; -+#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/ -+ REG_LCD_SPL = (spl_s << 16) | spl_e; -+ REG_LCD_CLS = (cls_s << 16) | cls_e; -+ REG_LCD_PS = (ps_s << 16) | ps_e; -+ REG_LCD_REV = (rev_s << 16) | rev_e; -+ break; -+ } -+ case MODE_TFT_CASIO: -+ break; -+ } -+ -+ /* Configure the LCD panel */ -+ REG_LCD_CFG = jzfb.cfg; -+ -+ /* Timing setting */ -+ __cpm_stop_lcd(); -+ -+ val = jzfb.fclk; /* frame clk */ -+ if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { -+ pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * -+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ -+ } -+ else { -+ /* serial mode: Hsync period = 3*Width_Pixel */ -+ pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * -+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ -+ } -+ -+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || -+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) -+ pclk = (pclk * 3); -+ -+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || -+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || -+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || -+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) -+ pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); -+ -+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || -+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) -+ pclk >>= 1; -+ -+#if defined(CONFIG_MIPS_JZ4730) -+ val = __cpm_get_pllout() / pclk; -+ REG_CPM_CFCR2 = val - 1; -+ val = pclk * 4 ; -+ if ( val > 150000000 ) { -+ printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); -+ printf("Change LCDClock to 150MHz\n"); -+ val = 150000000; -+ } -+ val = __cpm_get_pllout() / val; -+ val--; -+ if ( val > 0xF ) -+ val = 0xF; -+ __cpm_set_lcdclk_div(val); -+ REG_CPM_CFCR |= CPM_CFCR_UPE; -+ -+#elif defined(CONFIG_MIPS_JZ4740) -+ pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ -+ pll_div = pll_div ? 1 : 2 ; -+ val = ( __cpm_get_pllout()/pll_div ) / pclk; -+ val--; -+ if ( val > 0x1ff ) { -+ printf("CPM_LPCDR too large, set it to 0x1ff\n"); -+ val = 0x1ff; -+ } -+ __cpm_set_pixdiv(val); -+ -+ val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ -+ if ( val > 150000000 ) { -+ printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); -+ printf("Change LCDClock to 150MHz\n"); -+ val = 150000000; -+ } -+ val = ( __cpm_get_pllout()/pll_div ) / val; -+ val--; -+ if ( val > 0x1f ) { -+ printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); -+ val = 0x1f; -+ } -+ __cpm_set_ldiv( val ); -+ REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ -+ -+#else -+#error "cpu/mips/jz_lcd.c, CONFIG_MIPS_JZ4730, please set chip type." -+#endif /*#ifdef CONFIG_MIPS_JZ4730 */ -+ -+ __cpm_start_lcd(); -+ udelay(1000); -+ -+ REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ -+ -+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || -+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) -+ REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ -+ -+ return 0; -+} -+ -+#endif /* CONFIG_LCD */ -diff --git a/cpu/mips/jz_lcd.h b/cpu/mips/jz_lcd.h -new file mode 100644 -index 0000000..d2e7cc4 ---- /dev/null -+++ b/cpu/mips/jz_lcd.h -@@ -0,0 +1,1020 @@ -+/* -+ * JzRISC lcd controller -+ * -+ * xiangfu liu -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#ifndef __JZLCD_H__ -+#define __JZLCD_H__ -+ -+#include -+/* -+ * change u-boot macro to celinux macro -+ */ -+/* Chip type */ -+#if defined(CONFIG_JZ4730) -+#define CONFIG_MIPS_JZ4730 1 -+#endif -+#if defined(CONFIG_JZ4740) -+#define CONFIG_MIPS_JZ4740 1 -+#endif -+#if defined(CONFIG_JZ5730) -+#define CONFIG_MIPS_JZ5730 1 -+#endif -+ -+/* board type */ -+#if defined(CONFIG_LIBRA) -+#define CONFIG_MIPS_JZ4730_LIBRA 1 -+#endif -+#if defined(CONFIG_PMPV1) -+#define CONFIG_MIPS_JZ4730_PMPV1 1 -+#endif -+#if defined(CONFIG_PMPV2) -+#define CONFIG_MIPS_JZ4730_PMPV2 1 -+#endif -+#if defined(CONFIG_GPS) -+#define CONFIG_MIPS_JZ4730_GPS 1 -+#endif -+#if defined(CONFIG_FPRINT) -+#define CONFIG_MIPS_JZ4730_FPRINT 1 -+#endif -+#if defined(CONFIG_LEO) -+#define CONFIG_MIPS_JZ4740_LEO 1 -+#endif -+#if defined(CONFIG_PAVO) -+#define CONFIG_MIPS_JZ4740_PAVO 1 -+#endif -+#if defined(CONFIG_QI_LB60) -+#define CONFIG_MIPS_JZ4740_PI 1 -+#endif -+#if defined(CONFIG_VIRGO) -+#define CONFIG_MIPS_JZ4740_VIRGO 1 -+#endif -+ -+#define mdelay(n) udelay((n)*1000) -+ -+/* -+ * change u-boot macro to celinux macro -+ */ -+ -+#define NR_PALETTE 256 -+ -+struct lcd_desc{ -+ unsigned int next_desc; /* LCDDAx */ -+ unsigned int databuf; /* LCDSAx */ -+ unsigned int frame_id; /* LCDFIDx */ -+ unsigned int cmd; /* LCDCMDx */ -+}; -+ -+#define MODE_MASK 0x0f -+#define MODE_TFT_GEN 0x00 -+#define MODE_TFT_SHARP 0x01 -+#define MODE_TFT_CASIO 0x02 -+#define MODE_TFT_SAMSUNG 0x03 -+#define MODE_CCIR656_NONINT 0x04 -+#define MODE_CCIR656_INT 0x05 -+#define MODE_STN_COLOR_SINGLE 0x08 -+#define MODE_STN_MONO_SINGLE 0x09 -+#define MODE_STN_COLOR_DUAL 0x0a -+#define MODE_STN_MONO_DUAL 0x0b -+#define MODE_8BIT_SERIAL_TFT 0x0c -+ -+#define MODE_TFT_18BIT (1<<7) -+ -+#define STN_DAT_PIN1 (0x00 << 4) -+#define STN_DAT_PIN2 (0x01 << 4) -+#define STN_DAT_PIN4 (0x02 << 4) -+#define STN_DAT_PIN8 (0x03 << 4) -+#define STN_DAT_PINMASK STN_DAT_PIN8 -+ -+#define STFT_PSHI (1 << 15) -+#define STFT_CLSHI (1 << 14) -+#define STFT_SPLHI (1 << 13) -+#define STFT_REVHI (1 << 12) -+ -+#define SYNC_MASTER (0 << 16) -+#define SYNC_SLAVE (1 << 16) -+ -+#define DE_P (0 << 9) -+#define DE_N (1 << 9) -+ -+#define PCLK_P (0 << 10) -+#define PCLK_N (1 << 10) -+ -+#define HSYNC_P (0 << 11) -+#define HSYNC_N (1 << 11) -+ -+#define VSYNC_P (0 << 8) -+#define VSYNC_N (1 << 8) -+ -+#define DATA_NORMAL (0 << 17) -+#define DATA_INVERSE (1 << 17) -+ -+ -+/* Jz LCDFB supported I/O controls. */ -+#define FBIOSETBACKLIGHT 0x4688 -+#define FBIODISPON 0x4689 -+#define FBIODISPOFF 0x468a -+#define FBIORESET 0x468b -+#define FBIOPRINT_REG 0x468c -+ -+/* -+ * LCD panel specific definition -+ */ -+ -+#if defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW) || defined(CONFIG_JZLCD_TRULY_TFTG320240DTSW_SERIAL) -+ -+#if defined(CONFIG_MIPS_JZ4730_PMPV1) -+#define LCD_RESET_PIN 63 -+#elif defined(CONFIG_MIPS_JZ4730_PMPV2) -+#define LCD_RESET_PIN 60 -+#elif defined(CONFIG_MIPS_JZ4740_LEO) -+#define LCD_RESET_PIN 50 -+#endif -+ -+#define __lcd_special_on() \ -+do { \ -+ __gpio_set_pin(LCD_RESET_PIN); \ -+ __gpio_as_output(LCD_RESET_PIN); \ -+ __gpio_clear_pin(LCD_RESET_PIN); \ -+ udelay(100); \ -+ __gpio_set_pin(LCD_RESET_PIN); \ -+} while (0) -+ -+#endif /* CONFIG_JZLCD_TRULY_TFTG320240DTSW, parellel or serial RGB mode */ -+ -+#if defined(CONFIG_JZLCD_SAMSUNG_LTV350QVF04) -+ -+#if defined(CONFIG_MIPS_JZ4730_FPRINT) -+#define PortSDI 60 -+#define PortSCL 61 -+#define PortCS 62 -+#define PortRST 63 -+#define PortSht 64 -+#endif -+ -+#if defined(CONFIG_MIPS_JZ4730_GPS) -+#define PortSDI 74 -+#define PortSCL 72 -+#define PortCS 73 -+#define PortRST 60 -+#define PortSht 59 -+#endif -+ -+#ifndef PortSDI -+#define PortSDI 0 -+#endif -+#ifndef PortSCL -+#define PortSCL 0 -+#endif -+#ifndef PortCS -+#define PortCS 0 -+#endif -+#ifndef PortRST -+#define PortRST 0 -+#endif -+#ifndef PortSht -+#define PortSht 0 -+#endif -+ -+#define __lcd_special_pin_init() \ -+do { \ -+ __gpio_as_output(PortSDI); /* SDI */\ -+ __gpio_as_output(PortSCL); /* SCL */ \ -+ __gpio_as_output(PortCS); /* CS */ \ -+ __gpio_as_output(PortRST); /* Reset */ \ -+ __gpio_as_output(PortSht); /* Shut Down # */ \ -+ __gpio_set_pin(PortCS); \ -+ __gpio_set_pin(PortSCL); \ -+ __gpio_set_pin(PortSDI); \ -+} while (0) -+ -+#define __spi_out(val) \ -+do { \ -+ int __i__; \ -+ unsigned int _t_ = (val); \ -+ __gpio_clear_pin(PortCS); \ -+ udelay(25); \ -+ for (__i__ = 0; __i__ < 24; __i__++ ) { \ -+ __gpio_clear_pin(PortSCL); \ -+ if (_t_ & 0x800000) \ -+ __gpio_set_pin(PortSDI); \ -+ else \ -+ __gpio_clear_pin(PortSDI); \ -+ _t_ <<= 1; \ -+ udelay(25); \ -+ __gpio_set_pin(PortSCL); \ -+ udelay(25); \ -+ } \ -+ __gpio_set_pin(PortCS); \ -+ udelay(25); \ -+ __gpio_set_pin(PortSDI); \ -+ udelay(25); \ -+ __gpio_set_pin(PortSCL); \ -+} while (0) -+ -+#define __spi_id_op_data(rs, rw, val) \ -+ __spi_out((0x1d<<18)|((rs)<<17)|((rw)<<16)|(val)) -+ -+#define __spi_write_reg(reg, val) \ -+do { \ -+ __spi_id_op_data(0, 0, (reg)); \ -+ __spi_id_op_data(1, 0, (val)); \ -+} while (0) -+ -+#define __lcd_special_on() \ -+do { \ -+ __gpio_set_pin(PortSht); \ -+ __gpio_clear_pin(PortRST); \ -+ mdelay(10); \ -+ __gpio_set_pin(PortRST); \ -+ mdelay(1); \ -+ __spi_write_reg(0x09, 0); \ -+ mdelay(10); \ -+ __spi_write_reg(0x09, 0x4000); \ -+ __spi_write_reg(0x0a, 0x2000); \ -+ mdelay(40); \ -+ __spi_write_reg(0x09, 0x4055); \ -+ mdelay(50); \ -+ __spi_write_reg(0x01, 0x409d); \ -+ __spi_write_reg(0x02, 0x0204); \ -+ __spi_write_reg(0x03, 0x0100); \ -+ __spi_write_reg(0x04, 0x3000); \ -+ __spi_write_reg(0x05, 0x4003); \ -+ __spi_write_reg(0x06, 0x000a); \ -+ __spi_write_reg(0x07, 0x0021); \ -+ __spi_write_reg(0x08, 0x0c00); \ -+ __spi_write_reg(0x10, 0x0103); \ -+ __spi_write_reg(0x11, 0x0301); \ -+ __spi_write_reg(0x12, 0x1f0f); \ -+ __spi_write_reg(0x13, 0x1f0f); \ -+ __spi_write_reg(0x14, 0x0707); \ -+ __spi_write_reg(0x15, 0x0307); \ -+ __spi_write_reg(0x16, 0x0707); \ -+ __spi_write_reg(0x17, 0x0000); \ -+ __spi_write_reg(0x18, 0x0004); \ -+ __spi_write_reg(0x19, 0x0000); \ -+ mdelay(60); \ -+ __spi_write_reg(0x09, 0x4a55); \ -+ __spi_write_reg(0x05, 0x5003); \ -+} while (0) -+ -+#define __lcd_special_off() \ -+do { \ -+ __spi_write_reg(0x09, 0x4055); \ -+ __spi_write_reg(0x05, 0x4003); \ -+ __spi_write_reg(0x0a, 0x0000); \ -+ mdelay(10); \ -+ __spi_write_reg(0x09, 0x4000); \ -+ __gpio_clear_pin(PortSht); \ -+} while (0) -+ -+#endif /* CONFIG_JZLCD_SAMSUNG_LTV350QVF04 */ -+ -+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL) -+ -+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */ -+#define MODE 0xcd /* 24bit parellel RGB */ -+#endif -+#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL) -+#define MODE 0xc9 /* 8bit serial RGB */ -+#endif -+ -+#if defined(CONFIG_MIPS_JZ4730_PMPV1) || defined(CONFIG_MIPS_JZ4730_PMPV2) -+ #define SPEN 60 /*LCD_SPL */ -+ #define SPCK 61 /*LCD_CLS */ -+ #define SPDA 62 /*LCD_PS */ -+ #define LCD_RET 63 /*LCD_REV */ /*use for lcd reset */ -+#elif defined(CONFIG_MIPS_JZ4740_LEO) /* board leo */ -+ #define SPEN (32*1+18) /*LCD_SPL */ -+ #define SPCK (32*1+17) /*LCD_CLS */ -+ #define SPDA (32*2+22) /*LCD_PS */ -+ #define LCD_RET (32*2+23) /*LCD_REV */ /* use for lcd reset */ -+#elif defined(CONFIG_MIPS_JZ4740_PAVO) /* board pavo */ -+ #define SPEN (32*1+18) /*LCD_SPL */ -+ #define SPCK (32*1+17) /*LCD_CLS */ -+ #define SPDA (32*2+12) /*LCD_D12 */ -+ #define LCD_RET (32*2+23) /*LCD_REV, GPC23 */ -+#elif defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */ -+ #define SPEN (32*2+21) /*LCD_SPL */ -+ #define SPCK (32*2+23) /*LCD_CLS */ -+ #define SPDA (32*2+22) /*LCD_D12 */ -+ #define LCD_RET (32*3+27) -+#else -+#error "cpu/misp/Jzlcd.h, please define SPI pins on your board." -+#endif -+ -+ #define __spi_write_reg1(reg, val) \ -+ do { \ -+ unsigned char no;\ -+ unsigned short value;\ -+ unsigned char a=0;\ -+ unsigned char b=0;\ -+ a=reg;\ -+ b=val;\ -+ __gpio_set_pin(SPEN);\ -+ __gpio_set_pin(SPCK);\ -+ __gpio_clear_pin(SPDA);\ -+ __gpio_clear_pin(SPEN);\ -+ udelay(25);\ -+ value=((a<<8)|(b&0xFF));\ -+ for(no=0;no<16;no++)\ -+ {\ -+ __gpio_clear_pin(SPCK);\ -+ if((value&0x8000)==0x8000)\ -+ __gpio_set_pin(SPDA);\ -+ else\ -+ __gpio_clear_pin(SPDA);\ -+ udelay(25);\ -+ __gpio_set_pin(SPCK);\ -+ value=(value<<1); \ -+ udelay(25);\ -+ }\ -+ __gpio_set_pin(SPEN);\ -+ udelay(100);\ -+ } while (0) -+ -+ #define __spi_write_reg(reg, val) \ -+ do {\ -+ __spi_write_reg1((reg<<2|2), val);\ -+ udelay(100); \ -+ }while(0) -+ -+ -+ #define __lcd_special_pin_init() \ -+ do { \ -+ __gpio_as_output(SPEN); /* use SPDA */\ -+ __gpio_as_output(SPCK); /* use SPCK */\ -+ __gpio_as_output(SPDA); /* use SPDA */\ -+ __gpio_as_output(LCD_RET);\ -+ } while (0) -+ -+#if defined(CONFIG_QI_LB60) -+ #define __lcd_special_on() \ -+ do { \ -+ udelay(50);\ -+ __spi_write_reg1(0x05, 0x16); \ -+ __spi_write_reg1(0x04, 0x0b); \ -+ __spi_write_reg1(0x07, 0x8d); \ -+ __spi_write_reg1(0x01, 0x95); \ -+ __spi_write_reg1(0x08, 0xc0); \ -+ __spi_write_reg1(0x03, 0x40); \ -+ __spi_write_reg1(0x06, 0x15); \ -+ __spi_write_reg1(0x05, 0xd7); \ -+ } while (0) /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */ -+ -+ #define __lcd_special_off() \ -+ do { \ -+ __spi_write_reg1(0x05, 0x5e); \ -+ } while (0) -+#else -+ #define __lcd_special_on() \ -+ do { \ -+ udelay(50);\ -+ __gpio_clear_pin(LCD_RET);\ -+ mdelay(150);\ -+ __gpio_set_pin(LCD_RET);\ -+ mdelay(10);\ -+ __spi_write_reg(0x00, 0x03); \ -+ __spi_write_reg(0x01, 0x40); \ -+ __spi_write_reg(0x02, 0x11); \ -+ __spi_write_reg(0x03, MODE); /* mode */ \ -+ __spi_write_reg(0x04, 0x32); \ -+ __spi_write_reg(0x05, 0x0e); \ -+ __spi_write_reg(0x07, 0x03); \ -+ __spi_write_reg(0x08, 0x08); \ -+ __spi_write_reg(0x09, 0x40); \ -+ __spi_write_reg(0x0A, 0x88); \ -+ __spi_write_reg(0x0B, 0x88); \ -+ __spi_write_reg(0x0C, 0x20); \ -+ __spi_write_reg(0x0D, 0x20); \ -+ } while (0) /*reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */ -+ -+ #define __lcd_special_off() \ -+ do { \ -+ __spi_write_reg(0x00, 0x03); \ -+ } while (0) -+ -+#endif /* CONFIG_QI_LB60 */ -+#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */ -+ -+#if defined(CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E) -+ -+#if defined(CONFIG_MIPS_JZ4730_FPRINT) -+ #define PortSDI 60 -+ #define PortSCL 65 /* GPIO65 as WR/SCL */ -+ #define PortCS 62 -+ #define PortRST 63 -+ #define PortSDO 64 -+ #define PortSCL1 61 -+#else -+ #error "driver/video/Jzlcd.h, please define pins on your board." -+#endif -+ -+#define __spi_out(val) \ -+do { \ -+ int __i__; \ -+ unsigned int _t_ = (val); \ -+ __gpio_clear_pin(PortCS); \ -+ udelay(2); \ -+ for (__i__ = 0; __i__ < 24; __i__++ ) { \ -+ __gpio_clear_pin(PortSCL); \ -+ if (_t_ & 0x800000) \ -+ __gpio_set_pin(PortSDI); \ -+ else \ -+ __gpio_clear_pin(PortSDI); \ -+ _t_ <<= 1; \ -+ udelay(1); \ -+ __gpio_set_pin(PortSCL); \ -+ udelay(1); \ -+ } \ -+ udelay(2); \ -+ __gpio_set_pin(PortCS); \ -+ __gpio_set_pin(PortSDI); \ -+ __gpio_set_pin(PortSCL); \ -+} while (0) -+ -+#define __spi_id_op_data(rs, rw, val) \ -+ __spi_out((0x0e<<19)|(0<<18)|((rs)<<17)|((rw)<<16)|(val)) /* 0e: 01110. ID:? */ -+ -+#define __spi_write_reg(reg, val) \ -+do { \ -+ __spi_id_op_data(0, 0, (reg)); \ -+ __spi_id_op_data(1, 0, (val)); \ -+} while (0) -+ -+#define get_data(n) (__gpio_get_pin((n)) ? 1:0) /* 1: high level, 0: low level */ -+ -+static inline unsigned int __spi_in(void) -+{ -+ int __i__; -+ unsigned int read_val = 0; -+ unsigned int _t_ = (0x0e<<19)|(0<<18)|((1)<<17)|((1)<<16);/* 0e: 01110. ID:? */ -+ -+ __gpio_clear_pin(PortCS); -+ udelay(2); -+ for (__i__ = 0; __i__ < 32; __i__++ ) { -+ __gpio_clear_pin(PortSCL); -+ if (_t_ & 0x800000) /* send data */ -+ __gpio_set_pin(PortSDI); -+ else -+ __gpio_clear_pin(PortSDI); -+ _t_ <<= 1; -+ udelay(1); -+ __gpio_set_pin(PortSCL); -+ read_val <<= 1; -+ read_val |= get_data(PortSDO); /* receive data */ -+ udelay(1); -+ } -+ udelay(2); -+ __gpio_set_pin(PortCS); -+ __gpio_set_pin(PortSDI); -+ __gpio_set_pin(PortSCL); -+ -+ return read_val; -+ } -+static inline unsigned int __spi_read_reg(int reg) -+{ -+ unsigned int read_val; -+ __spi_id_op_data(0, 0, (reg)); -+ udelay(40); -+ read_val = __spi_in(); -+ return read_val; -+} -+ -+#define WMLCDCOM(val) __spi_id_op_data(0,0,val) -+#define WMLCDDATA(val) __spi_id_op_data(1,0,val) -+#define Delayms(n) mdelay(n) -+ -+static inline void mlcd_mode_setting(void) -+{ -+ /* RGB Interface */ -+ WMLCDCOM(0x0001);WMLCDDATA(0x0000); /* Horizontal reverse */ -+ WMLCDCOM(0x0002);WMLCDDATA(0x0700); -+ /* Entry Mode */ -+ /*WMLCDCOM(0x0003);WMLCDDATA(0x1230);*/ /* default 240x320, HWM=1 write data in high speed */ -+ WMLCDCOM(0x0003);WMLCDDATA(0x1038); /* Rotate to 320x240, HWM=0, low speed */ -+ WMLCDCOM(0x000C);WMLCDDATA(0x0111); /* External interface, as 16bit RGB interface */ -+ WMLCDCOM(0x0020);WMLCDDATA(0x0000); /* Horizontal base */ -+ WMLCDCOM(0x0021);WMLCDDATA(0x0000); /* Vertical base */ -+ WMLCDCOM(0x0030);WMLCDDATA(0x0707); -+ WMLCDCOM(0x0031);WMLCDDATA(0x0407); -+ WMLCDCOM(0x0032);WMLCDDATA(0x0203); -+ WMLCDCOM(0x0033);WMLCDDATA(0x0303); -+ WMLCDCOM(0x0034);WMLCDDATA(0x0303); -+ WMLCDCOM(0x0035);WMLCDDATA(0x0202); -+ WMLCDCOM(0x0036);WMLCDDATA(0x001F); -+ WMLCDCOM(0x0037);WMLCDDATA(0x0707); -+ WMLCDCOM(0x0038);WMLCDDATA(0x0407); -+ WMLCDCOM(0x0039);WMLCDDATA(0x0203); -+ WMLCDCOM(0x003A);WMLCDDATA(0x0303); -+ WMLCDCOM(0x003B);WMLCDDATA(0x0303); -+ WMLCDCOM(0x003C);WMLCDDATA(0x0202); -+ WMLCDCOM(0x003D);WMLCDDATA(0x001F); -+ WMLCDCOM(0x0050);WMLCDDATA(0x0000); /* X start: 0 */ -+ WMLCDCOM(0x0051);WMLCDDATA(0x00EF); /* X end: 239 */ -+ WMLCDCOM(0x0052);WMLCDDATA(0x0000); /* Y start: 0 */ -+ WMLCDCOM(0x0053);WMLCDDATA(0x013F); /* Y end: 319 */ -+ WMLCDCOM(0x0060);WMLCDDATA(0x2700); -+ WMLCDCOM(0x0061);WMLCDDATA(0x0001); -+ WMLCDCOM(0x006A);WMLCDDATA(0x0000); /* VL: Vertical Scroll */ -+ WMLCDCOM(0x0090);WMLCDDATA(0x0016); -+ WMLCDCOM(0x0092);WMLCDDATA(0x0000); -+ WMLCDCOM(0x0093);WMLCDDATA(0x0000); -+} -+ -+static inline void mlcd_power_on(void) -+{ -+ /* Power supply on */ -+ WMLCDCOM(0x0007);WMLCDDATA(0x0001); -+ WMLCDCOM(0x0017);WMLCDDATA(0x0001); -+ Delayms(50); -+ WMLCDCOM(0x0010);WMLCDDATA(0x17B0); -+ WMLCDCOM(0x0011);WMLCDDATA(0x0007); -+ WMLCDCOM(0x0012);WMLCDDATA(0x011A); -+ WMLCDCOM(0x0013);WMLCDDATA(0x0F00); -+ WMLCDCOM(0x0029);WMLCDDATA(0x0010); -+ WMLCDCOM(0x0012);WMLCDDATA(0x013A); -+ Delayms(50); -+} -+ -+static inline void mlcd_power_off(void) -+{ -+ WMLCDCOM(0x0010);WMLCDDATA(0x0780); -+ WMLCDCOM(0x0011);WMLCDDATA(0x0067); -+ WMLCDCOM(0x0012);WMLCDDATA(0x010A); -+ Delayms(20); -+ WMLCDCOM(0x0010);WMLCDDATA(0x0700); -+} -+ -+static inline void mlcd_display_on(void) -+{ -+ /* Display on sequence */ -+ WMLCDCOM(0x0007);WMLCDDATA(0x0021); -+ Delayms(1); -+ WMLCDCOM(0x0007);WMLCDDATA(0x0061); -+ Delayms(20); -+ WMLCDCOM(0x0007);WMLCDDATA(0x0173); -+ WMLCDCOM(0x0022); /* set Index register R22 */ -+} -+ -+static inline void mlcd_display_off(void) -+{ -+ /* Display off sequence */ -+ WMLCDCOM(0x0007);WMLCDDATA(0x0072); -+ Delayms(20); -+ WMLCDCOM(0x0007);WMLCDDATA(0x0001); -+ Delayms(1); -+ WMLCDCOM(0x0007);WMLCDDATA(0x0000); -+} -+ -+#define __lcd_special_pin_init() \ -+do { \ -+ __gpio_as_input(PortSDO); /* SDO */\ -+ __gpio_as_output(PortSDI); /* SDI */\ -+ __gpio_as_output(PortSCL); /* SCL */ \ -+ __gpio_as_output(PortCS); /* CS */ \ -+ __gpio_as_output(PortRST); /* Reset */ \ -+ __gpio_as_output(PortSCL1); /* SCL1 */ \ -+ __gpio_set_pin(PortCS); \ -+ __gpio_set_pin(PortSCL); \ -+ __gpio_set_pin(PortSDI); \ -+ __gpio_set_pin(PortRST); \ -+ __gpio_set_pin(PortSCL1); \ -+ __gpio_set_pin(PortRST); \ -+} while (0) -+ -+#define __lcd_special_on() \ -+do { \ -+ mdelay(10); \ -+ __gpio_clear_pin(PortRST); /* Reset period > 1ms */ \ -+ mdelay(10); \ -+ __gpio_set_pin(PortRST); \ -+ mdelay(1); \ -+ mlcd_power_on(); \ -+ mlcd_mode_setting();\ -+ mlcd_display_on(); \ -+} while (0) -+ -+#if 0 /* Customer need Power Off? --No need, right now */ -+#define __lcd_special_off() \ -+do { \ -+ mlcd_display_off(); \ -+ mlcd_power_off(); \ -+} while (0) -+#endif /* if 0 */ -+ -+#endif /* CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E */ -+ -+#ifndef __lcd_special_pin_init -+#define __lcd_special_pin_init() -+#endif -+#ifndef __lcd_special_on -+#define __lcd_special_on() -+#endif -+#ifndef __lcd_special_off -+#define __lcd_special_off() -+#endif -+ -+ -+/* -+ * Platform specific definition -+ */ -+ -+#if defined(CONFIG_MIPS_JZ4730_GPS) -+ -+#define __lcd_set_backlight_level(n) \ -+do { \ -+ ; \ -+} while (0) -+ -+#define __lcd_display_pin_init() \ -+do { \ -+ __lcd_special_pin_init(); \ -+ __gpio_as_output(94); /* PWM0 pin */ \ -+ __gpio_as_output(95); /* PWM1 pin */ \ -+} while (0) -+ -+#define __lcd_display_on() \ -+do { \ -+ __lcd_special_on(); \ -+ __gpio_set_pin(94); /* PWM0 pin */ \ -+ __gpio_set_pin(95); /* PWM1 pin */ \ -+ __lcd_set_backlight_level(8); \ -+} while (0) -+ -+#define __lcd_display_off() \ -+do { \ -+ __lcd_special_off(); \ -+} while (0) -+ -+#endif /* CONFIG_MIPS_JZ4730_GPS */ -+ -+#if defined(CONFIG_MIPS_JZ4730_FPRINT) -+ -+#define __lcd_set_backlight_level(n) \ -+do { \ -+ REG_PWM_DUT(0) = n; \ -+ REG_PWM_PER(0) = 7; \ -+ REG_PWM_CTR(0) = 0xc1; \ -+} while (0) -+ -+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) -+ -+#define __lcd_display_pin_init() \ -+do { \ -+ __lcd_special_pin_init();\ -+ __gpio_as_pwm();\ -+ __lcd_set_backlight_level(8);\ -+} while (0) -+ -+#define __lcd_display_on() \ -+do { \ -+ __lcd_set_backlight_level(8); \ -+ __lcd_special_on();\ -+} while (0) -+ -+#define __lcd_display_off() \ -+do { \ -+ __lcd_set_backlight_level(0); \ -+ __lcd_special_off();\ -+} while (0) -+ -+#elif defined(CONFIG_JZLCD_TRULY_TFTG240320UTSW_63W_E) -+/* pwm circle frequece = 1KHz */ -+/* back light level: 0~100 */ -+#undef __lcd_set_backlight_level -+#define __lcd_set_backlight_level(n) \ -+do { \ -+ REG_PWM_DUT(0) = n; \ -+ REG_PWM_PER(0) = 99; \ -+ REG_PWM_CTR(0) = 0xe4; \ -+} while (0) -+ -+#define __lcd_display_pin_init() \ -+do { \ -+ __lcd_special_pin_init();\ -+ __gpio_as_pwm();\ -+ __lcd_set_backlight_level(88);\ -+} while (0) -+ -+#define __lcd_display_on() \ -+do { \ -+ __lcd_set_backlight_level(88); \ -+ __lcd_special_on();\ -+} while (0) -+ -+#define __lcd_display_off() \ -+do { \ -+ __lcd_set_backlight_level(0); \ -+ __lcd_special_off();\ -+} while (0) -+ -+#else -+ -+#define __lcd_display_pin_init() \ -+do { \ -+ __gpio_as_output(GPIO_DISP_OFF_N); \ -+ __gpio_as_pwm(); \ -+ __lcd_set_backlight_level(8); \ -+} while (0) -+ -+#define __lcd_display_on() \ -+do { \ -+ __lcd_set_backlight_level(8); \ -+ __gpio_set_pin(GPIO_DISP_OFF_N); \ -+} while (0) -+ -+#define __lcd_display_off() \ -+do { \ -+ __lcd_set_backlight_level(0); \ -+ __gpio_clear_pin(GPIO_DISP_OFF_N); \ -+} while (0) -+#endif -+ -+#endif /* CONFIG_MIPS_JZ4730_FPRINT */ -+ -+#if defined(CONFIG_MIPS_JZ4730_LIBRA) -+ -+#define __lcd_set_backlight_level(n) \ -+do { \ -+} while (0) -+ -+#define __lcd_display_pin_init() \ -+do { \ -+ __lcd_special_pin_init(); \ -+ __gpio_clear_pin(100); \ -+ __gpio_as_output(100); \ -+ __gpio_as_output(94); \ -+ __gpio_as_output(95); \ -+ __lcd_set_backlight_level(8); \ -+} while (0) -+ -+#define __lcd_display_on() \ -+do { \ -+ __lcd_special_on(); \ -+ __gpio_set_pin(100); \ -+ __gpio_set_pin(94); \ -+ __gpio_set_pin(95); \ -+} while (0) -+ -+#define __lcd_display_off() \ -+do { \ -+ __lcd_special_off(); \ -+ __gpio_clear_pin(100); \ -+ __gpio_clear_pin(94); \ -+ __gpio_clear_pin(95); \ -+} while (0) -+ -+#endif /* CONFIG_MIPS_JZ4730_LIBRA */ -+ -+#if defined(CONFIG_MIPS_JZ4730_PMPV1) || defined(CONFIG_MIPS_JZ4730_PMPV2) -+ -+#define GPIO_PWM0 94 -+ -+#define __lcd_set_backlight_level(n) \ -+do { \ -+ __gpio_as_pwm(); \ -+ REG_PWM_DUT(0) = n; \ -+ REG_PWM_PER(0) = 7; \ -+ REG_PWM_CTR(0) = 0xc1; \ -+} while (0) -+ -+#define __lcd_close_backlight() \ -+do { \ -+__gpio_as_output(GPIO_PWM0);\ -+__gpio_clear_pin(GPIO_PWM0);\ -+} while (0) -+ -+#define __lcd_display_pin_init() \ -+do { \ -+ __gpio_as_output(GPIO_DISP_OFF_N); \ -+ __lcd_set_backlight_level(8); \ -+ __lcd_special_pin_init(); \ -+} while (0) -+ -+#define __lcd_display_on() \ -+do { \ -+ __gpio_set_pin(GPIO_DISP_OFF_N); \ -+ __lcd_special_on(); \ -+ __lcd_set_backlight_level(8); \ -+} while (0) -+ -+#define __lcd_display_off() \ -+do { \ -+ __lcd_special_off(); \ -+ __lcd_close_backlight(); \ -+ __gpio_clear_pin(GPIO_DISP_OFF_N); \ -+} while (0) -+ -+#endif /* CONFIG_MIPS_JZ4730_PMPV1 | CONFIG_MIPS_JZ4730_PMPV1 */ -+ -+ -+#if defined(CONFIG_MIPS_JZ4740_LEO) || defined(CONFIG_MIPS_JZ4740_PAVO)|| defined(CONFIG_MIPS_JZ4740_VIRGO) -+ -+#if defined(CONFIG_MIPS_JZ4740_PAVO) -+#define GPIO_PWM 123 /* GP_D27 */ -+#define PWM_CHN 4 /* pwm channel */ -+#define PWM_FULL 101 -+/* 100 level: 0,1,...,100 */ -+/*#define __lcd_set_backlight_level(n) \ -+do { \ -+ __gpio_as_pwm(4); \ -+ __tcu_disable_pwm_output(PWM_CHN); \ -+ __tcu_stop_counter(PWM_CHN); \ -+ __tcu_init_pwm_output_high(PWM_CHN); \ -+ __tcu_set_pwm_output_shutdown_abrupt(PWM_CHN); \ -+ __tcu_select_clk_div1(PWM_CHN); \ -+ __tcu_mask_full_match_irq(PWM_CHN); \ -+ __tcu_mask_half_match_irq(PWM_CHN); \ -+ __tcu_set_count(PWM_CHN,0); \ -+ __tcu_set_full_data(PWM_CHN,__cpm_get_extalclk()/1000); \ -+ __tcu_set_half_data(PWM_CHN,__cpm_get_extalclk()/1000*n/100); \ -+ __tcu_enable_pwm_output(PWM_CHN); \ -+ __tcu_select_extalclk(PWM_CHN); \ -+ __tcu_start_counter(PWM_CHN); \ -+} while (0) -+*/ -+#define __lcd_set_backlight_level(n) \ -+do { \ -+__gpio_as_output(GPIO_PWM); \ -+__gpio_set_pin(GPIO_PWM); \ -+} while (0) -+ -+#define __lcd_close_backlight() \ -+do { \ -+__gpio_as_output(GPIO_PWM); \ -+__gpio_clear_pin(GPIO_PWM); \ -+} while (0) -+ -+#elif defined(CONFIG_MIPS_JZ4740_VIRGO) -+#define GPIO_PWM 119 /* GP_D23 */ -+#define PWM_CHN 0 /* pwm channel */ -+#define PWM_FULL 101 -+/* 100 level: 0,1,...,100 */ -+/*#define __lcd_set_backlight_level(n) \ -+do { \ -+ __gpio_as_pwm(0); \ -+ __tcu_disable_pwm_output(PWM_CHN); \ -+ __tcu_stop_counter(PWM_CHN); \ -+ __tcu_init_pwm_output_high(PWM_CHN); \ -+ __tcu_set_pwm_output_shutdown_abrupt(PWM_CHN); \ -+ __tcu_select_clk_div1(PWM_CHN); \ -+ __tcu_mask_full_match_irq(PWM_CHN); \ -+ __tcu_mask_half_match_irq(PWM_CHN); \ -+ __tcu_set_count(PWM_CHN,0); \ -+ __tcu_set_full_data(PWM_CHN,__cpm_get_extalclk()/1000); \ -+ __tcu_set_half_data(PWM_CHN,__cpm_get_extalclk()/1000*n/100); \ -+ __tcu_enable_pwm_output(PWM_CHN); \ -+ __tcu_select_extalclk(PWM_CHN); \ -+ __tcu_start_counter(PWM_CHN); \ -+ } while (0) -+*/ -+ -+#define __lcd_set_backlight_level(n) \ -+do { \ -+__gpio_as_output(GPIO_PWM); \ -+__gpio_set_pin(GPIO_PWM); \ -+} while (0) -+ -+#define __lcd_close_backlight() \ -+do { \ -+__gpio_as_output(GPIO_PWM); \ -+__gpio_clear_pin(GPIO_PWM); \ -+} while (0) -+ -+#elif defined CONFIG_MIPS_JZ4740_LEO -+ -+#define __lcd_set_backlight_level(n) -+#define __lcd_close_backlight() -+ -+#endif /* #if defined(CONFIG_MIPS_JZ4740_PAVO) */ -+ -+#define __lcd_display_pin_init() \ -+do { \ -+ __gpio_as_output(GPIO_DISP_OFF_N); \ -+ __cpm_start_tcu(); \ -+ __lcd_special_pin_init(); \ -+} while (0) -+ -+#define __lcd_display_on() \ -+do { \ -+ __lcd_special_on(); \ -+ __gpio_set_pin(GPIO_DISP_OFF_N); \ -+ udelay(500000); \ -+ __lcd_set_backlight_level(80); \ -+} while (0) -+ -+#define __lcd_display_off() \ -+do { \ -+ __lcd_close_backlight(); \ -+ __lcd_special_off(); \ -+ __gpio_clear_pin(GPIO_DISP_OFF_N); \ -+} while (0) -+ -+#endif /* CONFIG_MIPS_JZ4740_LEO */ -+ -+#if defined(CONFIG_JZLCD_MSTN_240x128) -+#if 0 /* The final version does not use software emulation of VCOM. */ -+ -+#define GPIO_VSYNC 59 -+#define GPIO_VCOM 90 -+ -+#define REG_VCOM REG_GPIO_GPDR((GPIO_VCOM>>5)) -+#define VCOM_BIT (1 << (GPIO_VCOM & 0x1f)) -+static unsigned int vcom_static; -+static void vsync_irq(int irq, void *dev_id, struct pt_regs *reg) -+{ -+ vcom_static = REG_VCOM; -+ vcom_static ^= VCOM_BIT; -+ REG_VCOM = vcom_static; -+} -+ -+#define __lcd_display_pin_init() \ -+ __gpio_as_irq_rise_edge(GPIO_VSYNC); \ -+ __gpio_as_output(GPIO_VCOM); \ -+ { \ -+ static int inited = 0; \ -+ if (!inited) { \ -+ inited = 1; \ -+ if (request_irq(IRQ_GPIO_0 + GPIO_VSYNC, vsync_irq, SA_INTERRUPT, \ -+ "vsync", 0)) { \ -+ err = -EBUSY; \ -+ goto failed; \ -+ }}} -+ -+#endif -+ -+/* We uses AC BIAs pin to generate VCOM signal, so above code should be removed. -+ */ -+ -+#endif -+ -+#if defined(CONFIG_MIPS_JZ4740_PI) -+ -+ /* 100 level: 0,1,...,100 */ -+ #define __lcd_set_backlight_level(n)\ -+ do { \ -+ __gpio_as_output(32*3+27); \ -+ __gpio_set_pin(32*3+27); \ -+ } while (0) -+ -+ #define __lcd_close_backlight() \ -+ do { \ -+ __gpio_as_output(GPIO_PWM); \ -+ __gpio_clear_pin(GPIO_PWM); \ -+ } while (0) -+ -+ #define __lcd_display_pin_init() \ -+ do { \ -+ __gpio_as_output(GPIO_DISP_OFF_N); \ -+ __cpm_start_tcu(); \ -+ __lcd_special_pin_init(); \ -+ } while (0) -+ /* __lcd_set_backlight_level(100); \*/ -+ #define __lcd_display_on() \ -+ do { \ -+ __gpio_set_pin(GPIO_DISP_OFF_N); \ -+ __lcd_special_on(); \ -+ } while (0) -+ -+ #define __lcd_display_off() \ -+ do { \ -+ __lcd_special_off(); \ -+ __gpio_clear_pin(GPIO_DISP_OFF_N); \ -+ } while (0) -+ -+#endif /* CONFIG_MIPS_JZ4740_PI) */ -+ -+/***************************************************************************** -+ * LCD display pin dummy macros -+ *****************************************************************************/ -+#ifndef __lcd_display_pin_init -+#define __lcd_display_pin_init() -+#endif -+#ifndef __lcd_display_on -+#define __lcd_display_on() -+#endif -+#ifndef __lcd_display_off -+#define __lcd_display_off() -+#endif -+#ifndef __lcd_set_backlight_level -+#define __lcd_set_backlight_level(n) -+#endif -+ -+#endif /* __JZLCD_H__ */ diff --git a/cpu/mips/jz_mmc.c b/cpu/mips/jz_mmc.c new file mode 100644 index 0000000..ec0a518 @@ -6111,10 +2951,10 @@ index 0000000..7f0fa1f +#endif /* __MMC_JZMMC_H__ */ diff --git a/cpu/mips/jz_serial.c b/cpu/mips/jz_serial.c new file mode 100644 -index 0000000..446ffa9 +index 0000000..1f06f32 --- /dev/null +++ b/cpu/mips/jz_serial.c -@@ -0,0 +1,167 @@ +@@ -0,0 +1,159 @@ +/* + * Jz47xx UART support + * @@ -6141,10 +2981,6 @@ index 0000000..446ffa9 + */ + +#include -+ -+#if defined(CONFIG_JZ4730) || defined(CONFIG_JZ4740) || defined(CONFIG_JZ4750) \ -+ || defined(CONFIG_JZ4750D) || defined(CONFIG_JZ5730) -+ +#include + +#if defined(CONFIG_JZ4730) @@ -6170,17 +3006,15 @@ index 0000000..446ffa9 +#define UART_BASE CONFIG_SYS_UART_BASE +#endif + -+/****************************************************************************** -+* -+* serial_init - initialize a channel -+* -+* This routine initializes the number of data bits, parity -+* and set the selected baud rate. Interrupts are disabled. -+* Set the modem control signals if the option is selected. -+* -+* RETURNS: N/A -+*/ -+ ++/* ++ * serial_init - initialize a channel ++ * ++ * This routine initializes the number of data bits, parity ++ * and set the selected baud rate. Interrupts are disabled. ++ * Set the modem control signals if the option is selected. ++ * ++ * RETURNS: N/A ++ */ +int serial_init (void) +{ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) @@ -6280,8 +3114,6 @@ index 0000000..446ffa9 + } + return 0; +} -+ -+#endif /* CONFIG_JZ4730 || CONFIG_JZ4740 || CONFIG_JZ4750 || CONFIG_JZ45730 */ diff --git a/cpu/mips/mmc_protocol.h b/cpu/mips/mmc_protocol.h new file mode 100644 index 0000000..9028cdf @@ -12979,10 +9811,10 @@ index 0000000..2840bc0 +#endif /* __JZ4740_H__ */ diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h new file mode 100644 -index 0000000..02af607 +index 0000000..c3bf9c7 --- /dev/null +++ b/include/configs/qi_lb60.h -@@ -0,0 +1,213 @@ +@@ -0,0 +1,215 @@ +/* + * Authors: Xiangfu Liu + * @@ -13030,6 +9862,8 @@ index 0000000..02af607 +#define CONFIG_BOOTDELAY 0 +#define CONFIG_BOOTFILE "uImage" /* file to load */ +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" ++#define CONFIG_EXTRA_ENV_SETTINGS 1 ++#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait" +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" + +/* @@ -13417,10 +10251,10 @@ index 0000000..7042388 +} diff --git a/nand_spl/nand_boot_jz4740.c b/nand_spl/nand_boot_jz4740.c new file mode 100644 -index 0000000..924a47a +index 0000000..146de19 --- /dev/null +++ b/nand_spl/nand_boot_jz4740.c -@@ -0,0 +1,456 @@ +@@ -0,0 +1,438 @@ +/* + * Copyright (C) 2007 Ingenic Semiconductor Inc. + * Author: Peter @@ -13447,10 +10281,8 @@ index 0000000..924a47a +#include +#include + -+#define KEY_1_OUT (32 * 3 + 21) -+#define KEY_1_IN (32 * 3 + 19) -+#define KEY_2_OUT (32 * 3 + 25) -+#define KEY_2_IN (32 * 3 + 26) ++#define KEY_U_OUT (32 * 2 + 16) ++#define KEY_U_IN (32 * 3 + 19) + +/* + * NAND flash definitions @@ -13773,40 +10605,25 @@ index 0000000..924a47a + +static int is_usb_boot() +{ -+ int key2,keyh; -+ -+ key2 = 0; -+ keyh = 0; ++ int keyU = 0; + -+ __gpio_as_output(KEY_1_OUT); -+ __gpio_as_output(KEY_2_OUT); -+ __gpio_as_input(KEY_1_IN); -+ __gpio_as_input(KEY_2_IN); -+ __gpio_disable_pull(KEY_1_IN); -+ __gpio_disable_pull(KEY_2_IN); ++ __gpio_as_input(KEY_U_IN); ++ __gpio_enable_pull(KEY_U_IN); + -+ __gpio_clear_pin(KEY_1_OUT); -+ __gpio_clear_pin(KEY_2_OUT); ++ __gpio_as_output(KEY_U_OUT); ++ __gpio_clear_pin(KEY_U_OUT); + -+ key2 = __gpio_get_pin(KEY_2_IN); -+ keyh = __gpio_get_pin(KEY_1_IN); ++ keyU = __gpio_get_pin(KEY_U_IN); + -+ if(key2) -+ serial_puts("key2"); ++ if (keyU) ++ serial_puts("[U] not pressed\n"); + else -+ serial_puts("key2--"); ++ serial_puts("[U] pressed\n"); + -+ if(keyh) -+ serial_puts("keyh"); -+ else -+ serial_puts("keyh--"); -+ -+ -+ if( ( key2 == 0 ) && ( keyh == 0 ) ) ++ if (keyU == 0) + return 1; + else + return 0; -+ +} + +void nand_boot(void) @@ -13825,9 +10642,8 @@ index 0000000..924a47a + pll_init(); + sdram_init(); + -+ int ret = 0; -+ ret = is_usb_boot(); -+ if(ret) { ++ if(is_usb_boot()) { ++ serial_puts("enter USB BOOT mode\n"); + usb_boot(); + } + diff --git a/target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch b/target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch index 5160b20cd..6aa049b36 100644 --- a/target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch +++ b/target/linux/xburst/image/u-boot/patches/0002-add-xburst-support.patch @@ -6,11 +6,10 @@ From: Xiangfu Liu --- Makefile | 10 + - board/qi_lb60/qi_lb60.c | 39 +++- common/env_common.c | 2 common/lcd.c | 45 ++++ common/main.c | 4 - cpu/mips/Makefile | 4 + cpu/mips/Makefile | 5 cpu/mips/cache.S | 280 ++++++++++---------------- cpu/mips/config.mk | 6 - cpu/mips/cpu.c | 75 +++++++ @@ -19,13 +18,11 @@ From: Xiangfu Liu examples/standalone/mips.lds | 2 include/asm-mips/addrspace.h | 2 include/asm-mips/global_data.h | 11 + - include/configs/qi_lb60.h | 2 include/lcd.h | 56 +++++ lib_mips/board.c | 18 +- lib_mips/bootm.c | 7 + lib_mips/time.c | 4 - nand_spl/nand_boot_jz4740.c | 46 +--- - 20 files changed, 800 insertions(+), 333 deletions(-) + 17 files changed, 757 insertions(+), 290 deletions(-) diff --git a/Makefile b/Makefile @@ -49,89 +46,6 @@ index f06a97c..a318eb4 100644 ## MIPS64 5Kc ######################################################################### -diff --git a/board/qi_lb60/qi_lb60.c b/board/qi_lb60/qi_lb60.c -index 54625c3..aa7b85b 100644 ---- a/board/qi_lb60/qi_lb60.c -+++ b/board/qi_lb60/qi_lb60.c -@@ -12,6 +12,8 @@ - #include - #include - -+DECLARE_GLOBAL_DATA_PTR; -+ - static void gpio_init(void) - { - /* -@@ -25,11 +27,6 @@ static void gpio_init(void) - __gpio_as_sdram_32bit(); - - /* -- * Initialize UART0 pins -- */ -- __gpio_as_uart0(); -- -- /* - * Initialize LCD pins - */ - __gpio_as_lcd_18bit(); -@@ -43,17 +40,31 @@ static void gpio_init(void) - * Initialize Other pins - */ - unsigned int i; -+ for (i = 0; i < 7; i++){ -+ __gpio_as_input(GPIO_KEYIN_BASE + i); -+ __gpio_enable_pull(GPIO_KEYIN_BASE + i); -+ } -+ - for (i = 0; i < 8; i++) { - __gpio_as_output(GPIO_KEYOUT_BASE + i); -- __gpio_set_pin(GPIO_KEYOUT_BASE + i); -+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i); - } - -- for (i = 0; i < 7; i++){ -- __gpio_as_input(GPIO_KEYIN_BASE + i); -- __gpio_enable_pull(GPIO_KEYIN_BASE + i); -+ /* -+ * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the -+ * same gpio, init the gpio as uart0 cause a keyboard bug. so for -+ * end user we disable the uart0 -+ */ -+ if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){ -+ /* if pressed [S] */ -+ printf("[S] pressed, enable UART0\n"); -+ gd->boot_option = 5; -+ __gpio_as_uart0(); -+ } else { -+ printf("[S] not pressed, disable UART0\n"); -+ __gpio_as_input(GPIO_KEYIN_8); -+ __gpio_enable_pull(GPIO_KEYIN_8); - } -- /* __gpio_as_input( GPIO_KEYIN_8 ); */ -- /* __gpio_enable_pull( GPIO_KEYIN_8 ); */ - - __gpio_as_output(GPIO_AUDIO_POP); - __gpio_set_pin(GPIO_AUDIO_POP); -@@ -73,6 +84,11 @@ static void gpio_init(void) - - __gpio_as_input(GPIO_USB_DETECT); - __gpio_enable_pull(GPIO_USB_DETECT); -+ -+ if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) { -+ printf("[M] pressed, boot from sd card\n"); -+ gd->boot_option = 1; -+ } - } - - static void cpm_init(void) -@@ -98,7 +114,6 @@ void board_early_init(void) - - int checkboard (void) - { -- DECLARE_GLOBAL_DATA_PTR; - - printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n", - gd->cpu_clk/1000000); diff --git a/common/env_common.c b/common/env_common.c index 439a4a9..6cfe30b 100644 --- a/common/env_common.c @@ -267,15 +181,16 @@ index 10d8904..ff11ad7 100644 # ifdef CONFIG_BOOT_RETRY_TIME diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile -index 28a1cbb..5207bc5 100644 +index 28a1cbb..33afb66 100644 --- a/cpu/mips/Makefile +++ b/cpu/mips/Makefile -@@ -33,6 +33,10 @@ SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o +@@ -32,7 +32,10 @@ COBJS-y = cpu.o interrupts.o + SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o COBJS-$(CONFIG_PURPLE) += asc_serial.o - COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o -+COBJS-$(CONFIG_JZSOC) += jz4740.o jz_serial.o jz_i2c.o jz_mmc.o jz4740_nand.o -+COBJS-$(CONFIG_DRIVER_CS8900) += jz_cs8900.o +-COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o ++COBJS-$(CONFIG_JZSOC) += jz_serial.o jz_i2c.o jz_mmc.o ++COBJS-$(CONFIG_JZ4740) += jz4740.o jz4740_nand.o +COBJS-$(CONFIG_QI_LB60) += qi_lb60_gpm940b0.o + @@ -1514,19 +1429,6 @@ index b2c4891..23f597e 100644 unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ -diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h -index 02af607..c3bf9c7 100644 ---- a/include/configs/qi_lb60.h -+++ b/include/configs/qi_lb60.h -@@ -45,6 +45,8 @@ - #define CONFIG_BOOTDELAY 0 - #define CONFIG_BOOTFILE "uImage" /* file to load */ - #define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" -+#define CONFIG_EXTRA_ENV_SETTINGS 1 -+#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait" - #define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" - - /* diff --git a/include/lcd.h b/include/lcd.h index 1f85daa..997e246 100644 --- a/include/lcd.h @@ -1745,83 +1647,3 @@ index 07e356d..4654bf4 100644 } + +#endif /* !CONFIG_JzRISC */ -diff --git a/nand_spl/nand_boot_jz4740.c b/nand_spl/nand_boot_jz4740.c -index 924a47a..146de19 100644 ---- a/nand_spl/nand_boot_jz4740.c -+++ b/nand_spl/nand_boot_jz4740.c -@@ -24,10 +24,8 @@ - #include - #include - --#define KEY_1_OUT (32 * 3 + 21) --#define KEY_1_IN (32 * 3 + 19) --#define KEY_2_OUT (32 * 3 + 25) --#define KEY_2_IN (32 * 3 + 26) -+#define KEY_U_OUT (32 * 2 + 16) -+#define KEY_U_IN (32 * 3 + 19) - - /* - * NAND flash definitions -@@ -350,40 +348,25 @@ static void gpio_init(void) - - static int is_usb_boot() - { -- int key2,keyh; -- -- key2 = 0; -- keyh = 0; -+ int keyU = 0; - -- __gpio_as_output(KEY_1_OUT); -- __gpio_as_output(KEY_2_OUT); -- __gpio_as_input(KEY_1_IN); -- __gpio_as_input(KEY_2_IN); -- __gpio_disable_pull(KEY_1_IN); -- __gpio_disable_pull(KEY_2_IN); -+ __gpio_as_input(KEY_U_IN); -+ __gpio_enable_pull(KEY_U_IN); - -- __gpio_clear_pin(KEY_1_OUT); -- __gpio_clear_pin(KEY_2_OUT); -- -- key2 = __gpio_get_pin(KEY_2_IN); -- keyh = __gpio_get_pin(KEY_1_IN); -+ __gpio_as_output(KEY_U_OUT); -+ __gpio_clear_pin(KEY_U_OUT); - -- if(key2) -- serial_puts("key2"); -- else -- serial_puts("key2--"); -+ keyU = __gpio_get_pin(KEY_U_IN); - -- if(keyh) -- serial_puts("keyh"); -+ if (keyU) -+ serial_puts("[U] not pressed\n"); - else -- serial_puts("keyh--"); -+ serial_puts("[U] pressed\n"); - -- -- if( ( key2 == 0 ) && ( keyh == 0 ) ) -+ if (keyU == 0) - return 1; - else - return 0; -- - } - - void nand_boot(void) -@@ -402,9 +385,8 @@ void nand_boot(void) - pll_init(); - sdram_init(); - -- int ret = 0; -- ret = is_usb_boot(); -- if(ret) { -+ if(is_usb_boot()) { -+ serial_puts("enter USB BOOT mode\n"); - usb_boot(); - } -