From f9f05264eb5cb4c2e28c32be4e9526de3d98eb5a Mon Sep 17 00:00:00 2001 From: nbd Date: Sun, 16 May 2010 00:23:06 +0000 Subject: [PATCH] [backfire] merge CRLF changes from r21462 git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@21463 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../files/board/ifx/danube/ddr_settings.h | 100 ++-- .../board/ifx/danube/ddr_settings_r111.h | 100 ++-- .../board/infineon/easy50712/ddr_settings.h | 100 ++-- .../infineon/easy50712/ddr_settings_r111.h | 100 ++-- .../infineon/easy50812/ar9_ddr196_settings.h | 102 ++-- .../patches-2.6.32/230-external_phy_fix.patch | 26 +- .../arch/x86/mach-rdc321x/boards/ar525w.c | 486 +++++++++--------- .../arch/mips/boot/compressed/Makefile | 84 +-- tools/firmware-utils/src/nand_ecc.c | 408 +++++++-------- 9 files changed, 753 insertions(+), 753 deletions(-) diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h index cecd279b3..3a4b1350e 100644 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h +++ b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h @@ -1,50 +1,50 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 -#define MC_DC21_VALUE 0x1d00 -#define MC_DC22_VALUE 0x1d1d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* was 0x7f */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA03 +#define MC_DC21_VALUE 0x1d00 +#define MC_DC22_VALUE 0x1d1d +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x5e /* was 0x7f */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x2d89 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h index 385f7e4e5..fd155973e 100644 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h +++ b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h @@ -1,50 +1,50 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1200 +#define MC_DC22_VALUE 0x1212 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x2d89 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h index cecd279b3..3a4b1350e 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h +++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h @@ -1,50 +1,50 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 -#define MC_DC21_VALUE 0x1d00 -#define MC_DC22_VALUE 0x1d1d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* was 0x7f */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA03 +#define MC_DC21_VALUE 0x1d00 +#define MC_DC22_VALUE 0x1d1d +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x5e /* was 0x7f */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x2d89 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h index 385f7e4e5..fd155973e 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h +++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h @@ -1,50 +1,50 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1200 +#define MC_DC22_VALUE 0x1212 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x2d89 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h index b00177e0a..45daa188d 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h +++ b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h @@ -1,51 +1,51 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x306 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x80B -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xD02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xF -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x5FB -#define MC_DC29_VALUE 0x35DF -#define MC_DC30_VALUE 0x99E9 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x600 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ + +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x306 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x80B +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xD02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0x144 /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xF +#define MC_DC18_VALUE 0x301 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1200 +#define MC_DC22_VALUE 0x1212 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x66 /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x5FB +#define MC_DC29_VALUE 0x35DF +#define MC_DC30_VALUE 0x99E9 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x600 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 diff --git a/target/linux/brcm63xx/patches-2.6.32/230-external_phy_fix.patch b/target/linux/brcm63xx/patches-2.6.32/230-external_phy_fix.patch index 5edcfe8ef..f70d25aa4 100644 --- a/target/linux/brcm63xx/patches-2.6.32/230-external_phy_fix.patch +++ b/target/linux/brcm63xx/patches-2.6.32/230-external_phy_fix.patch @@ -1,13 +1,13 @@ ---- linux-2.6.32.10.orig/drivers/net/bcm63xx_enet.c 2010-04-06 19:25:52.612158288 +0100 -+++ linux-2.6.32.10/drivers/net/bcm63xx_enet.c 2010-04-07 21:40:26.991801424 +0100 -@@ -965,7 +965,9 @@ - /* all set, enable mac and interrupts, start dma engine and - * kick rx dma channel */ - wmb(); -- enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG); -+ val = enet_readl(priv, ENET_CTL_REG); -+ val |= ENET_CTL_ENABLE_MASK; -+ enet_writel(priv, val, ENET_CTL_REG); - enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); - enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, - ENETDMA_CHANCFG_REG(priv->rx_chan)); \ No newline at end of file +--- linux-2.6.32.10.orig/drivers/net/bcm63xx_enet.c 2010-04-06 19:25:52.612158288 +0100 ++++ linux-2.6.32.10/drivers/net/bcm63xx_enet.c 2010-04-07 21:40:26.991801424 +0100 +@@ -965,7 +965,9 @@ + /* all set, enable mac and interrupts, start dma engine and + * kick rx dma channel */ + wmb(); +- enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG); ++ val = enet_readl(priv, ENET_CTL_REG); ++ val |= ENET_CTL_ENABLE_MASK; ++ enet_writel(priv, val, ENET_CTL_REG); + enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); + enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, + ENETDMA_CHANCFG_REG(priv->rx_chan)); diff --git a/target/linux/rdc/files-2.6.30/arch/x86/mach-rdc321x/boards/ar525w.c b/target/linux/rdc/files-2.6.30/arch/x86/mach-rdc321x/boards/ar525w.c index 041a3ba34..5d54a3041 100644 --- a/target/linux/rdc/files-2.6.30/arch/x86/mach-rdc321x/boards/ar525w.c +++ b/target/linux/rdc/files-2.6.30/arch/x86/mach-rdc321x/boards/ar525w.c @@ -1,243 +1,243 @@ -/* - * ar525w RDC321x platform devices - * - * Copyright (C) 2007-2009 OpenWrt.org - * Copyright (C) 2007 Florian Fainelli - * Copyright (C) 2008-2009 Daniel Gimpelevich - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the - * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - * - */ - -#include -#include -#include -#include -#include - -#include - -struct image_header { - char magic[4]; /* ASICII: GMTK */ - u32 checksum; /* CRC32 */ - u32 version; /* x.x.x.x */ - u32 kernelsz; /* The size of the kernel image */ - u32 imagesz; /* The length of this image file ( kernel + romfs + this header) */ - u32 pid; /* Product ID */ - u32 fastcksum; /* Partial CRC32 on (First(256), medium(256), last(512)) */ - u32 reserved; -}; - -static struct gpio_led ar525w_leds[] = { - { .name = "rdc321x:dmz", .gpio = 1, .active_low = 1}, -}; -static struct gpio_button ar525w_btns[] = { - { - .gpio = 6, - .code = BTN_0, - .desc = "Reset", - .active_low = 1, - } -}; - -static u32 __initdata crctab[257] = { - 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, - 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, - 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, - 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, - 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, - 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, - 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, - 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, - 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, - 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, - 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, - 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, - 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, - 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, - 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, - 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, - 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, - 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, - 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, - 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, - 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, - 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, - 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, - 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, - 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, - 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, - 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, - 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, - 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, - 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, - 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, - 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, - 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, - 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, - 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, - 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, - 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, - 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, - 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, - 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, - 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, - 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, - 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, - 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, - 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, - 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, - 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, - 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, - 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, - 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, - 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, - 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, - 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, - 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, - 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, - 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, - 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, - 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, - 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, - 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, - 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, - 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, - 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, - 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, - 0 -}; - -static u32 __init crc32(u8 * buf, u32 len) -{ - register int i; - u32 sum; - register u32 s0; - s0 = ~0; - for (i = 0; i < len; i++) { - s0 = (s0 >> 8) ^ crctab[(u8) (s0 & 0xFF) ^ buf[i]]; - } - sum = ~s0; - return sum; -} - -static int __init fixup_ar525w_header(struct mtd_info *master, struct image_header *header) -{ - char *buffer; - int res; - u32 bufferlength = header->kernelsz + sizeof(struct image_header); - u32 len; - char crcbuf[0x400]; - - printk(KERN_INFO "Fixing up AR525W header, old image size: %u, new image size: %u\n", - header->imagesz, bufferlength); - - buffer = vmalloc(bufferlength); - if (!buffer) { - printk(KERN_ERR "Can't allocate %u bytes\n", bufferlength); - return -ENOMEM; - } - - res = master->read(master, 0x0, bufferlength, &len, buffer); - if (res || len != bufferlength) - goto out; - - header = (struct image_header *) buffer; - header->imagesz = bufferlength; - header->checksum = 0; - header->fastcksum = 0; - - memcpy(crcbuf, buffer, 0x100); - memcpy(crcbuf + 0x100, buffer + (bufferlength >> 1) - ((bufferlength & 0x6) >> 1), 0x100); - memcpy(crcbuf + 0x200, buffer + bufferlength - 0x200, 0x200); - - header->fastcksum = crc32(crcbuf, sizeof(crcbuf)); - header->checksum = crc32(buffer, bufferlength); - - if (master->unlock) - master->unlock(master, 0, master->erasesize); - res = erase_write (master, 0, master->erasesize, buffer); - if (res) - printk(KERN_ERR "Can't rewrite image header\n"); - -out: - vfree(buffer); - return res; -} - -static int __init parse_ar525w_partitions(struct mtd_info *master, struct mtd_partition **pparts, unsigned long plat_data) -{ - struct image_header header; - int res; - size_t len; - struct mtd_partition *rdc_flash_parts; - struct rdc_platform_data *pdata = (struct rdc_platform_data *) plat_data; - - if (master->size != 0x400000) //4MB - return -ENOSYS; - - res = master->read(master, 0x0, sizeof(header), &len, (char *)&header); - if (res) - return res; - - if (strncmp(header.magic, "GMTK", 4)) - return -ENOSYS; - - if (header.kernelsz > 0x400000 || header.kernelsz < master->erasesize) { - printk(KERN_ERR "AR525W image header found, but seems corrupt, kernel size %u\n", header.kernelsz); - return -EINVAL; - } - - if (header.kernelsz + sizeof(header) != header.imagesz) { - res = fixup_ar525w_header(master, &header); - if (res) - return res; - } - - rdc_flash_parts = kzalloc(sizeof(struct mtd_partition) * 3, GFP_KERNEL); - - rdc_flash_parts[0].name = "firmware"; - rdc_flash_parts[0].offset = 0x0; - rdc_flash_parts[0].size = 0x3E0000; - rdc_flash_parts[1].name = "rootfs"; - rdc_flash_parts[1].offset = header.kernelsz + sizeof(header); - rdc_flash_parts[1].size = rdc_flash_parts[0].size - rdc_flash_parts[1].offset; - rdc_flash_parts[2].name = "bootloader"; - rdc_flash_parts[2].offset = 0x3E0000; - rdc_flash_parts[2].size = 0x20000; - - *pparts = rdc_flash_parts; - - pdata->led_data.num_leds = ARRAY_SIZE(ar525w_leds); - pdata->led_data.leds = ar525w_leds; - pdata->button_data.nbuttons = ARRAY_SIZE(ar525w_btns); - pdata->button_data.buttons = ar525w_btns; - - return 3; -} - -static struct mtd_part_parser __initdata ar525w_parser = { - .owner = THIS_MODULE, - .parse_fn = parse_ar525w_partitions, - .name = "AR525W", -}; - -static int __init ar525w_setup(void) -{ - return register_mtd_parser(&ar525w_parser); -} - -arch_initcall(ar525w_setup); +/* + * ar525w RDC321x platform devices + * + * Copyright (C) 2007-2009 OpenWrt.org + * Copyright (C) 2007 Florian Fainelli + * Copyright (C) 2008-2009 Daniel Gimpelevich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include + +#include + +struct image_header { + char magic[4]; /* ASICII: GMTK */ + u32 checksum; /* CRC32 */ + u32 version; /* x.x.x.x */ + u32 kernelsz; /* The size of the kernel image */ + u32 imagesz; /* The length of this image file ( kernel + romfs + this header) */ + u32 pid; /* Product ID */ + u32 fastcksum; /* Partial CRC32 on (First(256), medium(256), last(512)) */ + u32 reserved; +}; + +static struct gpio_led ar525w_leds[] = { + { .name = "rdc321x:dmz", .gpio = 1, .active_low = 1}, +}; +static struct gpio_button ar525w_btns[] = { + { + .gpio = 6, + .code = BTN_0, + .desc = "Reset", + .active_low = 1, + } +}; + +static u32 __initdata crctab[257] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, + 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, + 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, + 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, + 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, + 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, + 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, + 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, + 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, + 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, + 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, + 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, + 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, + 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, + 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, + 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, + 0 +}; + +static u32 __init crc32(u8 * buf, u32 len) +{ + register int i; + u32 sum; + register u32 s0; + s0 = ~0; + for (i = 0; i < len; i++) { + s0 = (s0 >> 8) ^ crctab[(u8) (s0 & 0xFF) ^ buf[i]]; + } + sum = ~s0; + return sum; +} + +static int __init fixup_ar525w_header(struct mtd_info *master, struct image_header *header) +{ + char *buffer; + int res; + u32 bufferlength = header->kernelsz + sizeof(struct image_header); + u32 len; + char crcbuf[0x400]; + + printk(KERN_INFO "Fixing up AR525W header, old image size: %u, new image size: %u\n", + header->imagesz, bufferlength); + + buffer = vmalloc(bufferlength); + if (!buffer) { + printk(KERN_ERR "Can't allocate %u bytes\n", bufferlength); + return -ENOMEM; + } + + res = master->read(master, 0x0, bufferlength, &len, buffer); + if (res || len != bufferlength) + goto out; + + header = (struct image_header *) buffer; + header->imagesz = bufferlength; + header->checksum = 0; + header->fastcksum = 0; + + memcpy(crcbuf, buffer, 0x100); + memcpy(crcbuf + 0x100, buffer + (bufferlength >> 1) - ((bufferlength & 0x6) >> 1), 0x100); + memcpy(crcbuf + 0x200, buffer + bufferlength - 0x200, 0x200); + + header->fastcksum = crc32(crcbuf, sizeof(crcbuf)); + header->checksum = crc32(buffer, bufferlength); + + if (master->unlock) + master->unlock(master, 0, master->erasesize); + res = erase_write (master, 0, master->erasesize, buffer); + if (res) + printk(KERN_ERR "Can't rewrite image header\n"); + +out: + vfree(buffer); + return res; +} + +static int __init parse_ar525w_partitions(struct mtd_info *master, struct mtd_partition **pparts, unsigned long plat_data) +{ + struct image_header header; + int res; + size_t len; + struct mtd_partition *rdc_flash_parts; + struct rdc_platform_data *pdata = (struct rdc_platform_data *) plat_data; + + if (master->size != 0x400000) //4MB + return -ENOSYS; + + res = master->read(master, 0x0, sizeof(header), &len, (char *)&header); + if (res) + return res; + + if (strncmp(header.magic, "GMTK", 4)) + return -ENOSYS; + + if (header.kernelsz > 0x400000 || header.kernelsz < master->erasesize) { + printk(KERN_ERR "AR525W image header found, but seems corrupt, kernel size %u\n", header.kernelsz); + return -EINVAL; + } + + if (header.kernelsz + sizeof(header) != header.imagesz) { + res = fixup_ar525w_header(master, &header); + if (res) + return res; + } + + rdc_flash_parts = kzalloc(sizeof(struct mtd_partition) * 3, GFP_KERNEL); + + rdc_flash_parts[0].name = "firmware"; + rdc_flash_parts[0].offset = 0x0; + rdc_flash_parts[0].size = 0x3E0000; + rdc_flash_parts[1].name = "rootfs"; + rdc_flash_parts[1].offset = header.kernelsz + sizeof(header); + rdc_flash_parts[1].size = rdc_flash_parts[0].size - rdc_flash_parts[1].offset; + rdc_flash_parts[2].name = "bootloader"; + rdc_flash_parts[2].offset = 0x3E0000; + rdc_flash_parts[2].size = 0x20000; + + *pparts = rdc_flash_parts; + + pdata->led_data.num_leds = ARRAY_SIZE(ar525w_leds); + pdata->led_data.leds = ar525w_leds; + pdata->button_data.nbuttons = ARRAY_SIZE(ar525w_btns); + pdata->button_data.buttons = ar525w_btns; + + return 3; +} + +static struct mtd_part_parser __initdata ar525w_parser = { + .owner = THIS_MODULE, + .parse_fn = parse_ar525w_partitions, + .name = "AR525W", +}; + +static int __init ar525w_setup(void) +{ + return register_mtd_parser(&ar525w_parser); +} + +arch_initcall(ar525w_setup); diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile index 9b4132985..90f36e63c 100644 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile +++ b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile @@ -1,42 +1,42 @@ -# -# linux/arch/mips/boot/compressed/Makefile -# -# create a compressed zImage from the original vmlinux -# - -targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o - -OBJS := $(obj)/head.o $(obj)/misc.o - -LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic -OBJCOPY_ARGS := -O elf32-tradlittlemips - -ENTRY := $(obj)/../tools/entry -FILESIZE := $(obj)/../tools/filesize - -drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options -strip-flags = $(addprefix --remove-section=,$(drop-sections)) - - -$(obj)/vmlinux.bin.gz: vmlinux - rm -f $(obj)/vmlinux.bin.gz - $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin - gzip -v9f $(obj)/vmlinux.bin - -$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux - $(CC) $(KBUILD_AFLAGS) \ - -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \ - -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \ - -DLOADADDR=$(loadaddr) \ - -c -o $(obj)/head.o $< - -$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o - $(OBJCOPY) \ - --add-section=.image=$(obj)/vmlinux.bin.gz \ - --set-section-flags=.image=contents,alloc,load,readonly,data \ - $(obj)/dummy.o $(obj)/piggy.o - $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o - $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap - -zImage: $(obj)/vmlinuz - $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage +# +# linux/arch/mips/boot/compressed/Makefile +# +# create a compressed zImage from the original vmlinux +# + +targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o + +OBJS := $(obj)/head.o $(obj)/misc.o + +LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic +OBJCOPY_ARGS := -O elf32-tradlittlemips + +ENTRY := $(obj)/../tools/entry +FILESIZE := $(obj)/../tools/filesize + +drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options +strip-flags = $(addprefix --remove-section=,$(drop-sections)) + + +$(obj)/vmlinux.bin.gz: vmlinux + rm -f $(obj)/vmlinux.bin.gz + $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin + gzip -v9f $(obj)/vmlinux.bin + +$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux + $(CC) $(KBUILD_AFLAGS) \ + -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \ + -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \ + -DLOADADDR=$(loadaddr) \ + -c -o $(obj)/head.o $< + +$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o + $(OBJCOPY) \ + --add-section=.image=$(obj)/vmlinux.bin.gz \ + --set-section-flags=.image=contents,alloc,load,readonly,data \ + $(obj)/dummy.o $(obj)/piggy.o + $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o + $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap + +zImage: $(obj)/vmlinuz + $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage diff --git a/tools/firmware-utils/src/nand_ecc.c b/tools/firmware-utils/src/nand_ecc.c index e270480d7..b1e930515 100644 --- a/tools/firmware-utils/src/nand_ecc.c +++ b/tools/firmware-utils/src/nand_ecc.c @@ -1,204 +1,204 @@ -/* - * calculate ecc code for nand flash - * - * Copyright (C) 2008 yajin - * Copyright (C) 2009 Felix Fietkau - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 or - * (at your option) version 3 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include - -#define DEF_NAND_PAGE_SIZE 2048 -#define DEF_NAND_OOB_SIZE 64 -#define DEF_NAND_ECC_OFFSET 0x28 - -static int page_size = DEF_NAND_PAGE_SIZE; -static int oob_size = DEF_NAND_OOB_SIZE; -static int ecc_offset = DEF_NAND_ECC_OFFSET; - -/* - * Pre-calculated 256-way 1 byte column parity - */ -static const uint8_t nand_ecc_precalc_table[] = { - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 -}; - -/** - * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block - * @dat: raw data - * @ecc_code: buffer for ECC - */ -int nand_calculate_ecc(const uint8_t *dat, - uint8_t *ecc_code) -{ - uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; - int i; - - /* Initialize variables */ - reg1 = reg2 = reg3 = 0; - - /* Build up column parity */ - for(i = 0; i < 256; i++) { - /* Get CP0 - CP5 from table */ - idx = nand_ecc_precalc_table[*dat++]; - reg1 ^= (idx & 0x3f); - - /* All bit XOR = 1 ? */ - if (idx & 0x40) { - reg3 ^= (uint8_t) i; - reg2 ^= ~((uint8_t) i); - } - } - - /* Create non-inverted ECC code from line parity */ - tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */ - tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ - tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */ - tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ - tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */ - tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ - tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */ - tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ - - tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */ - tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ - tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */ - tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ - tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */ - tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ - tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */ - tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */ - - /* Calculate final ECC code */ -#ifdef CONFIG_MTD_NAND_ECC_SMC - ecc_code[0] = ~tmp2; - ecc_code[1] = ~tmp1; -#else - ecc_code[0] = ~tmp1; - ecc_code[1] = ~tmp2; -#endif - ecc_code[2] = ((~reg1) << 2) | 0x03; - - return 0; -} - -/* - * usage: bb-nandflash-ecc start_address size - */ -void usage(const char *prog) -{ - fprintf(stderr, "Usage: %s [options] \n" - "Options:\n" - " -p NAND page size (default: %d)\n" - " -o NAND OOB size (default: %d)\n" - " -e NAND ECC offset (default: %d)\n" - "\n", prog, DEF_NAND_PAGE_SIZE, DEF_NAND_OOB_SIZE, - DEF_NAND_ECC_OFFSET); - exit(1); -} - -/*start_address/size does not include oob - */ -int main(int argc, char **argv) -{ - uint8_t *page_data = NULL; - uint8_t *ecc_data; - int infd = -1, outfd = -1; - int ret = 1; - ssize_t bytes; - int ch; - - while ((ch = getopt(argc, argv, "e:o:p:")) != -1) { - switch(ch) { - case 'p': - page_size = strtoul(optarg, NULL, 0); - break; - case 'o': - oob_size = strtoul(optarg, NULL, 0); - break; - case 'e': - ecc_offset = strtoul(optarg, NULL, 0); - break; - default: - usage(argv[0]); - } - } - argc -= optind; - if (argc < 2) - usage(argv[0]); - - argv += optind; - - infd = open(argv[0], O_RDONLY, 0); - if (infd < 0) { - perror("open input file"); - goto out; - } - - outfd = open(argv[1], O_WRONLY|O_CREAT|O_TRUNC, 0644); - if (outfd < 0) { - perror("open output file"); - goto out; - } - - page_data = malloc(page_size + oob_size); - - while ((bytes = read(infd, page_data, page_size)) == page_size) { - int j; - - ecc_data = page_data + page_size + ecc_offset; - for (j = 0; j < page_size / 256; j++) - { - nand_calculate_ecc(page_data + j * 256, ecc_data); - ecc_data += 3; - } - write(outfd, page_data, page_size + oob_size); - } - - ret = 0; -out: - if (infd >= 0) - close(infd); - if (outfd >= 0) - close(outfd); - if (page_data) - free(page_data); - return ret; -} - +/* + * calculate ecc code for nand flash + * + * Copyright (C) 2008 yajin + * Copyright (C) 2009 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include + +#define DEF_NAND_PAGE_SIZE 2048 +#define DEF_NAND_OOB_SIZE 64 +#define DEF_NAND_ECC_OFFSET 0x28 + +static int page_size = DEF_NAND_PAGE_SIZE; +static int oob_size = DEF_NAND_OOB_SIZE; +static int ecc_offset = DEF_NAND_ECC_OFFSET; + +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const uint8_t nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block + * @dat: raw data + * @ecc_code: buffer for ECC + */ +int nand_calculate_ecc(const uint8_t *dat, + uint8_t *ecc_code) +{ + uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; + int i; + + /* Initialize variables */ + reg1 = reg2 = reg3 = 0; + + /* Build up column parity */ + for(i = 0; i < 256; i++) { + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[*dat++]; + reg1 ^= (idx & 0x3f); + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (uint8_t) i; + reg2 ^= ~((uint8_t) i); + } + } + + /* Create non-inverted ECC code from line parity */ + tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */ + tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ + tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */ + tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ + tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */ + tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ + tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */ + tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ + + tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */ + tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ + tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */ + tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ + tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */ + tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ + tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */ + tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */ + + /* Calculate final ECC code */ +#ifdef CONFIG_MTD_NAND_ECC_SMC + ecc_code[0] = ~tmp2; + ecc_code[1] = ~tmp1; +#else + ecc_code[0] = ~tmp1; + ecc_code[1] = ~tmp2; +#endif + ecc_code[2] = ((~reg1) << 2) | 0x03; + + return 0; +} + +/* + * usage: bb-nandflash-ecc start_address size + */ +void usage(const char *prog) +{ + fprintf(stderr, "Usage: %s [options] \n" + "Options:\n" + " -p NAND page size (default: %d)\n" + " -o NAND OOB size (default: %d)\n" + " -e NAND ECC offset (default: %d)\n" + "\n", prog, DEF_NAND_PAGE_SIZE, DEF_NAND_OOB_SIZE, + DEF_NAND_ECC_OFFSET); + exit(1); +} + +/*start_address/size does not include oob + */ +int main(int argc, char **argv) +{ + uint8_t *page_data = NULL; + uint8_t *ecc_data; + int infd = -1, outfd = -1; + int ret = 1; + ssize_t bytes; + int ch; + + while ((ch = getopt(argc, argv, "e:o:p:")) != -1) { + switch(ch) { + case 'p': + page_size = strtoul(optarg, NULL, 0); + break; + case 'o': + oob_size = strtoul(optarg, NULL, 0); + break; + case 'e': + ecc_offset = strtoul(optarg, NULL, 0); + break; + default: + usage(argv[0]); + } + } + argc -= optind; + if (argc < 2) + usage(argv[0]); + + argv += optind; + + infd = open(argv[0], O_RDONLY, 0); + if (infd < 0) { + perror("open input file"); + goto out; + } + + outfd = open(argv[1], O_WRONLY|O_CREAT|O_TRUNC, 0644); + if (outfd < 0) { + perror("open output file"); + goto out; + } + + page_data = malloc(page_size + oob_size); + + while ((bytes = read(infd, page_data, page_size)) == page_size) { + int j; + + ecc_data = page_data + page_size + ecc_offset; + for (j = 0; j < page_size / 256; j++) + { + nand_calculate_ecc(page_data + j * 256, ecc_data); + ecc_data += 3; + } + write(outfd, page_data, page_size + oob_size); + } + + ret = 0; +out: + if (infd >= 0) + close(infd); + if (outfd >= 0) + close(outfd); + if (page_data) + free(page_data); + return ret; +} +