qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-12-29 20:17:43 +02:00
Code

finally fix pesky irq issues

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@3207 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
mbm 2006-02-09 22:20:42 +00:00
parent bd82ddf487
commit fc64f30a0d
2 changed files with 105 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
openwrt/target/linux/aruba-2.6/patches/000-aruba.patch
View File

@ -1057,14 +1057,13 @@ diff -Nur linux-2.6.15/arch/mips/aruba/wdt_merlot.c linux-2.6.15-openwrt/arch/mi
diff -Nur linux-2.6.15/arch/mips/Kconfig linux-2.6.15-openwrt/arch/mips/Kconfig diff -Nur linux-2.6.15/arch/mips/Kconfig linux-2.6.15-openwrt/arch/mips/Kconfig
--- linux-2.6.15/arch/mips/Kconfig 2006-01-03 04:21:10.000000000 +0100 --- linux-2.6.15/arch/mips/Kconfig 2006-01-03 04:21:10.000000000 +0100
+++ linux-2.6.15-openwrt/arch/mips/Kconfig 2006-01-10 00:32:32.000000000 +0100 +++ linux-2.6.15-openwrt/arch/mips/Kconfig 2006-01-10 00:32:32.000000000 +0100
@@ -227,6 +227,18 @@ @@ -227,6 +227,17 @@
either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
a kernel for this platform. a kernel for this platform.
+config MACH_ARUBA +config MACH_ARUBA
+ bool "Support for the ARUBA product line" + bool "Support for the ARUBA product line"
+ select DMA_NONCOHERENT + select DMA_NONCOHERENT
+ select IRQ_CPU
+ select CPU_HAS_PREFETCH + select CPU_HAS_PREFETCH
+ select HW_HAS_PCI + select HW_HAS_PCI
+ select SWAP_IO_SPACE + select SWAP_IO_SPACE

169
openwrt/target/linux/aruba-2.6/patches/002-irq.patch
View File

@ -92,7 +92,7 @@ diff -Nur linux-2.6.15/arch/mips/aruba/idtIRQ.S linux-2.6.15-openwrt/arch/mips/a
diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/aruba/irq.c diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/aruba/irq.c
--- linux-2.6.15/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100 --- linux-2.6.15/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.15-openwrt/arch/mips/aruba/irq.c 2006-01-10 00:32:32.000000000 +0100 +++ linux-2.6.15-openwrt/arch/mips/aruba/irq.c 2006-01-10 00:32:32.000000000 +0100
@@ -0,0 +1,393 @@ @@ -0,0 +1,424 @@
+/************************************************************************** +/**************************************************************************
+ * + *
+ * BRIEF MODULE DESCRIPTION + * BRIEF MODULE DESCRIPTION
@ -242,9 +242,14 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
+ +
+static void aruba_enable_irq(unsigned int irq_nr) +static void aruba_enable_irq(unsigned int irq_nr)
+{ +{
+ unsigned long flags;
+ int ip = irq_nr - GROUP0_IRQ_BASE; + int ip = irq_nr - GROUP0_IRQ_BASE;
+ unsigned int group, intr_bit; + unsigned int group, intr_bit;
+ volatile unsigned int *addr; + volatile unsigned int *addr;
+
+
+ local_irq_save(flags);
+
+ if (ip < 0) { + if (ip < 0) {
+ enable_local_irq(irq_nr); + enable_local_irq(irq_nr);
+ } else { + } else {
@ -281,57 +286,70 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
+ break; + break;
+ } + }
+ } + }
+
+ local_irq_restore(flags);
+
+} +}
+ +
+static void aruba_disable_irq(unsigned int irq_nr) +static void aruba_disable_irq(unsigned int irq_nr)
+{ +{
+ unsigned long flags;
+ int ip = irq_nr - GROUP0_IRQ_BASE; + int ip = irq_nr - GROUP0_IRQ_BASE;
+ unsigned int group, intr_bit, mask; + unsigned int group, intr_bit, mask;
+ volatile unsigned int *addr; + volatile unsigned int *addr;
+ +
+ // calculate group + local_irq_save(flags);
+ switch (mips_machtype) { +
+ case MACH_ARUBA_AP70: + if (ip < 0) {
+ group = ip >> 5; + disable_local_irq(irq_nr);
+ break; + } else {
+ case MACH_ARUBA_AP65: + // calculate group
+ case MACH_ARUBA_AP60: + switch (mips_machtype) {
+ default: + case MACH_ARUBA_AP70:
+ group = 0; + group = ip >> 5;
+ break; + break;
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ default:
+ group = 0;
+ break;
+ }
+
+ // calc interrupt bit within group
+ ip -= group << 5;
+ intr_bit = 1 << ip;
+
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ addr = intr_group_muscat[group].base_addr;
+ // mask intr within group
+ mask = READ_MASK_MUSCAT(addr);
+ mask |= intr_bit;
+ WRITE_MASK_MUSCAT(addr, mask);
+
+ /*
+ if there are no more interrupts enabled in this
+ group, disable corresponding IP
+ */
+ if (mask == intr_group_muscat[group].mask)
+ disable_local_irq(group_to_ip(group));
+ break;
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ default:
+ addr = intr_group_merlot[group].base_addr;
+ // mask intr within group
+ mask = READ_MASK_MERLOT(addr);
+ mask &= ~intr_bit;
+ WRITE_MASK_MERLOT(addr, mask);
+ if (!mask)
+ disable_local_irq(group_to_ip(group));
+ break;
+ }
+ } + }
+ +
+ // calc interrupt bit within group + local_irq_restore(flags);
+ ip -= group << 5;
+ intr_bit = 1 << ip;
+ +
+ switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ addr = intr_group_muscat[group].base_addr;
+ // mask intr within group
+ mask = READ_MASK_MUSCAT(addr);
+ mask |= intr_bit;
+ WRITE_MASK_MUSCAT(addr, mask);
+
+ /*
+ if there are no more interrupts enabled in this
+ group, disable corresponding IP
+ */
+ if (mask == intr_group_muscat[group].mask)
+ disable_local_irq(group_to_ip(group));
+ break;
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ default:
+ addr = intr_group_merlot[group].base_addr;
+ // mask intr within group
+ mask = READ_MASK_MERLOT(addr);
+ mask &= ~intr_bit;
+ WRITE_MASK_MERLOT(addr, mask);
+ if (!mask)
+ disable_local_irq(group_to_ip(group));
+ break;
+ }
+} +}
+ +
+static unsigned int startup_irq(unsigned int irq_nr) +static unsigned int startup_irq(unsigned int irq_nr)
@ -355,50 +373,60 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
+static void end_irq(unsigned int irq_nr) +static void end_irq(unsigned int irq_nr)
+{ +{
+ +
+ unsigned long flags;
+ int ip = irq_nr - GROUP0_IRQ_BASE; + int ip = irq_nr - GROUP0_IRQ_BASE;
+ unsigned int intr_bit, group; + unsigned int intr_bit, group;
+ volatile unsigned int *addr; + volatile unsigned int *addr;
+ +
+
+ local_irq_save(flags);
+ if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) { + if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) {
+ printk("warning: end_irq %d did not enable (%x)\n", + printk("warning: end_irq %d did not enable (%x) (ignoring)\n",
+ irq_nr, irq_desc[irq_nr].status); + irq_nr, irq_desc[irq_nr].status);
+ } + }
+ +
+ switch (mips_machtype) { + if (ip<0) {
+ case MACH_ARUBA_AP70: + enable_local_irq(irq_nr);
+ if (irq_nr == GROUP4_IRQ_BASE + 9) idt_gpio->gpioistat &= 0xfffffdff; + } else {
+ else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
+ else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
+ else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
+ +
+ group = ip >> 5; + switch (mips_machtype) {
+ case MACH_ARUBA_AP70:
+ if (irq_nr == GROUP4_IRQ_BASE + 9) idt_gpio->gpioistat &= 0xfffffdff;
+ else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
+ else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
+ else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
+ +
+ // calc interrupt bit within group + group = ip >> 5;
+ ip -= (group << 5);
+ intr_bit = 1 << ip;
+ +
+ // first enable the IP mapped to this IRQ + // calc interrupt bit within group
+ enable_local_irq(group_to_ip(group)); + ip -= (group << 5);
+ intr_bit = 1 << ip;
+ +
+ addr = intr_group_muscat[group].base_addr; + // first enable the IP mapped to this IRQ
+ // unmask intr within group + enable_local_irq(group_to_ip(group));
+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
+ break;
+ case MACH_ARUBA_AP65:
+ case MACH_ARUBA_AP60:
+ group = 0;
+ +
+ // calc interrupt bit within group + addr = intr_group_muscat[group].base_addr;
+ intr_bit = 1 << ip; + // unmask intr within group
+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
+ break;
+ +
+ // first enable the IP mapped to this IRQ + case MACH_ARUBA_AP65:
+ enable_local_irq(group_to_ip(group)); + case MACH_ARUBA_AP60:
+ group = 0;
+ +
+ addr = intr_group_merlot[group].base_addr; + // calc interrupt bit within group
+ // unmask intr within group + intr_bit = 1 << ip;
+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit); +
+ break; + // first enable the IP mapped to this IRQ
+ enable_local_irq(group_to_ip(group));
+
+ addr = intr_group_merlot[group].base_addr;
+ // unmask intr within group
+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
+ break;
+ }
+ } + }
+ local_irq_restore(flags);
+} +}
+ +
+static struct hw_interrupt_type aruba_irq_type = { +static struct hw_interrupt_type aruba_irq_type = {
@ -418,6 +446,9 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
+ memset(irq_desc, 0, sizeof(irq_desc)); + memset(irq_desc, 0, sizeof(irq_desc));
+ set_except_vector(0, idtIRQ); + set_except_vector(0, idtIRQ);
+ +
+
+ set_c0_status(0xFF00);
+
+ for (i = 0; i < RC32434_NR_IRQS; i++) { + for (i = 0; i < RC32434_NR_IRQS; i++) {
+ irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL; + irq_desc[i].action = NULL;