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Code

Remove another now obsolete file: ops.h

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This commit is contained in:
Lars-Peter Clausen 2010-01-11 02:16:50 +01:00
parent 5c8c909c75
commit fef52063ca
8 changed files with 151 additions and 2283 deletions
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131
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/clock.h
View File

@ -15,8 +15,6 @@
#ifndef __ASM_JZ4740_CLOCK_H__
#define __ASM_JZ4740_CLOCK_H__
#include <asm/mach-jz4740/ops.h>
#ifndef JZ_EXTAL
//#define JZ_EXTAL 3686400 /* 3.6864 MHz */
#define JZ_EXTAL 12000000 /* 3.6864 MHz */
@ -25,6 +23,135 @@
#define JZ_EXTAL2 32768 /* 32.768 KHz */
#endif
/***************************************************************************
* CPM
***************************************************************************/
#define __cpm_get_pllm() \
((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
#define __cpm_get_plln() \
((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
#define __cpm_get_pllod() \
((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
#define __cpm_get_cdiv() \
((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
#define __cpm_get_hdiv() \
((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
#define __cpm_get_pdiv() \
((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
#define __cpm_get_mdiv() \
((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
#define __cpm_get_ldiv() \
((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
#define __cpm_get_udiv() \
((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
#define __cpm_get_i2sdiv() \
((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
#define __cpm_get_pixdiv() \
((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
#define __cpm_get_mscdiv() \
((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
#define __cpm_get_uhcdiv() \
((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
#define __cpm_get_ssidiv() \
((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
#define __cpm_set_cdiv(v) \
(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
#define __cpm_set_hdiv(v) \
(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
#define __cpm_set_pdiv(v) \
(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
#define __cpm_set_mdiv(v) \
(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
#define __cpm_set_ldiv(v) \
(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
#define __cpm_set_udiv(v) \
(REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
#define __cpm_set_i2sdiv(v) \
(REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
#define __cpm_set_pixdiv(v) \
(REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
#define __cpm_set_mscdiv(v) \
(REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
#define __cpm_set_uhcdiv(v) \
(REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT)))
#define __cpm_ssiclk_select_exclk() \
(REG_CPM_SSICDR &= ~CPM_SSICDR_SCS)
#define __cpm_ssiclk_select_pllout() \
(REG_CPM_SSICDR |= CPM_SSICDR_SCS)
#define __cpm_set_ssidiv(v) \
(REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
#define __cpm_get_cclk_doze_duty() \
((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
#define __cpm_set_cclk_doze_duty(v) \
(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
#define __cpm_idle_mode() \
(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
#define __cpm_sleep_mode() \
(REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
#define __cpm_get_o1st() \
((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
#define __cpm_set_o1st(v) \
(REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
/*
* JZ4740 clocks structure
*/

6
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/gpio.h
View File

@ -25,6 +25,7 @@ enum jz_gpio_function {
JZ_GPIO_FUNC3,
};
/*
Usually a driver for a SoC component has to request several gpio pins and
configure them as funcion pins.
@ -68,6 +69,11 @@ void jz_gpio_enable_pullup(unsigned gpio);
void jz_gpio_disable_pullup(unsigned gpio);
int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
int jz_gpio_port_direction_input(int port, uint32_t mask);
int jz_gpio_port_direction_output(int port, uint32_t mask);
void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
#include <asm/mach-generic/gpio.h>
#define JZ_GPIO_PORTA(x) (x + 32 * 0)

2
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/irq.h
View File

@ -4,7 +4,7 @@
#define MIPS_CPU_IRQ_BASE 0
#define JZ_IRQ_BASE 8
// 1st-level interrupts
/* 1st-level interrupts */
#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
#define JZ_IRQ_I2C JZ_IRQ(1)
#define JZ_IRQ_UHC JZ_IRQ(3)

2
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/jz4740.h
View File

@ -16,7 +16,6 @@
#define __ASM_JZ4740_H__
#include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/ops.h>
#include <asm/mach-jz4740/dma.h>
/*------------------------------------------------------------------
@ -34,7 +33,6 @@
* Follows are related to platform definitions
*/
#include <asm/mach-jz4740/clock.h>
#include <asm/mach-jz4740/serial.h>
#endif /* __ASM_JZ4740_H__ */

2226
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/ops.h
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File diff suppressed because it is too large Load Diff

3
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/regs.h
View File

@ -1938,6 +1938,7 @@
#define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
#define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
#define SADC_CFG_DNUM_BIT 18 /* Sample Number */
#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
#define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
#define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
@ -1947,6 +1948,8 @@
#define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
#define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
#define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
#define SADC_CFG_SNUM(x) ((x) << SADC_CFG_SNUM_BIT)
#define SADC_CFG_DNUM(x) ((x) << SADC_CFG_DNUM_BIT)
#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */

1
target/linux/xburst/files-2.6.31/arch/mips/jz4740/proc.c
View File

@ -31,7 +31,6 @@
#include <asm/pgtable.h>
#include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/clock.h>
#include <asm/mach-jz4740/ops.h>
//#define DEBUG 1
#undef DEBUG

41
target/linux/xburst/files-2.6.31/arch/mips/jz4740/setup.c
View File

@ -38,7 +38,6 @@
#include <asm/pgtable.h>
#include <asm/time.h>
#include <asm/mach-jz4740/regs.h>
#include <asm/mach-jz4740/ops.h>
#include <asm/mach-jz4740/clock.h>
#include <asm/mach-jz4740/serial.h>
@ -49,17 +48,6 @@ extern void jz_halt(void);
extern void jz_power_off(void);
extern void jz_time_init(void);
static void __init sysclocks_setup(void)
{
#if 0
printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n",
(jz_clocks.cclk + 500000) / 1000000,
(jz_clocks.hclk + 500000) / 1000000,
(jz_clocks.pclk + 500000) / 1000000,
(jz_clocks.mclk + 500000) / 1000000);
#endif
}
static void __init soc_cpm_setup(void)
{
/* Enable CKO to external memory */
@ -67,33 +55,6 @@ static void __init soc_cpm_setup(void)
/* CPU enters IDLE mode when executing 'wait' instruction */
__cpm_idle_mode();
/* Setup system clocks */
sysclocks_setup();
}
static void __init soc_harb_setup(void)
{
// __harb_set_priority(0x00); /* CIM>LCD>DMA>ETH>PCI>USB>CBB */
// __harb_set_priority(0x03); /* LCD>CIM>DMA>ETH>PCI>USB>CBB */
// __harb_set_priority(0x0a); /* ETH>LCD>CIM>DMA>PCI>USB>CBB */
}
static void __init soc_emc_setup(void)
{
}
static void __init soc_dmac_setup(void)
{
__dmac_enable_module();
}
static void __init jz_soc_setup(void)
{
soc_cpm_setup();
soc_harb_setup();
soc_emc_setup();
soc_dmac_setup();
}
static void __init jz_serial_setup(void)
@ -140,7 +101,7 @@ void __init plat_mem_setup(void)
_machine_restart = jz_restart;
_machine_halt = jz_halt;
pm_power_off = jz_power_off;
jz_soc_setup();
soc_cpm_setup();
jz_serial_setup();
}