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Commit Graph

7 Commits

Author SHA1 Message Date
matteo
d600b610a6 ar7: remove unneeded packed and array initialization
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10752 3c298f89-4303-0410-b956-a3cf2f4a3e73
2008-04-07 01:30:07 +00:00
matteo
c0feef0d72 vlynq: small fixes
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10711 3c298f89-4303-0410-b956-a3cf2f4a3e73
2008-04-02 14:50:19 +00:00
matteo
d8a1a7c53e add proper email addresses to the comment headers
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10709 3c298f89-4303-0410-b956-a3cf2f4a3e73
2008-04-02 11:45:18 +00:00
matteo
295c04e6cd Let authors holds copyright of the AR7 code (closes #2369)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10708 3c298f89-4303-0410-b956-a3cf2f4a3e73
2008-04-02 11:18:00 +00:00
matteo
1927554d27 vlynq: probe for an external clock first, needed to enable acx on the Leonardo board
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10707 3c298f89-4303-0410-b956-a3cf2f4a3e73
2008-04-02 11:06:50 +00:00
nbd
863d4e55d3 Fix VLYNQ device enable for DG834Gv1
This patch allows VLYNQ devices on the DG834Gv1 to be successfully
enabled.

Currently the "__vlynq_enable_device" function attempts to set the VLYNQ
device clock divisor to values from 1 through 8 until a link is
successfully established. On the DG834Gv1 (but not the DG834Gv2),
setting the VLYNQ device clock divisor to 1 (full rate) results in all
further VLYNQ operations failing (including software reset), so the
device is never enabled. This patches changes the function to only
attempt divisors 2 through 8, and hence the device is successfully
enabled.

Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com>

---------


git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9656 3c298f89-4303-0410-b956-a3cf2f4a3e73
2007-12-04 12:49:54 +00:00
ejka
c3585201fb cleanup vlynq. drop vlynq-pci
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9143 3c298f89-4303-0410-b956-a3cf2f4a3e73
2007-10-05 17:54:36 +00:00