/* * Copyright (C) 2005-2007 by Texas Instruments * Some code has been taken from tusb6010.c * Copyrights for that are attributable to: * Copyright (C) 2006 Nokia Corporation * Jarkko Nikula * Tony Lindgren * * This file is part of the Inventra Controller Driver for Linux. * * The Inventra Controller Driver for Linux is free software; you * can redistribute it and/or modify it under the terms of the GNU * General Public License version 2 as published by the Free Software * Foundation. * * The Inventra Controller Driver for Linux is distributed in * the hope that it will be useful, but WITHOUT ANY WARRANTY; * without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public * License for more details. * * You should have received a copy of the GNU General Public License * along with The Inventra Controller Driver for Linux ; if not, * write to the Free Software Foundation, Inc., 59 Temple Place, * Suite 330, Boston, MA 02111-1307 USA * */ #include #include #include #include #include #include #include #include #include "musb_core.h" #define MUSB_TIMEOUT_A_WAIT_BCON 1100 /* Hooks we hasn't used yet. */ void musb_platform_enable(struct musb *musb) { return; } void musb_platform_disable(struct musb *musb) { return; } void musb_platform_set_mode(struct musb *musb, u8 musb_mode) { return; } /* Code copied form omap2430.c */ static void jz4760_set_vbus(struct musb *musb, int is_on) { u8 devctl; /* HDRC controls CPEN, but beware current surges during device * connect. They can trigger transient overcurrent conditions * that must be ignored. */ devctl = musb_readb(musb->mregs, MUSB_DEVCTL); if (is_on) { musb->is_active = 1; musb->xceiv.default_a = 1; musb->xceiv.state = OTG_STATE_A_WAIT_VRISE; devctl |= MUSB_DEVCTL_SESSION; MUSB_HST_MODE(musb); } else { musb->is_active = 0; /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and * jumping right to B_IDLE... */ musb->xceiv.default_a = 0; musb->xceiv.state = OTG_STATE_B_IDLE; devctl &= ~MUSB_DEVCTL_SESSION; MUSB_DEV_MODE(musb); } musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); DBG(1, "VBUS %s, devctl %02x " /* otg %3x conf %08x prcm %08x */ "\n", otg_state_string(musb), musb_readb(musb->mregs, MUSB_DEVCTL)); } int __init musb_platform_init(struct musb *musb) { if (is_host_enabled(musb)) musb->board_set_vbus = jz4760_set_vbus; musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON; return 0; } int musb_platform_exit(struct musb *musb) { return 0; }