this patch is for SAKC From: Xiangfu Liu create by Carlos --- Makefile | 7 + board/sakc/Makefile | 38 ++++++++ board/sakc/config.mk | 31 ++++++ board/sakc/flash.c | 50 ++++++++++ board/sakc/sakc.c | 94 +++++++++++++++++++ board/sakc/u-boot-nand.lds | 63 +++++++++++++ board/sakc/u-boot.lds | 63 +++++++++++++ cpu/mips/Makefile | 2 cpu/mips/jz_mmc.c | 21 ++++ cpu/mips/mmc_protocol.h | 3 - cpu/mips/qi_lb60_gpm940b0.h | 21 ++++ include/configs/sakc.h | 200 ++++++++++++++++++++++++++++++++++++++++ nand_spl/board/sakc/Makefile | 104 +++++++++++++++++++++ nand_spl/board/sakc/config.mk | 34 +++++++ nand_spl/board/sakc/u-boot.lds | 63 +++++++++++++ nand_spl/nand_boot_jz4740.c | 2 16 files changed, 791 insertions(+), 5 deletions(-) create mode 100644 board/sakc/Makefile create mode 100644 board/sakc/config.mk create mode 100644 board/sakc/flash.c create mode 100644 board/sakc/sakc.c create mode 100644 board/sakc/u-boot-nand.lds create mode 100644 board/sakc/u-boot.lds create mode 100644 include/configs/sakc.h create mode 100644 nand_spl/board/sakc/Makefile create mode 100644 nand_spl/board/sakc/config.mk create mode 100644 nand_spl/board/sakc/u-boot.lds diff --git a/Makefile b/Makefile index a318eb4..7d14b8b 100644 --- a/Makefile +++ b/Makefile @@ -3448,6 +3448,13 @@ qi_lb60_config : unconfig @echo "TEXT_BASE = 0x80100000" > $(obj)board/qi_lb60/config.tmp @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk +sakc_config : unconfig + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @echo "Compile NAND boot image for SAKC" + @$(MKCONFIG) -a sakc mips mips sakc + @echo "TEXT_BASE = 0x80100000" > $(obj)board/sakc/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + ######################################################################### ## MIPS64 5Kc ######################################################################### diff --git a/board/sakc/Makefile b/board/sakc/Makefile new file mode 100644 index 0000000..470447d --- /dev/null +++ b/board/sakc/Makefile @@ -0,0 +1,38 @@ +# +# (C) Copyright 2006 +# Ingenic Semiconductor, +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +SOBJS = + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sakc/config.mk b/board/sakc/config.mk new file mode 100644 index 0000000..b254958 --- /dev/null +++ b/board/sakc/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2006 Qi Hardware, Inc. +# Author: Xiangfu Liu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# SAKC Board +# + +ifndef TEXT_BASE +# ROM version +# TEXT_BASE = 0x88000000 + +# RAM version +TEXT_BASE = 0x80100000 +endif diff --git a/board/sakc/flash.c b/board/sakc/flash.c new file mode 100644 index 0000000..891c604 --- /dev/null +++ b/board/sakc/flash.c @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2009 PI + * xiangfu liu, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 3 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + return (0); +} + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + printf ("flash_erase not implemented\n"); + return 0; +} + +void flash_print_info (flash_info_t * info) +{ + printf ("flash_print_info not implemented\n"); +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + printf ("write_buff not implemented\n"); + return (-1); +} diff --git a/board/sakc/sakc.c b/board/sakc/sakc.c new file mode 100644 index 0000000..85763c7 --- /dev/null +++ b/board/sakc/sakc.c @@ -0,0 +1,94 @@ +/* + * Authors: Xiangfu Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 3 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void gpio_init(void) +{ + /* + * Initialize NAND Flash Pins + */ + __gpio_as_nand(); + + /* + * Initialize SDRAM pins + */ + __gpio_as_sdram_16bit_4725(); + + /* + * Initialize UART0 pins + */ + __gpio_as_uart0(); + + /* + * Initialize LCD pins + */ + __gpio_as_lcd_18bit(); + + /* + * Initialize MSC pins + */ + __gpio_as_msc(); + + /* + * Initialize SSI pins + */ + __gpio_as_ssi(); + + /* + * Initialize I2C pins + */ + __gpio_as_i2c(); + + /* + * Initialize MSC pins + */ + __gpio_as_msc(); + + /* + * Initialize Other pins + */ + __gpio_as_input(GPIO_SD_DETECT); + __gpio_disable_pull(GPIO_SD_DETECT); +} +/* TODO SAKC +static void cpm_init(void) +{ + __cpm_stop_ipu(); + __cpm_stop_cim(); + __cpm_stop_i2c(); + __cpm_stop_ssi(); + __cpm_stop_uart1(); + __cpm_stop_sadc(); + __cpm_stop_uhc(); + __cpm_stop_aic1(); + __cpm_stop_aic2(); +}*/ + +void board_early_init(void) +{ + gpio_init(); + //cpm_init(); //TODO SAKC +} + +/* U-Boot common routines */ + +int checkboard (void) +{ + + printf("Board: SAKC (Ingenic XBurst Jz4725 SoC, Speed %d MHz)\n", + gd->cpu_clk/1000000); + + return 0; /* success */ +} diff --git a/board/sakc/u-boot-nand.lds b/board/sakc/u-boot-nand.lds new file mode 100644 index 0000000..a15a96e --- /dev/null +++ b/board/sakc/u-boot-nand.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2006 + * Ingenic Semiconductor, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/board/sakc/u-boot.lds b/board/sakc/u-boot.lds new file mode 100644 index 0000000..a15a96e --- /dev/null +++ b/board/sakc/u-boot.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2006 + * Ingenic Semiconductor, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile index 33afb66..a177653 100644 --- a/cpu/mips/Makefile +++ b/cpu/mips/Makefile @@ -35,7 +35,7 @@ COBJS-$(CONFIG_PURPLE) += asc_serial.o COBJS-$(CONFIG_JZSOC) += jz_serial.o jz_i2c.o jz_mmc.o COBJS-$(CONFIG_JZ4740) += jz4740.o jz4740_nand.o COBJS-$(CONFIG_QI_LB60) += qi_lb60_gpm940b0.o - +COBJS-$(CONFIG_SAKC) += qi_lb60_gpm940b0.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/mips/jz_mmc.c b/cpu/mips/jz_mmc.c index ec0a518..a71da9e 100644 --- a/cpu/mips/jz_mmc.c +++ b/cpu/mips/jz_mmc.c @@ -41,6 +41,14 @@ static int sd2_0 = 0; /* * GPIO definition */ +#if defined(CONFIG_SAKC) + +#define __msc_init_io() \ +do { \ + __gpio_as_input(GPIO_SD_CD_N); \ +} while (0) + +#else #define __msc_init_io() \ do { \ __gpio_as_output(GPIO_SD_VCC_EN_N); \ @@ -56,11 +64,14 @@ do { \ do { \ __gpio_set_pin(GPIO_SD_VCC_EN_N); \ } while (0) + +#endif /* CONFIG_SAKE */ #define __msc_card_detected() \ ({ \ int detected = 1; \ __gpio_as_input(GPIO_SD_CD_N); \ + __gpio_disable_pull(GPIO_SD_CD_N); \ if (!__gpio_get_pin(GPIO_SD_CD_N)) \ detected = 0; \ detected; \ @@ -358,11 +369,11 @@ int jz_mmc_exec_cmd(struct mmc_request *request) } if (request->cmd == SET_BUS_WIDTH) { if (request->arg == 0x2) { - DEBUG(2, "Use 4-bit bus width\n"); + printf("Use 4-bit bus width\n"); use_4bit = 1; } else { - DEBUG(2, "Use 1-bit bus width\n"); + printf("Use 1-bit bus width\n"); use_4bit = 0; } } @@ -735,7 +746,11 @@ int mmc_select_card(void) if (retval) { return retval; } +#if defined(MMC_BUS_WIDTH_1BIT) + mmc_simple_cmd(&request, SET_BUS_WIDTH, 1, RESPONSE_R1); +#else mmc_simple_cmd(&request, SET_BUS_WIDTH, 2, RESPONSE_R1); +#endif retval = mmc_unpack_r1(&request,&r1,0); if (retval) { return retval; @@ -982,7 +997,9 @@ int mmc_legacy_init(int verbose) __msc_init_io(); /* Step-2: turn on power of card */ +#if !defined(CONFIG_SAKC) __msc_enable_power(); +#endif /* Step-3: Reset MSC Controller. */ __msc_reset(); diff --git a/cpu/mips/mmc_protocol.h b/cpu/mips/mmc_protocol.h index 9028cdf..70c07b6 100644 --- a/cpu/mips/mmc_protocol.h +++ b/cpu/mips/mmc_protocol.h @@ -90,6 +90,7 @@ Known problems or limitations with current version /* SD class */ #define SD_SEND_OP_COND 41 /* bcr [31:0] OCR R3 */ #define SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ + #define SEND_SCR 51 /* adtc [31:0] staff R1 */ /* Don't change the order of these; they are used in dispatch tables */ @@ -102,7 +103,7 @@ enum mmc_rsp_t { RESPONSE_R3 = 5, RESPONSE_R4 = 6, RESPONSE_R5 = 7, - RESPONSE_R6 = 8, + RESPONSE_R6 = 8, }; diff --git a/cpu/mips/qi_lb60_gpm940b0.h b/cpu/mips/qi_lb60_gpm940b0.h index a4f8b0b..16821c6 100644 --- a/cpu/mips/qi_lb60_gpm940b0.h +++ b/cpu/mips/qi_lb60_gpm940b0.h @@ -184,15 +184,33 @@ do { \ __gpio_set_pin(LCD_RET); \ } while (0) +#if defined(CONFIG_SAKC) #define __lcd_close_backlight() \ do { \ __gpio_as_output(GPIO_PWM); \ __gpio_clear_pin(GPIO_PWM); \ } while (0) +#endif +#if defined(CONFIG_SAKC) +#define __lcd_display_pin_init() \ +do { \ + __cpm_start_tcu(); \ + __lcd_special_pin_init(); \ +} while (0) + +#define __lcd_display_on() \ +do { \ + __lcd_special_on(); \ +} while (0) + +#define __lcd_display_off() \ +do { \ + __lcd_special_off(); \ +} while (0) +#else #define __lcd_display_pin_init() \ do { \ - __gpio_as_output(GPIO_DISP_OFF_N); \ __cpm_start_tcu(); \ __lcd_special_pin_init(); \ } while (0) @@ -208,5 +226,6 @@ do { \ __lcd_special_off(); \ __gpio_clear_pin(GPIO_DISP_OFF_N); \ } while (0) +#endif #endif /* __QI_LB60_GPM940B0_H__ */ diff --git a/include/configs/sakc.h b/include/configs/sakc.h new file mode 100644 index 0000000..e0bc34e --- /dev/null +++ b/include/configs/sakc.h @@ -0,0 +1,200 @@ +/* + * Authors: Xiangfu Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 3 of the License, or (at your option) any later version. + */ + +/* + * This file contains the configuration parameters for SAKC. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_JzRISC 1 /* JzRISC core */ +#define CONFIG_JZSOC 1 /* Jz SoC */ +#define CONFIG_JZ4725 1 /* Jz4725 SoC */ +#define CONFIG_JZ4740 1 /* Jz4740 SoC */ +#define CONFIG_SAKC 1 /* SAKC board */ + +#define MMC_BUS_WIDTH_1BIT 1 /* 1 for MMC 1Bit Bus Width */ + +//#define CONFIG_LCD 1 /* LCD support */ +//#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */ +//#define CONFIG_SYS_WHITE_ON_BLACK 1 + +#define CONFIG_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ +#define CONFIG_EXTAL 12000000 /* EXTAL freq: 12 MHz */ +#define CONFIG_SYS_HZ (CONFIG_EXTAL / 256) /* incrementer freq */ +#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_CPU_SPEED + +#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */ +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_MMC 1 +#define CONFIG_FAT 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" /* file to load */ +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" +#define CONFIG_EXTRA_ENV_SETTINGS 1 +#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait" +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" + +/* + * Command line configuration. + */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ + +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVEENV /* saveenv */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_SOURCE /* "source" command support */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ + +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT + +/* + * Serial download configuration + */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "SAKC# " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ + +#define CONFIG_SYS_MALLOC_LEN 128 * 1024 +#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80800000 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ + +/* + * NAND FLASH configuration + */ +/* NAND Boot config code */ +#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 + +#define SAKC_NAND_SIZE 1 /* if board nand flash is 1GB, set to 1 + * if board nand flash is 2GB, set to 2 + * for change the PAGE_SIZE and BLOCK_SIZE + * will delete when there is no 1GB flash + */ + +#define CONFIG_NAND_PAGE_SIZE (2048 * SAKC_NAND_SIZE) +/* nand chip block size */ +#define CONFIG_NAND_BLOCK_SIZE (256 * SAKC_NAND_SIZE << 10) +/* nand bad block was marked at this page in a block, start from 0 */ +#define CONFIG_NAND_BADBLOCK_PAGE 127 +/* ECC offset position in oob area, default value is 6 if it isn't defined */ +#define CONFIG_NAND_ECC_POS (6 * SAKC_NAND_SIZE) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xB8000000 +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/ +#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 8k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 8kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + */ +#define CONFIG_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */ +#define CONFIG_NAND_U_BOOT_START CONFIG_NAND_U_BOOT_DST +/* Start NUB from this addr*/ + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CONFIG_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */ +#define CONFIG_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ + +#define CONFIG_ENV_SIZE CONFIG_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (CONFIG_NAND_BLOCK_SIZE + CONFIG_NAND_U_BOOT_SIZE + CONFIG_NAND_BLOCK_SIZE) +/* environment starts here */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) + +/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE + +/* + * SDRAM Info. + */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* SDRAM paramters */ +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ +#define SDRAM_COL 9 /* Column address: 8 to 12 */ +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ + +/* SDRAM Timings, unit: ns */ +#define SDRAM_TRAS 45 /* RAS# Active Time */ +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ + +/* + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * GPIO definition + */ +#define GPIO_SD_DETECT (2 * 32 + 27) +#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ +#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/sakc/Makefile b/nand_spl/board/sakc/Makefile new file mode 100644 index 0000000..bd45379 --- /dev/null +++ b/nand_spl/board/sakc/Makefile @@ -0,0 +1,104 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o usb_boot.o +COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin + dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1 + cat $< $(nandobj)junk1 > $(nandobj)junk2 + dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3 + cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4 + dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5 + cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6 + dd bs=1024 count=256 if=$(nandobj)junk6 of=$@ + rm -f $(nandobj)junk* + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +# from cpu directory +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S + +$(obj)usb_boot.S: + @rm -f $(obj)usb_boot.S + ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S + +$(obj)cpu.c: + @rm -f $(obj)cpu.c + ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c + +$(obj)jz4740.c: + @rm -f $(obj)jz4740.c + ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c + +$(obj)jz_serial.c: + @rm -f $(obj)jz_serial.c + ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c + +# from nand_spl directory +$(obj)nand_boot_jz4740.c: + @rm -f $(obj)nand_boot_jz4740.c + ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/sakc/config.mk b/nand_spl/board/sakc/config.mk new file mode 100644 index 0000000..698c476 --- /dev/null +++ b/nand_spl/board/sakc/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# Ingenic JZ4740 Reference Platform +# + +# +# TEXT_BASE for SPL: +# +# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000, +# in the first 4kBytes of memory space in cache. So we set +# TEXT_BASE to starting address in internal cache here. +# +TEXT_BASE = 0x80000000 diff --git a/nand_spl/board/sakc/u-boot.lds b/nand_spl/board/sakc/u-boot.lds new file mode 100644 index 0000000..7042388 --- /dev/null +++ b/nand_spl/board/sakc/u-boot.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2005 + * Ingenic Semiconductor, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/nand_spl/nand_boot_jz4740.c b/nand_spl/nand_boot_jz4740.c index 146de19..a70ca55 100644 --- a/nand_spl/nand_boot_jz4740.c +++ b/nand_spl/nand_boot_jz4740.c @@ -385,10 +385,12 @@ void nand_boot(void) pll_init(); sdram_init(); +#if defined(CONFIG_QI_LB60) if(is_usb_boot()) { serial_puts("enter USB BOOT mode\n"); usb_boot(); } +#endif #if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) bus_width = 8;