From 0ea046d777bf567cfd89c7d968c0b962e3e7589b Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 11 Apr 2012 18:47:53 +0200 Subject: [PATCH 68/70] MIPS: lantiq: stp, fix for ase, add get, clock disabled Lantiq serial-to-parallel hardware gpio module Added gpio pins as used for amazon se (ase) Added get to enable reporting of gpio status Changed to use software update, as hw clock was not running on ase. Clock really only needed if hw flashing was implemented. Signed-off-by: Conor O'Gorman --- arch/mips/lantiq/xway/gpio_stp.c | 22 +++++++++++++--------- 1 files changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c index 9610c10..791beeb 100644 --- a/arch/mips/lantiq/xway/gpio_stp.c +++ b/arch/mips/lantiq/xway/gpio_stp.c @@ -27,6 +27,7 @@ #define LTQ_STP_AR 0x10 #define LTQ_STP_CON_SWU (1 << 31) +#define LTQ_STP_SWU_MASK (1 << 31) #define LTQ_STP_2HZ 0 #define LTQ_STP_4HZ (1 << 23) #define LTQ_STP_8HZ (2 << 23) @@ -60,6 +61,12 @@ static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value) else ltq_stp_shadow &= ~(1 << offset); ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0); + ltq_stp_w32_mask(LTQ_STP_SWU_MASK, LTQ_STP_CON_SWU, LTQ_STP_CON0); +} + +static int ltq_stp_get(struct gpio_chip *chip, unsigned offset) +{ + return !!(ltq_stp_r32(LTQ_STP_CPU0) & (1<dev, 4, 2, 1, "stp-st") || - ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") || - ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) { + pin = ltq_is_ase() ? 1 : 4; + if (ltq_gpio_request(&pdev->dev, pin, 2, 1, "stp-st") || + ltq_gpio_request(&pdev->dev, pin+1, 2, 1, "stp-d") || + ltq_gpio_request(&pdev->dev, pin+2, 2, 1, "stp-sh")) { dev_err(&pdev->dev, "failed to request needed gpios\n"); return -EBUSY; } -- 1.7.9.1