mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-27 23:29:22 +02:00
a604d7454c
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29574 3c298f89-4303-0410-b956-a3cf2f4a3e73
3977 lines
116 KiB
Diff
3977 lines
116 KiB
Diff
--- /dev/null
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+++ b/Documentation/ABI/testing/sysfs-bus-bcma
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@@ -0,0 +1,31 @@
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+What: /sys/bus/bcma/devices/.../manuf
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+Date: May 2011
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+KernelVersion: 2.6.40
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+Contact: Rafał Miłecki <zajec5@gmail.com>
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+Description:
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+ Each BCMA core has it's manufacturer id. See
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+ include/linux/bcma/bcma.h for possible values.
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+
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+What: /sys/bus/bcma/devices/.../id
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+Date: May 2011
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+KernelVersion: 2.6.40
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+Contact: Rafał Miłecki <zajec5@gmail.com>
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+Description:
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+ There are a few types of BCMA cores, they can be identified by
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+ id field.
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+
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+What: /sys/bus/bcma/devices/.../rev
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+Date: May 2011
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+KernelVersion: 2.6.40
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+Contact: Rafał Miłecki <zajec5@gmail.com>
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+Description:
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+ BCMA cores of the same type can still slightly differ depending
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+ on their revision. Use it for detailed programming.
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+
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+What: /sys/bus/bcma/devices/.../class
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+Date: May 2011
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+KernelVersion: 2.6.40
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+Contact: Rafał Miłecki <zajec5@gmail.com>
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+Description:
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+ Each BCMA core is identified by few fields, including class it
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+ belongs to. See include/linux/bcma/bcma.h for possible values.
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -5264,6 +5264,13 @@ S: Maintained
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F: drivers/ssb/
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F: include/linux/ssb/
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+BROADCOM SPECIFIC AMBA DRIVER (BCMA)
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+M: Rafał Miłecki <zajec5@gmail.com>
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+L: linux-wireless@vger.kernel.org
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+S: Maintained
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+F: drivers/bcma/
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+F: include/linux/bcma/
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+
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SONY VAIO CONTROL DEVICE DRIVER
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P: Mattia Dongili
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M: malattia@linux.it
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--- a/drivers/Kconfig
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+++ b/drivers/Kconfig
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@@ -66,6 +66,8 @@ source "drivers/watchdog/Kconfig"
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source "drivers/ssb/Kconfig"
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+source "drivers/bcma/Kconfig"
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+
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source "drivers/mfd/Kconfig"
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source "drivers/regulator/Kconfig"
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--- a/drivers/Makefile
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+++ b/drivers/Makefile
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@@ -104,6 +104,7 @@ obj-$(CONFIG_HID) += hid/
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obj-$(CONFIG_PPC_PS3) += ps3/
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obj-$(CONFIG_OF) += of/
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obj-$(CONFIG_SSB) += ssb/
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+obj-$(CONFIG_BCMA) += bcma/
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obj-$(CONFIG_VIRTIO) += virtio/
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obj-$(CONFIG_STAGING) += staging/
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obj-y += platform/
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--- /dev/null
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+++ b/drivers/bcma/Kconfig
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@@ -0,0 +1,57 @@
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+config BCMA_POSSIBLE
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+ bool
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+ depends on HAS_IOMEM && HAS_DMA
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+ default y
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+
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+menu "Broadcom specific AMBA"
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+ depends on BCMA_POSSIBLE
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+
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+config BCMA
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+ tristate "BCMA support"
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+ depends on BCMA_POSSIBLE
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+ help
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+ Bus driver for Broadcom specific Advanced Microcontroller Bus
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+ Architecture.
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+
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+# Support for Block-I/O. SELECT this from the driver that needs it.
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+config BCMA_BLOCKIO
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+ bool
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+ depends on BCMA
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+
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+config BCMA_HOST_PCI_POSSIBLE
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+ bool
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+ depends on BCMA && PCI = y
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+ default y
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+
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+config BCMA_HOST_PCI
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+ bool "Support for BCMA on PCI-host bus"
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+ depends on BCMA_HOST_PCI_POSSIBLE
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+
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+config BCMA_DRIVER_PCI_HOSTMODE
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+ bool "Driver for PCI core working in hostmode"
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+ depends on BCMA && MIPS
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+ help
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+ PCI core hostmode operation (external PCI bus).
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+
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+config BCMA_HOST_SOC
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+ bool
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+ depends on BCMA_DRIVER_MIPS
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+
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+config BCMA_DRIVER_MIPS
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+ bool "BCMA Broadcom MIPS core driver"
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+ depends on BCMA && MIPS
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+ help
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+ Driver for the Broadcom MIPS core attached to Broadcom specific
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+ Advanced Microcontroller Bus.
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+
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+ If unsure, say N
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+
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+config BCMA_DEBUG
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+ bool "BCMA debugging"
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+ depends on BCMA
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+ help
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+ This turns on additional debugging messages.
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+
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+ If unsure, say N
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+
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+endmenu
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--- /dev/null
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+++ b/drivers/bcma/Makefile
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@@ -0,0 +1,10 @@
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+bcma-y += main.o scan.o core.o sprom.o
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+bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
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+bcma-y += driver_pci.o
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+bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
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+bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
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+bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
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+bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
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+obj-$(CONFIG_BCMA) += bcma.o
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+
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+ccflags-$(CONFIG_BCMA_DEBUG) := -DDEBUG
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--- /dev/null
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+++ b/drivers/bcma/README
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@@ -0,0 +1,19 @@
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+Broadcom introduced new bus as replacement for older SSB. It is based on AMBA,
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+however from programming point of view there is nothing AMBA specific we use.
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+
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+Standard AMBA drivers are platform specific, have hardcoded addresses and use
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+AMBA standard fields like CID and PID.
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+
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+In case of Broadcom's cards every device consists of:
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+1) Broadcom specific AMBA device. It is put on AMBA bus, but can not be treated
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+ as standard AMBA device. Reading it's CID or PID can cause machine lockup.
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+2) AMBA standard devices called ports or wrappers. They have CIDs (AMBA_CID)
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+ and PIDs (0x103BB369), but we do not use that info for anything. One of that
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+ devices is used for managing Broadcom specific core.
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+
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+Addresses of AMBA devices are not hardcoded in driver and have to be read from
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+EPROM.
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+
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+In this situation we decided to introduce separated bus. It can contain up to
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+16 devices identified by Broadcom specific fields: manufacturer, id, revision
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+and class.
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--- /dev/null
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+++ b/drivers/bcma/TODO
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@@ -0,0 +1,3 @@
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+- Interrupts
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+- Defines for PCI core driver
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+- Create kernel Documentation (use info from README)
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--- /dev/null
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+++ b/drivers/bcma/bcma_private.h
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@@ -0,0 +1,54 @@
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+#ifndef LINUX_BCMA_PRIVATE_H_
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+#define LINUX_BCMA_PRIVATE_H_
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+
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+#ifndef pr_fmt
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+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+#endif
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+
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+#include <linux/bcma/bcma.h>
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+#include <linux/delay.h>
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+
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+#define BCMA_CORE_SIZE 0x1000
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+
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+struct bcma_bus;
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+
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+/* main.c */
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+int bcma_bus_register(struct bcma_bus *bus);
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+void bcma_bus_unregister(struct bcma_bus *bus);
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+int __init bcma_bus_early_register(struct bcma_bus *bus,
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+ struct bcma_device *core_cc,
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+ struct bcma_device *core_mips);
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+#ifdef CONFIG_PM
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+int bcma_bus_resume(struct bcma_bus *bus);
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+#endif
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+
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+/* scan.c */
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+int bcma_bus_scan(struct bcma_bus *bus);
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+int __init bcma_bus_scan_early(struct bcma_bus *bus,
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+ struct bcma_device_id *match,
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+ struct bcma_device *core);
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+void bcma_init_bus(struct bcma_bus *bus);
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+
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+/* sprom.c */
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+int bcma_sprom_get(struct bcma_bus *bus);
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+
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+/* driver_chipcommon.c */
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+#ifdef CONFIG_BCMA_DRIVER_MIPS
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+void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
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+#endif /* CONFIG_BCMA_DRIVER_MIPS */
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+
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+/* driver_chipcommon_pmu.c */
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+u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
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+u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
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+
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+#ifdef CONFIG_BCMA_HOST_PCI
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+/* host_pci.c */
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+extern int __init bcma_host_pci_init(void);
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+extern void __exit bcma_host_pci_exit(void);
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+#endif /* CONFIG_BCMA_HOST_PCI */
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+
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+#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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+void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
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+#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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+
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+#endif
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--- /dev/null
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+++ b/drivers/bcma/core.c
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@@ -0,0 +1,126 @@
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+/*
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+ * Broadcom specific AMBA
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+ * Core ops
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include "bcma_private.h"
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+#include <linux/bcma/bcma.h>
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+
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+bool bcma_core_is_enabled(struct bcma_device *core)
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+{
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+ if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
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+ != BCMA_IOCTL_CLK)
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+ return false;
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+ if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
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+ return false;
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+ return true;
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+}
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+EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
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+
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+void bcma_core_disable(struct bcma_device *core, u32 flags)
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+{
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+ if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
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+ return;
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+
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+ bcma_awrite32(core, BCMA_IOCTL, flags);
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+ bcma_aread32(core, BCMA_IOCTL);
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+ udelay(10);
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+
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+ bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
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+ udelay(1);
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+}
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+EXPORT_SYMBOL_GPL(bcma_core_disable);
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+
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+int bcma_core_enable(struct bcma_device *core, u32 flags)
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+{
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+ bcma_core_disable(core, flags);
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+
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+ bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
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+ bcma_aread32(core, BCMA_IOCTL);
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+
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+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+ udelay(1);
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+
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+ bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
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+ bcma_aread32(core, BCMA_IOCTL);
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+ udelay(1);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(bcma_core_enable);
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+
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+void bcma_core_set_clockmode(struct bcma_device *core,
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+ enum bcma_clkmode clkmode)
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+{
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+ u16 i;
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+
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+ WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
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+ core->id.id != BCMA_CORE_PCIE &&
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+ core->id.id != BCMA_CORE_80211);
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+
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+ switch (clkmode) {
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+ case BCMA_CLKMODE_FAST:
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+ bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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+ udelay(64);
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+ for (i = 0; i < 1500; i++) {
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+ if (bcma_read32(core, BCMA_CLKCTLST) &
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+ BCMA_CLKCTLST_HAVEHT) {
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+ i = 0;
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+ break;
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+ }
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+ udelay(10);
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+ }
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+ if (i)
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+ pr_err("HT force timeout\n");
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+ break;
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+ case BCMA_CLKMODE_DYNAMIC:
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+ pr_warning("Dynamic clockmode not supported yet!\n");
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+ break;
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+ }
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+}
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+EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
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+
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+void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
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+{
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+ u16 i;
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+
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+ WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
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+ WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);
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+
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+ if (on) {
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+ bcma_set32(core, BCMA_CLKCTLST, req);
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+ for (i = 0; i < 10000; i++) {
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+ if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
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+ status) {
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+ i = 0;
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+ break;
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+ }
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+ udelay(10);
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+ }
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+ if (i)
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+ pr_err("PLL enable timeout\n");
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+ } else {
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+ pr_warning("Disabling PLL not supported yet!\n");
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+ }
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+}
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+EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
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+
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+u32 bcma_core_dma_translation(struct bcma_device *core)
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+{
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+ switch (core->bus->hosttype) {
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+ case BCMA_HOSTTYPE_SOC:
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+ return 0;
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+ case BCMA_HOSTTYPE_PCI:
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+ if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
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+ return BCMA_DMA_TRANSLATION_DMA64_CMT;
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+ else
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+ return BCMA_DMA_TRANSLATION_DMA32_CMT;
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+ default:
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+ pr_err("DMA translation unknown for host %d\n",
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+ core->bus->hosttype);
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+ }
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+ return BCMA_DMA_TRANSLATION_NONE;
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+}
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+EXPORT_SYMBOL(bcma_core_dma_translation);
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--- /dev/null
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -0,0 +1,156 @@
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+/*
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+ * Broadcom specific AMBA
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+ * ChipCommon core driver
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+ *
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+ * Copyright 2005, Broadcom Corporation
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+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include "bcma_private.h"
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+#include <linux/bcma/bcma.h>
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+
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+static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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+ u32 mask, u32 value)
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+{
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+ value &= mask;
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+ value |= bcma_cc_read32(cc, offset) & ~mask;
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+ bcma_cc_write32(cc, offset, value);
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+
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+ return value;
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+}
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+
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+void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
|
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+{
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+ u32 leddc_on = 10;
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+ u32 leddc_off = 90;
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+
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+ if (cc->setup_done)
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+ return;
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+
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+ if (cc->core->id.rev >= 11)
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+ cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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+ cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
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+ if (cc->core->id.rev >= 35)
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+ cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
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+
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+ if (cc->core->id.rev >= 20) {
|
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+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
|
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+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
|
|
+ }
|
|
+
|
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+ if (cc->capabilities & BCMA_CC_CAP_PMU)
|
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+ bcma_pmu_init(cc);
|
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+ if (cc->capabilities & BCMA_CC_CAP_PCTL)
|
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+ pr_err("Power control not implemented!\n");
|
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+
|
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+ if (cc->core->id.rev >= 16) {
|
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+ if (cc->core->bus->sprom.leddc_on_time &&
|
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+ cc->core->bus->sprom.leddc_off_time) {
|
|
+ leddc_on = cc->core->bus->sprom.leddc_on_time;
|
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+ leddc_off = cc->core->bus->sprom.leddc_off_time;
|
|
+ }
|
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+ bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
|
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+ ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
|
|
+ (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
|
|
+ }
|
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+
|
|
+ cc->setup_done = true;
|
|
+}
|
|
+
|
|
+/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
|
|
+void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
|
|
+{
|
|
+ /* instant NMI */
|
|
+ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
|
|
+}
|
|
+
|
|
+void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
|
|
+{
|
|
+ return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
|
|
+{
|
|
+ return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
|
|
+
|
|
+u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
|
|
+}
|
|
+
|
|
+u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
|
+{
|
|
+ return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
+void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ unsigned int irq;
|
|
+ u32 baud_base;
|
|
+ u32 i;
|
|
+ unsigned int ccrev = cc->core->id.rev;
|
|
+ struct bcma_serial_port *ports = cc->serial_ports;
|
|
+
|
|
+ if (ccrev >= 11 && ccrev != 15) {
|
|
+ /* Fixed ALP clock */
|
|
+ baud_base = bcma_pmu_alp_clock(cc);
|
|
+ if (ccrev >= 21) {
|
|
+ /* Turn off UART clock before switching clocksource. */
|
|
+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
|
|
+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
|
|
+ & ~BCMA_CC_CORECTL_UARTCLKEN);
|
|
+ }
|
|
+ /* Set the override bit so we don't divide it */
|
|
+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
|
|
+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
|
|
+ | BCMA_CC_CORECTL_UARTCLK0);
|
|
+ if (ccrev >= 21) {
|
|
+ /* Re-enable the UART clock. */
|
|
+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
|
|
+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
|
|
+ | BCMA_CC_CORECTL_UARTCLKEN);
|
|
+ }
|
|
+ } else {
|
|
+ pr_err("serial not supported on this device ccrev: 0x%x\n",
|
|
+ ccrev);
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ irq = bcma_core_mips_irq(cc->core);
|
|
+
|
|
+ /* Determine the registers of the UARTs */
|
|
+ cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
|
|
+ for (i = 0; i < cc->nr_serial_ports; i++) {
|
|
+ ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
|
|
+ (i * 256);
|
|
+ ports[i].irq = irq;
|
|
+ ports[i].baud_base = baud_base;
|
|
+ ports[i].reg_shift = 0;
|
|
+ }
|
|
+}
|
|
+#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/driver_chipcommon_pmu.c
|
|
@@ -0,0 +1,309 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * ChipCommon Power Management Unit driver
|
|
+ *
|
|
+ * Copyright 2009, Michael Buesch <m@bues.ch>
|
|
+ * Copyright 2007, Broadcom Corporation
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+#include <linux/bcma/bcma.h>
|
|
+
|
|
+static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
|
|
+{
|
|
+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
|
+ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
|
|
+ return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
|
|
+}
|
|
+
|
|
+void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
|
|
+{
|
|
+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
|
+ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
|
|
+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
|
|
+
|
|
+void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
|
|
+ u32 set)
|
|
+{
|
|
+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
|
|
+ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
|
|
+ bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
|
|
+
|
|
+void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
|
|
+ u32 offset, u32 mask, u32 set)
|
|
+{
|
|
+ bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
|
|
+ bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
|
|
+ bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
|
|
+
|
|
+void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
|
|
+ u32 set)
|
|
+{
|
|
+ bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
|
|
+ bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
|
|
+ bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
|
|
+
|
|
+static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case 0x4313:
|
|
+ case 0x4331:
|
|
+ case 43224:
|
|
+ case 43225:
|
|
+ break;
|
|
+ default:
|
|
+ pr_err("PLL init unknown for device 0x%04X\n",
|
|
+ bus->chipinfo.id);
|
|
+ }
|
|
+}
|
|
+
|
|
+static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+ u32 min_msk = 0, max_msk = 0;
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case 0x4313:
|
|
+ min_msk = 0x200D;
|
|
+ max_msk = 0xFFFF;
|
|
+ break;
|
|
+ case 43224:
|
|
+ case 43225:
|
|
+ break;
|
|
+ default:
|
|
+ pr_err("PMU resource config unknown for device 0x%04X\n",
|
|
+ bus->chipinfo.id);
|
|
+ }
|
|
+
|
|
+ /* Set the resource masks. */
|
|
+ if (min_msk)
|
|
+ bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
|
|
+ if (max_msk)
|
|
+ bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
|
|
+}
|
|
+
|
|
+void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case 0x4313:
|
|
+ case 0x4331:
|
|
+ case 43224:
|
|
+ case 43225:
|
|
+ break;
|
|
+ default:
|
|
+ pr_err("PMU switch/regulators init unknown for device "
|
|
+ "0x%04X\n", bus->chipinfo.id);
|
|
+ }
|
|
+}
|
|
+
|
|
+/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
|
|
+void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+ u32 val;
|
|
+
|
|
+ val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
|
|
+ if (enable) {
|
|
+ val |= BCMA_CHIPCTL_4331_EXTPA_EN;
|
|
+ if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
|
|
+ val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
|
|
+ } else {
|
|
+ val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
|
|
+ val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
|
|
+ }
|
|
+ bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
|
|
+}
|
|
+
|
|
+void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case 0x4313:
|
|
+ bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
|
|
+ break;
|
|
+ case 0x4331:
|
|
+ /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
|
|
+ break;
|
|
+ case 43224:
|
|
+ if (bus->chipinfo.rev == 0) {
|
|
+ pr_err("Workarounds for 43224 rev 0 not fully "
|
|
+ "implemented\n");
|
|
+ bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
|
|
+ } else {
|
|
+ bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
|
|
+ }
|
|
+ break;
|
|
+ case 43225:
|
|
+ break;
|
|
+ default:
|
|
+ pr_err("Workarounds unknown for device 0x%04X\n",
|
|
+ bus->chipinfo.id);
|
|
+ }
|
|
+}
|
|
+
|
|
+void bcma_pmu_init(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ u32 pmucap;
|
|
+
|
|
+ pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
|
|
+ cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
|
|
+
|
|
+ pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
|
|
+ pmucap);
|
|
+
|
|
+ if (cc->pmu.rev == 1)
|
|
+ bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
|
|
+ ~BCMA_CC_PMU_CTL_NOILPONW);
|
|
+ else
|
|
+ bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
|
|
+ BCMA_CC_PMU_CTL_NOILPONW);
|
|
+
|
|
+ if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
|
|
+ pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
|
|
+
|
|
+ bcma_pmu_pll_init(cc);
|
|
+ bcma_pmu_resources_init(cc);
|
|
+ bcma_pmu_swreg_init(cc);
|
|
+ bcma_pmu_workarounds(cc);
|
|
+}
|
|
+
|
|
+u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case 0x4716:
|
|
+ case 0x4748:
|
|
+ case 47162:
|
|
+ case 0x4313:
|
|
+ case 0x5357:
|
|
+ case 0x4749:
|
|
+ case 53572:
|
|
+ /* always 20Mhz */
|
|
+ return 20000 * 1000;
|
|
+ case 0x5356:
|
|
+ case 0x5300:
|
|
+ /* always 25Mhz */
|
|
+ return 25000 * 1000;
|
|
+ default:
|
|
+ pr_warning("No ALP clock specified for %04X device, "
|
|
+ "pmu rev. %d, using default %d Hz\n",
|
|
+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
|
|
+ }
|
|
+ return BCMA_CC_PMU_ALP_CLOCK;
|
|
+}
|
|
+
|
|
+/* Find the output of the "m" pll divider given pll controls that start with
|
|
+ * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
|
|
+ */
|
|
+static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
|
+{
|
|
+ u32 tmp, div, ndiv, p1, p2, fc;
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
|
|
+
|
|
+ BUG_ON(!m || m > 4);
|
|
+
|
|
+ if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
|
|
+ /* Detect failure in clock setting */
|
|
+ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
|
|
+ if (tmp & 0x40000)
|
|
+ return 133 * 1000000;
|
|
+ }
|
|
+
|
|
+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
|
|
+ p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
|
|
+ p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
|
|
+
|
|
+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
|
|
+ div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
|
|
+ BCMA_CC_PPL_MDIV_MASK;
|
|
+
|
|
+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
|
|
+ ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
|
|
+
|
|
+ /* Do calculation in Mhz */
|
|
+ fc = bcma_pmu_alp_clock(cc) / 1000000;
|
|
+ fc = (p1 * ndiv * fc) / p2;
|
|
+
|
|
+ /* Return clock in Hertz */
|
|
+ return (fc / div) * 1000000;
|
|
+}
|
|
+
|
|
+/* query bus clock frequency for PMU-enabled chipcommon */
|
|
+u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case 0x4716:
|
|
+ case 0x4748:
|
|
+ case 47162:
|
|
+ return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ case 0x5356:
|
|
+ return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ case 0x5357:
|
|
+ case 0x4749:
|
|
+ return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ case 0x5300:
|
|
+ return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
|
|
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
|
+ case 53572:
|
|
+ return 75000000;
|
|
+ default:
|
|
+ pr_warning("No backplane clock specified for %04X device, "
|
|
+ "pmu rev. %d, using default %d Hz\n",
|
|
+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
|
|
+ }
|
|
+ return BCMA_CC_PMU_HT_CLOCK;
|
|
+}
|
|
+
|
|
+/* query cpu clock frequency for PMU-enabled chipcommon */
|
|
+u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
|
|
+{
|
|
+ struct bcma_bus *bus = cc->core->bus;
|
|
+
|
|
+ if (bus->chipinfo.id == 53572)
|
|
+ return 300000000;
|
|
+
|
|
+ if (cc->pmu.rev >= 5) {
|
|
+ u32 pll;
|
|
+ switch (bus->chipinfo.id) {
|
|
+ case 0x5356:
|
|
+ pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
|
|
+ break;
|
|
+ case 0x5357:
|
|
+ case 0x4749:
|
|
+ pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
|
|
+ break;
|
|
+ default:
|
|
+ pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ /* TODO: if (bus->chipinfo.id == 0x5300)
|
|
+ return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
|
|
+ return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
|
+ }
|
|
+
|
|
+ return bcma_pmu_get_clockcontrol(cc);
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/driver_pci.c
|
|
@@ -0,0 +1,237 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * PCI Core
|
|
+ *
|
|
+ * Copyright 2005, Broadcom Corporation
|
|
+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+#include <linux/bcma/bcma.h>
|
|
+
|
|
+/**************************************************
|
|
+ * R/W ops.
|
|
+ **************************************************/
|
|
+
|
|
+static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
|
|
+{
|
|
+ pcicore_write32(pc, 0x130, address);
|
|
+ pcicore_read32(pc, 0x130);
|
|
+ return pcicore_read32(pc, 0x134);
|
|
+}
|
|
+
|
|
+#if 0
|
|
+static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
|
|
+{
|
|
+ pcicore_write32(pc, 0x130, address);
|
|
+ pcicore_read32(pc, 0x130);
|
|
+ pcicore_write32(pc, 0x134, data);
|
|
+}
|
|
+#endif
|
|
+
|
|
+static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
|
|
+{
|
|
+ const u16 mdio_control = 0x128;
|
|
+ const u16 mdio_data = 0x12C;
|
|
+ u32 v;
|
|
+ int i;
|
|
+
|
|
+ v = (1 << 30); /* Start of Transaction */
|
|
+ v |= (1 << 28); /* Write Transaction */
|
|
+ v |= (1 << 17); /* Turnaround */
|
|
+ v |= (0x1F << 18);
|
|
+ v |= (phy << 4);
|
|
+ pcicore_write32(pc, mdio_data, v);
|
|
+
|
|
+ udelay(10);
|
|
+ for (i = 0; i < 200; i++) {
|
|
+ v = pcicore_read32(pc, mdio_control);
|
|
+ if (v & 0x100 /* Trans complete */)
|
|
+ break;
|
|
+ msleep(1);
|
|
+ }
|
|
+}
|
|
+
|
|
+static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
|
|
+{
|
|
+ const u16 mdio_control = 0x128;
|
|
+ const u16 mdio_data = 0x12C;
|
|
+ int max_retries = 10;
|
|
+ u16 ret = 0;
|
|
+ u32 v;
|
|
+ int i;
|
|
+
|
|
+ v = 0x80; /* Enable Preamble Sequence */
|
|
+ v |= 0x2; /* MDIO Clock Divisor */
|
|
+ pcicore_write32(pc, mdio_control, v);
|
|
+
|
|
+ if (pc->core->id.rev >= 10) {
|
|
+ max_retries = 200;
|
|
+ bcma_pcie_mdio_set_phy(pc, device);
|
|
+ }
|
|
+
|
|
+ v = (1 << 30); /* Start of Transaction */
|
|
+ v |= (1 << 29); /* Read Transaction */
|
|
+ v |= (1 << 17); /* Turnaround */
|
|
+ if (pc->core->id.rev < 10)
|
|
+ v |= (u32)device << 22;
|
|
+ v |= (u32)address << 18;
|
|
+ pcicore_write32(pc, mdio_data, v);
|
|
+ /* Wait for the device to complete the transaction */
|
|
+ udelay(10);
|
|
+ for (i = 0; i < max_retries; i++) {
|
|
+ v = pcicore_read32(pc, mdio_control);
|
|
+ if (v & 0x100 /* Trans complete */) {
|
|
+ udelay(10);
|
|
+ ret = pcicore_read32(pc, mdio_data);
|
|
+ break;
|
|
+ }
|
|
+ msleep(1);
|
|
+ }
|
|
+ pcicore_write32(pc, mdio_control, 0);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
|
|
+ u8 address, u16 data)
|
|
+{
|
|
+ const u16 mdio_control = 0x128;
|
|
+ const u16 mdio_data = 0x12C;
|
|
+ int max_retries = 10;
|
|
+ u32 v;
|
|
+ int i;
|
|
+
|
|
+ v = 0x80; /* Enable Preamble Sequence */
|
|
+ v |= 0x2; /* MDIO Clock Divisor */
|
|
+ pcicore_write32(pc, mdio_control, v);
|
|
+
|
|
+ if (pc->core->id.rev >= 10) {
|
|
+ max_retries = 200;
|
|
+ bcma_pcie_mdio_set_phy(pc, device);
|
|
+ }
|
|
+
|
|
+ v = (1 << 30); /* Start of Transaction */
|
|
+ v |= (1 << 28); /* Write Transaction */
|
|
+ v |= (1 << 17); /* Turnaround */
|
|
+ if (pc->core->id.rev < 10)
|
|
+ v |= (u32)device << 22;
|
|
+ v |= (u32)address << 18;
|
|
+ v |= data;
|
|
+ pcicore_write32(pc, mdio_data, v);
|
|
+ /* Wait for the device to complete the transaction */
|
|
+ udelay(10);
|
|
+ for (i = 0; i < max_retries; i++) {
|
|
+ v = pcicore_read32(pc, mdio_control);
|
|
+ if (v & 0x100 /* Trans complete */)
|
|
+ break;
|
|
+ msleep(1);
|
|
+ }
|
|
+ pcicore_write32(pc, mdio_control, 0);
|
|
+}
|
|
+
|
|
+/**************************************************
|
|
+ * Workarounds.
|
|
+ **************************************************/
|
|
+
|
|
+static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
|
|
+{
|
|
+ return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
|
|
+}
|
|
+
|
|
+static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
|
|
+{
|
|
+ const u8 serdes_pll_device = 0x1D;
|
|
+ const u8 serdes_rx_device = 0x1F;
|
|
+ u16 tmp;
|
|
+
|
|
+ bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
|
|
+ bcma_pcicore_polarity_workaround(pc));
|
|
+ tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
|
|
+ if (tmp & 0x4000)
|
|
+ bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
|
|
+}
|
|
+
|
|
+/**************************************************
|
|
+ * Init.
|
|
+ **************************************************/
|
|
+
|
|
+static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
|
|
+{
|
|
+ bcma_pcicore_serdes_workaround(pc);
|
|
+}
|
|
+
|
|
+static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
|
|
+{
|
|
+ struct bcma_bus *bus = pc->core->bus;
|
|
+ u16 chipid_top;
|
|
+
|
|
+ chipid_top = (bus->chipinfo.id & 0xFF00);
|
|
+ if (chipid_top != 0x4700 &&
|
|
+ chipid_top != 0x5300)
|
|
+ return false;
|
|
+
|
|
+#ifdef CONFIG_SSB_DRIVER_PCICORE
|
|
+ if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
|
|
+ return false;
|
|
+#endif /* CONFIG_SSB_DRIVER_PCICORE */
|
|
+
|
|
+#if 0
|
|
+ /* TODO: on BCMA we use address from EROM instead of magic formula */
|
|
+ u32 tmp;
|
|
+ return !mips_busprobe32(tmp, (bus->mmio +
|
|
+ (pc->core->core_index * BCMA_CORE_SIZE)));
|
|
+#endif
|
|
+
|
|
+ return true;
|
|
+}
|
|
+
|
|
+void bcma_core_pci_init(struct bcma_drv_pci *pc)
|
|
+{
|
|
+ if (pc->setup_done)
|
|
+ return;
|
|
+
|
|
+ if (bcma_core_pci_is_in_hostmode(pc)) {
|
|
+#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
|
|
+ bcma_core_pci_hostmode_init(pc);
|
|
+#else
|
|
+ pr_err("Driver compiled without support for hostmode PCI\n");
|
|
+#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
|
|
+ } else {
|
|
+ bcma_core_pci_clientmode_init(pc);
|
|
+ }
|
|
+
|
|
+ pc->setup_done = true;
|
|
+}
|
|
+
|
|
+int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
|
|
+ bool enable)
|
|
+{
|
|
+ struct pci_dev *pdev = pc->core->bus->host_pci;
|
|
+ u32 coremask, tmp;
|
|
+ int err = 0;
|
|
+
|
|
+ if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
|
|
+ /* This bcma device is not on a PCI host-bus. So the IRQs are
|
|
+ * not routed through the PCI core.
|
|
+ * So we must not enable routing through the PCI core. */
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
|
|
+ if (err)
|
|
+ goto out;
|
|
+
|
|
+ coremask = BIT(core->core_index) << 8;
|
|
+ if (enable)
|
|
+ tmp |= coremask;
|
|
+ else
|
|
+ tmp &= ~coremask;
|
|
+
|
|
+ err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
|
|
+
|
|
+out:
|
|
+ return err;
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/host_pci.c
|
|
@@ -0,0 +1,299 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * PCI Host
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+#include <linux/slab.h>
|
|
+#include <linux/bcma/bcma.h>
|
|
+#include <linux/pci.h>
|
|
+#include <linux/module.h>
|
|
+
|
|
+static void bcma_host_pci_switch_core(struct bcma_device *core)
|
|
+{
|
|
+ pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
|
|
+ core->addr);
|
|
+ pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
|
|
+ core->wrap);
|
|
+ core->bus->mapped_core = core;
|
|
+ pr_debug("Switched to core: 0x%X\n", core->id.id);
|
|
+}
|
|
+
|
|
+/* Provides access to the requested core. Returns base offset that has to be
|
|
+ * used. It makes use of fixed windows when possible. */
|
|
+static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
|
|
+{
|
|
+ switch (core->id.id) {
|
|
+ case BCMA_CORE_CHIPCOMMON:
|
|
+ return 3 * BCMA_CORE_SIZE;
|
|
+ case BCMA_CORE_PCIE:
|
|
+ return 2 * BCMA_CORE_SIZE;
|
|
+ }
|
|
+
|
|
+ if (core->bus->mapped_core != core)
|
|
+ bcma_host_pci_switch_core(core);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ offset += bcma_host_pci_provide_access_to_core(core);
|
|
+ return ioread8(core->bus->mmio + offset);
|
|
+}
|
|
+
|
|
+static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ offset += bcma_host_pci_provide_access_to_core(core);
|
|
+ return ioread16(core->bus->mmio + offset);
|
|
+}
|
|
+
|
|
+static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ offset += bcma_host_pci_provide_access_to_core(core);
|
|
+ return ioread32(core->bus->mmio + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
|
|
+ u8 value)
|
|
+{
|
|
+ offset += bcma_host_pci_provide_access_to_core(core);
|
|
+ iowrite8(value, core->bus->mmio + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
|
|
+ u16 value)
|
|
+{
|
|
+ offset += bcma_host_pci_provide_access_to_core(core);
|
|
+ iowrite16(value, core->bus->mmio + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
|
|
+ u32 value)
|
|
+{
|
|
+ offset += bcma_host_pci_provide_access_to_core(core);
|
|
+ iowrite32(value, core->bus->mmio + offset);
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_BCMA_BLOCKIO
|
|
+void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width)
|
|
+{
|
|
+ void __iomem *addr = core->bus->mmio + offset;
|
|
+ if (core->bus->mapped_core != core)
|
|
+ bcma_host_pci_switch_core(core);
|
|
+ switch (reg_width) {
|
|
+ case sizeof(u8):
|
|
+ ioread8_rep(addr, buffer, count);
|
|
+ break;
|
|
+ case sizeof(u16):
|
|
+ WARN_ON(count & 1);
|
|
+ ioread16_rep(addr, buffer, count >> 1);
|
|
+ break;
|
|
+ case sizeof(u32):
|
|
+ WARN_ON(count & 3);
|
|
+ ioread32_rep(addr, buffer, count >> 2);
|
|
+ break;
|
|
+ default:
|
|
+ WARN_ON(1);
|
|
+ }
|
|
+}
|
|
+
|
|
+void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width)
|
|
+{
|
|
+ void __iomem *addr = core->bus->mmio + offset;
|
|
+ if (core->bus->mapped_core != core)
|
|
+ bcma_host_pci_switch_core(core);
|
|
+ switch (reg_width) {
|
|
+ case sizeof(u8):
|
|
+ iowrite8_rep(addr, buffer, count);
|
|
+ break;
|
|
+ case sizeof(u16):
|
|
+ WARN_ON(count & 1);
|
|
+ iowrite16_rep(addr, buffer, count >> 1);
|
|
+ break;
|
|
+ case sizeof(u32):
|
|
+ WARN_ON(count & 3);
|
|
+ iowrite32_rep(addr, buffer, count >> 2);
|
|
+ break;
|
|
+ default:
|
|
+ WARN_ON(1);
|
|
+ }
|
|
+}
|
|
+#endif
|
|
+
|
|
+static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ if (core->bus->mapped_core != core)
|
|
+ bcma_host_pci_switch_core(core);
|
|
+ return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
|
|
+ u32 value)
|
|
+{
|
|
+ if (core->bus->mapped_core != core)
|
|
+ bcma_host_pci_switch_core(core);
|
|
+ iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
|
|
+}
|
|
+
|
|
+const struct bcma_host_ops bcma_host_pci_ops = {
|
|
+ .read8 = bcma_host_pci_read8,
|
|
+ .read16 = bcma_host_pci_read16,
|
|
+ .read32 = bcma_host_pci_read32,
|
|
+ .write8 = bcma_host_pci_write8,
|
|
+ .write16 = bcma_host_pci_write16,
|
|
+ .write32 = bcma_host_pci_write32,
|
|
+#ifdef CONFIG_BCMA_BLOCKIO
|
|
+ .block_read = bcma_host_pci_block_read,
|
|
+ .block_write = bcma_host_pci_block_write,
|
|
+#endif
|
|
+ .aread32 = bcma_host_pci_aread32,
|
|
+ .awrite32 = bcma_host_pci_awrite32,
|
|
+};
|
|
+
|
|
+static int bcma_host_pci_probe(struct pci_dev *dev,
|
|
+ const struct pci_device_id *id)
|
|
+{
|
|
+ struct bcma_bus *bus;
|
|
+ int err = -ENOMEM;
|
|
+ const char *name;
|
|
+ u32 val;
|
|
+
|
|
+ /* Alloc */
|
|
+ bus = kzalloc(sizeof(*bus), GFP_KERNEL);
|
|
+ if (!bus)
|
|
+ goto out;
|
|
+
|
|
+ /* Basic PCI configuration */
|
|
+ err = pci_enable_device(dev);
|
|
+ if (err)
|
|
+ goto err_kfree_bus;
|
|
+
|
|
+ name = dev_name(&dev->dev);
|
|
+ if (dev->driver && dev->driver->name)
|
|
+ name = dev->driver->name;
|
|
+ err = pci_request_regions(dev, name);
|
|
+ if (err)
|
|
+ goto err_pci_disable;
|
|
+ pci_set_master(dev);
|
|
+
|
|
+ /* Disable the RETRY_TIMEOUT register (0x41) to keep
|
|
+ * PCI Tx retries from interfering with C3 CPU state */
|
|
+ pci_read_config_dword(dev, 0x40, &val);
|
|
+ if ((val & 0x0000ff00) != 0)
|
|
+ pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
|
|
+
|
|
+ /* SSB needed additional powering up, do we have any AMBA PCI cards? */
|
|
+ if (!dev->is_pcie)
|
|
+ pr_err("PCI card detected, report problems.\n");
|
|
+
|
|
+ /* Map MMIO */
|
|
+ err = -ENOMEM;
|
|
+ bus->mmio = pci_iomap(dev, 0, ~0UL);
|
|
+ if (!bus->mmio)
|
|
+ goto err_pci_release_regions;
|
|
+
|
|
+ /* Host specific */
|
|
+ bus->host_pci = dev;
|
|
+ bus->hosttype = BCMA_HOSTTYPE_PCI;
|
|
+ bus->ops = &bcma_host_pci_ops;
|
|
+
|
|
+ /* Register */
|
|
+ err = bcma_bus_register(bus);
|
|
+ if (err)
|
|
+ goto err_pci_unmap_mmio;
|
|
+
|
|
+ pci_set_drvdata(dev, bus);
|
|
+
|
|
+out:
|
|
+ return err;
|
|
+
|
|
+err_pci_unmap_mmio:
|
|
+ pci_iounmap(dev, bus->mmio);
|
|
+err_pci_release_regions:
|
|
+ pci_release_regions(dev);
|
|
+err_pci_disable:
|
|
+ pci_disable_device(dev);
|
|
+err_kfree_bus:
|
|
+ kfree(bus);
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static void bcma_host_pci_remove(struct pci_dev *dev)
|
|
+{
|
|
+ struct bcma_bus *bus = pci_get_drvdata(dev);
|
|
+
|
|
+ bcma_bus_unregister(bus);
|
|
+ pci_iounmap(dev, bus->mmio);
|
|
+ pci_release_regions(dev);
|
|
+ pci_disable_device(dev);
|
|
+ kfree(bus);
|
|
+ pci_set_drvdata(dev, NULL);
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+static int bcma_host_pci_suspend(struct pci_dev *dev, pm_message_t state)
|
|
+{
|
|
+ /* Host specific */
|
|
+ pci_save_state(dev);
|
|
+ pci_disable_device(dev);
|
|
+ pci_set_power_state(dev, pci_choose_state(dev, state));
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcma_host_pci_resume(struct pci_dev *dev)
|
|
+{
|
|
+ struct bcma_bus *bus = pci_get_drvdata(dev);
|
|
+ int err;
|
|
+
|
|
+ /* Host specific */
|
|
+ pci_set_power_state(dev, 0);
|
|
+ err = pci_enable_device(dev);
|
|
+ if (err)
|
|
+ return err;
|
|
+ pci_restore_state(dev);
|
|
+
|
|
+ /* Bus specific */
|
|
+ err = bcma_bus_resume(bus);
|
|
+ if (err)
|
|
+ return err;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#else /* CONFIG_PM */
|
|
+# define bcma_host_pci_suspend NULL
|
|
+# define bcma_host_pci_resume NULL
|
|
+#endif /* CONFIG_PM */
|
|
+
|
|
+static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
|
|
+ { 0, },
|
|
+};
|
|
+MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
|
|
+
|
|
+static struct pci_driver bcma_pci_bridge_driver = {
|
|
+ .name = "bcma-pci-bridge",
|
|
+ .id_table = bcma_pci_bridge_tbl,
|
|
+ .probe = bcma_host_pci_probe,
|
|
+ .remove = bcma_host_pci_remove,
|
|
+ .suspend = bcma_host_pci_suspend,
|
|
+ .resume = bcma_host_pci_resume,
|
|
+};
|
|
+
|
|
+int __init bcma_host_pci_init(void)
|
|
+{
|
|
+ return pci_register_driver(&bcma_pci_bridge_driver);
|
|
+}
|
|
+
|
|
+void __exit bcma_host_pci_exit(void)
|
|
+{
|
|
+ pci_unregister_driver(&bcma_pci_bridge_driver);
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/main.c
|
|
@@ -0,0 +1,354 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * Bus subsystem
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+#include <linux/module.h>
|
|
+#include <linux/bcma/bcma.h>
|
|
+#include <linux/slab.h>
|
|
+
|
|
+MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
|
|
+MODULE_LICENSE("GPL");
|
|
+
|
|
+static int bcma_bus_match(struct device *dev, struct device_driver *drv);
|
|
+static int bcma_device_probe(struct device *dev);
|
|
+static int bcma_device_remove(struct device *dev);
|
|
+static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env);
|
|
+
|
|
+static ssize_t manuf_show(struct device *dev, struct device_attribute *attr, char *buf)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ return sprintf(buf, "0x%03X\n", core->id.manuf);
|
|
+}
|
|
+static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ return sprintf(buf, "0x%03X\n", core->id.id);
|
|
+}
|
|
+static ssize_t rev_show(struct device *dev, struct device_attribute *attr, char *buf)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ return sprintf(buf, "0x%02X\n", core->id.rev);
|
|
+}
|
|
+static ssize_t class_show(struct device *dev, struct device_attribute *attr, char *buf)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ return sprintf(buf, "0x%X\n", core->id.class);
|
|
+}
|
|
+static struct device_attribute bcma_device_attrs[] = {
|
|
+ __ATTR_RO(manuf),
|
|
+ __ATTR_RO(id),
|
|
+ __ATTR_RO(rev),
|
|
+ __ATTR_RO(class),
|
|
+ __ATTR_NULL,
|
|
+};
|
|
+
|
|
+static struct bus_type bcma_bus_type = {
|
|
+ .name = "bcma",
|
|
+ .match = bcma_bus_match,
|
|
+ .probe = bcma_device_probe,
|
|
+ .remove = bcma_device_remove,
|
|
+ .uevent = bcma_device_uevent,
|
|
+ .dev_attrs = bcma_device_attrs,
|
|
+};
|
|
+
|
|
+static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ if (core->id.id == coreid)
|
|
+ return core;
|
|
+ }
|
|
+ return NULL;
|
|
+}
|
|
+
|
|
+static void bcma_release_core_dev(struct device *dev)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ if (core->io_addr)
|
|
+ iounmap(core->io_addr);
|
|
+ if (core->io_wrap)
|
|
+ iounmap(core->io_wrap);
|
|
+ kfree(core);
|
|
+}
|
|
+
|
|
+static int bcma_register_cores(struct bcma_bus *bus)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+ int err, dev_id = 0;
|
|
+
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ /* We support that cores ourself */
|
|
+ switch (core->id.id) {
|
|
+ case BCMA_CORE_CHIPCOMMON:
|
|
+ case BCMA_CORE_PCI:
|
|
+ case BCMA_CORE_PCIE:
|
|
+ case BCMA_CORE_MIPS_74K:
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ core->dev.release = bcma_release_core_dev;
|
|
+ core->dev.bus = &bcma_bus_type;
|
|
+ dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
|
|
+
|
|
+ switch (bus->hosttype) {
|
|
+ case BCMA_HOSTTYPE_PCI:
|
|
+ core->dev.parent = &bus->host_pci->dev;
|
|
+ core->dma_dev = &bus->host_pci->dev;
|
|
+ core->irq = bus->host_pci->irq;
|
|
+ break;
|
|
+ case BCMA_HOSTTYPE_SOC:
|
|
+ core->dev.dma_mask = &core->dev.coherent_dma_mask;
|
|
+ core->dma_dev = &core->dev;
|
|
+ break;
|
|
+ case BCMA_HOSTTYPE_SDIO:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ err = device_register(&core->dev);
|
|
+ if (err) {
|
|
+ pr_err("Could not register dev for core 0x%03X\n",
|
|
+ core->id.id);
|
|
+ continue;
|
|
+ }
|
|
+ core->dev_registered = true;
|
|
+ dev_id++;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void bcma_unregister_cores(struct bcma_bus *bus)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ if (core->dev_registered)
|
|
+ device_unregister(&core->dev);
|
|
+ }
|
|
+}
|
|
+
|
|
+int bcma_bus_register(struct bcma_bus *bus)
|
|
+{
|
|
+ int err;
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ /* Scan for devices (cores) */
|
|
+ err = bcma_bus_scan(bus);
|
|
+ if (err) {
|
|
+ pr_err("Failed to scan: %d\n", err);
|
|
+ return -1;
|
|
+ }
|
|
+
|
|
+ /* Init CC core */
|
|
+ core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
|
|
+ if (core) {
|
|
+ bus->drv_cc.core = core;
|
|
+ bcma_core_chipcommon_init(&bus->drv_cc);
|
|
+ }
|
|
+
|
|
+ /* Init MIPS core */
|
|
+ core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
+ if (core) {
|
|
+ bus->drv_mips.core = core;
|
|
+ bcma_core_mips_init(&bus->drv_mips);
|
|
+ }
|
|
+
|
|
+ /* Init PCIE core */
|
|
+ core = bcma_find_core(bus, BCMA_CORE_PCIE);
|
|
+ if (core) {
|
|
+ bus->drv_pci.core = core;
|
|
+ bcma_core_pci_init(&bus->drv_pci);
|
|
+ }
|
|
+
|
|
+ /* Try to get SPROM */
|
|
+ err = bcma_sprom_get(bus);
|
|
+ if (err == -ENOENT) {
|
|
+ pr_err("No SPROM available\n");
|
|
+ } else if (err) {
|
|
+ pr_err("Failed to get SPROM: %d\n", err);
|
|
+ return -ENOENT;
|
|
+ }
|
|
+
|
|
+ /* Register found cores */
|
|
+ bcma_register_cores(bus);
|
|
+
|
|
+ pr_info("Bus registered\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void bcma_bus_unregister(struct bcma_bus *bus)
|
|
+{
|
|
+ bcma_unregister_cores(bus);
|
|
+}
|
|
+
|
|
+int __init bcma_bus_early_register(struct bcma_bus *bus,
|
|
+ struct bcma_device *core_cc,
|
|
+ struct bcma_device *core_mips)
|
|
+{
|
|
+ int err;
|
|
+ struct bcma_device *core;
|
|
+ struct bcma_device_id match;
|
|
+
|
|
+ bcma_init_bus(bus);
|
|
+
|
|
+ match.manuf = BCMA_MANUF_BCM;
|
|
+ match.id = BCMA_CORE_CHIPCOMMON;
|
|
+ match.class = BCMA_CL_SIM;
|
|
+ match.rev = BCMA_ANY_REV;
|
|
+
|
|
+ /* Scan for chip common core */
|
|
+ err = bcma_bus_scan_early(bus, &match, core_cc);
|
|
+ if (err) {
|
|
+ pr_err("Failed to scan for common core: %d\n", err);
|
|
+ return -1;
|
|
+ }
|
|
+
|
|
+ match.manuf = BCMA_MANUF_MIPS;
|
|
+ match.id = BCMA_CORE_MIPS_74K;
|
|
+ match.class = BCMA_CL_SIM;
|
|
+ match.rev = BCMA_ANY_REV;
|
|
+
|
|
+ /* Scan for mips core */
|
|
+ err = bcma_bus_scan_early(bus, &match, core_mips);
|
|
+ if (err) {
|
|
+ pr_err("Failed to scan for mips core: %d\n", err);
|
|
+ return -1;
|
|
+ }
|
|
+
|
|
+ /* Init CC core */
|
|
+ core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
|
|
+ if (core) {
|
|
+ bus->drv_cc.core = core;
|
|
+ bcma_core_chipcommon_init(&bus->drv_cc);
|
|
+ }
|
|
+
|
|
+ /* Init MIPS core */
|
|
+ core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
+ if (core) {
|
|
+ bus->drv_mips.core = core;
|
|
+ bcma_core_mips_init(&bus->drv_mips);
|
|
+ }
|
|
+
|
|
+ pr_info("Early bus registered\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+int bcma_bus_resume(struct bcma_bus *bus)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ /* Init CC core */
|
|
+ core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
|
|
+ if (core) {
|
|
+ bus->drv_cc.setup_done = false;
|
|
+ bcma_core_chipcommon_init(&bus->drv_cc);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+int __bcma_driver_register(struct bcma_driver *drv, struct module *owner)
|
|
+{
|
|
+ drv->drv.name = drv->name;
|
|
+ drv->drv.bus = &bcma_bus_type;
|
|
+ drv->drv.owner = owner;
|
|
+
|
|
+ return driver_register(&drv->drv);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(__bcma_driver_register);
|
|
+
|
|
+void bcma_driver_unregister(struct bcma_driver *drv)
|
|
+{
|
|
+ driver_unregister(&drv->drv);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(bcma_driver_unregister);
|
|
+
|
|
+static int bcma_bus_match(struct device *dev, struct device_driver *drv)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
|
|
+ const struct bcma_device_id *cid = &core->id;
|
|
+ const struct bcma_device_id *did;
|
|
+
|
|
+ for (did = adrv->id_table; did->manuf || did->id || did->rev; did++) {
|
|
+ if ((did->manuf == cid->manuf || did->manuf == BCMA_ANY_MANUF) &&
|
|
+ (did->id == cid->id || did->id == BCMA_ANY_ID) &&
|
|
+ (did->rev == cid->rev || did->rev == BCMA_ANY_REV) &&
|
|
+ (did->class == cid->class || did->class == BCMA_ANY_CLASS))
|
|
+ return 1;
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcma_device_probe(struct device *dev)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
|
|
+ drv);
|
|
+ int err = 0;
|
|
+
|
|
+ if (adrv->probe)
|
|
+ err = adrv->probe(core);
|
|
+
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static int bcma_device_remove(struct device *dev)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+ struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
|
|
+ drv);
|
|
+
|
|
+ if (adrv->remove)
|
|
+ adrv->remove(core);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env)
|
|
+{
|
|
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
+
|
|
+ return add_uevent_var(env,
|
|
+ "MODALIAS=bcma:m%04Xid%04Xrev%02Xcl%02X",
|
|
+ core->id.manuf, core->id.id,
|
|
+ core->id.rev, core->id.class);
|
|
+}
|
|
+
|
|
+static int __init bcma_modinit(void)
|
|
+{
|
|
+ int err;
|
|
+
|
|
+ err = bus_register(&bcma_bus_type);
|
|
+ if (err)
|
|
+ return err;
|
|
+
|
|
+#ifdef CONFIG_BCMA_HOST_PCI
|
|
+ err = bcma_host_pci_init();
|
|
+ if (err) {
|
|
+ pr_err("PCI host initialization failed\n");
|
|
+ err = 0;
|
|
+ }
|
|
+#endif
|
|
+
|
|
+ return err;
|
|
+}
|
|
+fs_initcall(bcma_modinit);
|
|
+
|
|
+static void __exit bcma_modexit(void)
|
|
+{
|
|
+#ifdef CONFIG_BCMA_HOST_PCI
|
|
+ bcma_host_pci_exit();
|
|
+#endif
|
|
+ bus_unregister(&bcma_bus_type);
|
|
+}
|
|
+module_exit(bcma_modexit)
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/scan.c
|
|
@@ -0,0 +1,486 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * Bus scanning
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "scan.h"
|
|
+#include "bcma_private.h"
|
|
+
|
|
+#include <linux/bcma/bcma.h>
|
|
+#include <linux/bcma/bcma_regs.h>
|
|
+#include <linux/pci.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/dma-mapping.h>
|
|
+#include <linux/slab.h>
|
|
+
|
|
+struct bcma_device_id_name {
|
|
+ u16 id;
|
|
+ const char *name;
|
|
+};
|
|
+struct bcma_device_id_name bcma_device_names[] = {
|
|
+ { BCMA_CORE_OOB_ROUTER, "OOB Router" },
|
|
+ { BCMA_CORE_INVALID, "Invalid" },
|
|
+ { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
|
|
+ { BCMA_CORE_ILINE20, "ILine 20" },
|
|
+ { BCMA_CORE_SRAM, "SRAM" },
|
|
+ { BCMA_CORE_SDRAM, "SDRAM" },
|
|
+ { BCMA_CORE_PCI, "PCI" },
|
|
+ { BCMA_CORE_MIPS, "MIPS" },
|
|
+ { BCMA_CORE_ETHERNET, "Fast Ethernet" },
|
|
+ { BCMA_CORE_V90, "V90" },
|
|
+ { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
|
|
+ { BCMA_CORE_ADSL, "ADSL" },
|
|
+ { BCMA_CORE_ILINE100, "ILine 100" },
|
|
+ { BCMA_CORE_IPSEC, "IPSEC" },
|
|
+ { BCMA_CORE_UTOPIA, "UTOPIA" },
|
|
+ { BCMA_CORE_PCMCIA, "PCMCIA" },
|
|
+ { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
|
|
+ { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
|
|
+ { BCMA_CORE_OFDM, "OFDM" },
|
|
+ { BCMA_CORE_EXTIF, "EXTIF" },
|
|
+ { BCMA_CORE_80211, "IEEE 802.11" },
|
|
+ { BCMA_CORE_PHY_A, "PHY A" },
|
|
+ { BCMA_CORE_PHY_B, "PHY B" },
|
|
+ { BCMA_CORE_PHY_G, "PHY G" },
|
|
+ { BCMA_CORE_MIPS_3302, "MIPS 3302" },
|
|
+ { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
|
|
+ { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
|
|
+ { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
|
|
+ { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
|
|
+ { BCMA_CORE_SDIO_HOST, "SDIO Host" },
|
|
+ { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
|
|
+ { BCMA_CORE_PARA_ATA, "PATA" },
|
|
+ { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
|
|
+ { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
|
|
+ { BCMA_CORE_PCIE, "PCIe" },
|
|
+ { BCMA_CORE_PHY_N, "PHY N" },
|
|
+ { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
|
|
+ { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
|
|
+ { BCMA_CORE_ARM_1176, "ARM 1176" },
|
|
+ { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
|
|
+ { BCMA_CORE_PHY_LP, "PHY LP" },
|
|
+ { BCMA_CORE_PMU, "PMU" },
|
|
+ { BCMA_CORE_PHY_SSN, "PHY SSN" },
|
|
+ { BCMA_CORE_SDIO_DEV, "SDIO Device" },
|
|
+ { BCMA_CORE_ARM_CM3, "ARM CM3" },
|
|
+ { BCMA_CORE_PHY_HT, "PHY HT" },
|
|
+ { BCMA_CORE_MIPS_74K, "MIPS 74K" },
|
|
+ { BCMA_CORE_MAC_GBIT, "GBit MAC" },
|
|
+ { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
|
|
+ { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
|
|
+ { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
|
|
+ { BCMA_CORE_SHARED_COMMON, "Common Shared" },
|
|
+ { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
|
|
+ { BCMA_CORE_SPI_HOST, "SPI Host" },
|
|
+ { BCMA_CORE_I2S, "I2S" },
|
|
+ { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
|
|
+ { BCMA_CORE_SHIM, "SHIM" },
|
|
+ { BCMA_CORE_DEFAULT, "Default" },
|
|
+};
|
|
+const char *bcma_device_name(struct bcma_device_id *id)
|
|
+{
|
|
+ int i;
|
|
+
|
|
+ if (id->manuf == BCMA_MANUF_BCM) {
|
|
+ for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
|
|
+ if (bcma_device_names[i].id == id->id)
|
|
+ return bcma_device_names[i].name;
|
|
+ }
|
|
+ }
|
|
+ return "UNKNOWN";
|
|
+}
|
|
+
|
|
+static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
|
|
+ u16 offset)
|
|
+{
|
|
+ return readl(bus->mmio + offset);
|
|
+}
|
|
+
|
|
+static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
|
|
+{
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_PCI)
|
|
+ pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
|
|
+ addr);
|
|
+}
|
|
+
|
|
+static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
|
|
+{
|
|
+ u32 ent = readl(*eromptr);
|
|
+ (*eromptr)++;
|
|
+ return ent;
|
|
+}
|
|
+
|
|
+static void bcma_erom_push_ent(u32 **eromptr)
|
|
+{
|
|
+ (*eromptr)--;
|
|
+}
|
|
+
|
|
+static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
|
|
+{
|
|
+ u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
+ if (!(ent & SCAN_ER_VALID))
|
|
+ return -ENOENT;
|
|
+ if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
|
|
+ return -ENOENT;
|
|
+ return ent;
|
|
+}
|
|
+
|
|
+static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
|
|
+{
|
|
+ u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
+ bcma_erom_push_ent(eromptr);
|
|
+ return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
|
|
+}
|
|
+
|
|
+static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
|
|
+{
|
|
+ u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
+ bcma_erom_push_ent(eromptr);
|
|
+ return (((ent & SCAN_ER_VALID)) &&
|
|
+ ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
|
|
+ ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
|
|
+}
|
|
+
|
|
+static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
|
|
+{
|
|
+ u32 ent;
|
|
+ while (1) {
|
|
+ ent = bcma_erom_get_ent(bus, eromptr);
|
|
+ if ((ent & SCAN_ER_VALID) &&
|
|
+ ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
|
|
+ break;
|
|
+ if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
|
|
+ break;
|
|
+ }
|
|
+ bcma_erom_push_ent(eromptr);
|
|
+}
|
|
+
|
|
+static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
|
|
+{
|
|
+ u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
+ if (!(ent & SCAN_ER_VALID))
|
|
+ return -ENOENT;
|
|
+ if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
|
|
+ return -ENOENT;
|
|
+ return ent;
|
|
+}
|
|
+
|
|
+static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
|
|
+ u32 type, u8 port)
|
|
+{
|
|
+ u32 addrl, addrh, sizel, sizeh = 0;
|
|
+ u32 size;
|
|
+
|
|
+ u32 ent = bcma_erom_get_ent(bus, eromptr);
|
|
+ if ((!(ent & SCAN_ER_VALID)) ||
|
|
+ ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
|
|
+ ((ent & SCAN_ADDR_TYPE) != type) ||
|
|
+ (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
|
|
+ bcma_erom_push_ent(eromptr);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ addrl = ent & SCAN_ADDR_ADDR;
|
|
+ if (ent & SCAN_ADDR_AG32)
|
|
+ addrh = bcma_erom_get_ent(bus, eromptr);
|
|
+ else
|
|
+ addrh = 0;
|
|
+
|
|
+ if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
|
|
+ size = bcma_erom_get_ent(bus, eromptr);
|
|
+ sizel = size & SCAN_SIZE_SZ;
|
|
+ if (size & SCAN_SIZE_SG32)
|
|
+ sizeh = bcma_erom_get_ent(bus, eromptr);
|
|
+ } else
|
|
+ sizel = SCAN_ADDR_SZ_BASE <<
|
|
+ ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
|
|
+
|
|
+ return addrl;
|
|
+}
|
|
+
|
|
+static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
|
|
+ u16 index)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ if (core->core_index == index)
|
|
+ return core;
|
|
+ }
|
|
+ return NULL;
|
|
+}
|
|
+
|
|
+static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
|
|
+ struct bcma_device_id *match, int core_num,
|
|
+ struct bcma_device *core)
|
|
+{
|
|
+ s32 tmp;
|
|
+ u8 i, j;
|
|
+ s32 cia, cib;
|
|
+ u8 ports[2], wrappers[2];
|
|
+
|
|
+ /* get CIs */
|
|
+ cia = bcma_erom_get_ci(bus, eromptr);
|
|
+ if (cia < 0) {
|
|
+ bcma_erom_push_ent(eromptr);
|
|
+ if (bcma_erom_is_end(bus, eromptr))
|
|
+ return -ESPIPE;
|
|
+ return -EILSEQ;
|
|
+ }
|
|
+ cib = bcma_erom_get_ci(bus, eromptr);
|
|
+ if (cib < 0)
|
|
+ return -EILSEQ;
|
|
+
|
|
+ /* parse CIs */
|
|
+ core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
|
|
+ core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
|
|
+ core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
|
|
+ ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
|
|
+ ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
|
|
+ wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
|
|
+ wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
|
|
+ core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
|
|
+
|
|
+ if (((core->id.manuf == BCMA_MANUF_ARM) &&
|
|
+ (core->id.id == 0xFFF)) ||
|
|
+ (ports[1] == 0)) {
|
|
+ bcma_erom_skip_component(bus, eromptr);
|
|
+ return -ENXIO;
|
|
+ }
|
|
+
|
|
+ /* check if component is a core at all */
|
|
+ if (wrappers[0] + wrappers[1] == 0) {
|
|
+ /* we could save addrl of the router
|
|
+ if (cid == BCMA_CORE_OOB_ROUTER)
|
|
+ */
|
|
+ bcma_erom_skip_component(bus, eromptr);
|
|
+ return -ENXIO;
|
|
+ }
|
|
+
|
|
+ if (bcma_erom_is_bridge(bus, eromptr)) {
|
|
+ bcma_erom_skip_component(bus, eromptr);
|
|
+ return -ENXIO;
|
|
+ }
|
|
+
|
|
+ if (bcma_find_core_by_index(bus, core_num)) {
|
|
+ bcma_erom_skip_component(bus, eromptr);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ if (match && ((match->manuf != BCMA_ANY_MANUF &&
|
|
+ match->manuf != core->id.manuf) ||
|
|
+ (match->id != BCMA_ANY_ID && match->id != core->id.id) ||
|
|
+ (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) ||
|
|
+ (match->class != BCMA_ANY_CLASS && match->class != core->id.class)
|
|
+ )) {
|
|
+ bcma_erom_skip_component(bus, eromptr);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ /* get & parse master ports */
|
|
+ for (i = 0; i < ports[0]; i++) {
|
|
+ s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
|
|
+ if (mst_port_d < 0)
|
|
+ return -EILSEQ;
|
|
+ }
|
|
+
|
|
+ /* get & parse slave ports */
|
|
+ for (i = 0; i < ports[1]; i++) {
|
|
+ for (j = 0; ; j++) {
|
|
+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
|
|
+ SCAN_ADDR_TYPE_SLAVE, i);
|
|
+ if (tmp < 0) {
|
|
+ /* no more entries for port _i_ */
|
|
+ /* pr_debug("erom: slave port %d "
|
|
+ * "has %d descriptors\n", i, j); */
|
|
+ break;
|
|
+ } else {
|
|
+ if (i == 0 && j == 0)
|
|
+ core->addr = tmp;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* get & parse master wrappers */
|
|
+ for (i = 0; i < wrappers[0]; i++) {
|
|
+ for (j = 0; ; j++) {
|
|
+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
|
|
+ SCAN_ADDR_TYPE_MWRAP, i);
|
|
+ if (tmp < 0) {
|
|
+ /* no more entries for port _i_ */
|
|
+ /* pr_debug("erom: master wrapper %d "
|
|
+ * "has %d descriptors\n", i, j); */
|
|
+ break;
|
|
+ } else {
|
|
+ if (i == 0 && j == 0)
|
|
+ core->wrap = tmp;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* get & parse slave wrappers */
|
|
+ for (i = 0; i < wrappers[1]; i++) {
|
|
+ u8 hack = (ports[1] == 1) ? 0 : 1;
|
|
+ for (j = 0; ; j++) {
|
|
+ tmp = bcma_erom_get_addr_desc(bus, eromptr,
|
|
+ SCAN_ADDR_TYPE_SWRAP, i + hack);
|
|
+ if (tmp < 0) {
|
|
+ /* no more entries for port _i_ */
|
|
+ /* pr_debug("erom: master wrapper %d "
|
|
+ * has %d descriptors\n", i, j); */
|
|
+ break;
|
|
+ } else {
|
|
+ if (wrappers[0] == 0 && !i && !j)
|
|
+ core->wrap = tmp;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
|
|
+ core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
|
|
+ if (!core->io_addr)
|
|
+ return -ENOMEM;
|
|
+ core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
|
|
+ if (!core->io_wrap) {
|
|
+ iounmap(core->io_addr);
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void bcma_init_bus(struct bcma_bus *bus)
|
|
+{
|
|
+ s32 tmp;
|
|
+
|
|
+ if (bus->init_done)
|
|
+ return;
|
|
+
|
|
+ INIT_LIST_HEAD(&bus->cores);
|
|
+ bus->nr_cores = 0;
|
|
+
|
|
+ bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
|
|
+
|
|
+ tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
|
|
+ bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
|
|
+ bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
|
|
+ bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
|
|
+ bus->init_done = true;
|
|
+}
|
|
+
|
|
+int bcma_bus_scan(struct bcma_bus *bus)
|
|
+{
|
|
+ u32 erombase;
|
|
+ u32 __iomem *eromptr, *eromend;
|
|
+
|
|
+ int err, core_num = 0;
|
|
+
|
|
+ bcma_init_bus(bus);
|
|
+
|
|
+ erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
|
|
+ eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
|
|
+ if (!eromptr)
|
|
+ return -ENOMEM;
|
|
+ } else {
|
|
+ eromptr = bus->mmio;
|
|
+ }
|
|
+
|
|
+ eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
|
|
+
|
|
+ bcma_scan_switch_core(bus, erombase);
|
|
+
|
|
+ while (eromptr < eromend) {
|
|
+ struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
|
|
+ if (!core)
|
|
+ return -ENOMEM;
|
|
+ INIT_LIST_HEAD(&core->list);
|
|
+ core->bus = bus;
|
|
+
|
|
+ err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
|
|
+ if (err == -ENODEV) {
|
|
+ core_num++;
|
|
+ continue;
|
|
+ } else if (err == -ENXIO)
|
|
+ continue;
|
|
+ else if (err == -ESPIPE)
|
|
+ break;
|
|
+ else if (err < 0)
|
|
+ return err;
|
|
+
|
|
+ core->core_index = core_num++;
|
|
+ bus->nr_cores++;
|
|
+
|
|
+ pr_info("Core %d found: %s "
|
|
+ "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
|
|
+ core->core_index, bcma_device_name(&core->id),
|
|
+ core->id.manuf, core->id.id, core->id.rev,
|
|
+ core->id.class);
|
|
+
|
|
+ list_add(&core->list, &bus->cores);
|
|
+ }
|
|
+
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
|
|
+ iounmap(eromptr);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int __init bcma_bus_scan_early(struct bcma_bus *bus,
|
|
+ struct bcma_device_id *match,
|
|
+ struct bcma_device *core)
|
|
+{
|
|
+ u32 erombase;
|
|
+ u32 __iomem *eromptr, *eromend;
|
|
+
|
|
+ int err = -ENODEV;
|
|
+ int core_num = 0;
|
|
+
|
|
+ erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
|
|
+ eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
|
|
+ if (!eromptr)
|
|
+ return -ENOMEM;
|
|
+ } else {
|
|
+ eromptr = bus->mmio;
|
|
+ }
|
|
+
|
|
+ eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
|
|
+
|
|
+ bcma_scan_switch_core(bus, erombase);
|
|
+
|
|
+ while (eromptr < eromend) {
|
|
+ memset(core, 0, sizeof(*core));
|
|
+ INIT_LIST_HEAD(&core->list);
|
|
+ core->bus = bus;
|
|
+
|
|
+ err = bcma_get_next_core(bus, &eromptr, match, core_num, core);
|
|
+ if (err == -ENODEV) {
|
|
+ core_num++;
|
|
+ continue;
|
|
+ } else if (err == -ENXIO)
|
|
+ continue;
|
|
+ else if (err == -ESPIPE)
|
|
+ break;
|
|
+ else if (err < 0)
|
|
+ return err;
|
|
+
|
|
+ core->core_index = core_num++;
|
|
+ bus->nr_cores++;
|
|
+ pr_info("Core %d found: %s "
|
|
+ "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
|
|
+ core->core_index, bcma_device_name(&core->id),
|
|
+ core->id.manuf, core->id.id, core->id.rev,
|
|
+ core->id.class);
|
|
+
|
|
+ list_add(&core->list, &bus->cores);
|
|
+ err = 0;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
|
|
+ iounmap(eromptr);
|
|
+
|
|
+ return err;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/scan.h
|
|
@@ -0,0 +1,56 @@
|
|
+#ifndef BCMA_SCAN_H_
|
|
+#define BCMA_SCAN_H_
|
|
+
|
|
+#define BCMA_ADDR_BASE 0x18000000
|
|
+#define BCMA_WRAP_BASE 0x18100000
|
|
+
|
|
+#define SCAN_ER_VALID 0x00000001
|
|
+#define SCAN_ER_TAGX 0x00000006 /* we have to ignore 0x8 bit when checking tag for SCAN_ER_TAG_ADDR */
|
|
+#define SCAN_ER_TAG 0x0000000E
|
|
+#define SCAN_ER_TAG_CI 0x00000000
|
|
+#define SCAN_ER_TAG_MP 0x00000002
|
|
+#define SCAN_ER_TAG_ADDR 0x00000004
|
|
+#define SCAN_ER_TAG_END 0x0000000E
|
|
+#define SCAN_ER_BAD 0xFFFFFFFF
|
|
+
|
|
+#define SCAN_CIA_CLASS 0x000000F0
|
|
+#define SCAN_CIA_CLASS_SHIFT 4
|
|
+#define SCAN_CIA_ID 0x000FFF00
|
|
+#define SCAN_CIA_ID_SHIFT 8
|
|
+#define SCAN_CIA_MANUF 0xFFF00000
|
|
+#define SCAN_CIA_MANUF_SHIFT 20
|
|
+
|
|
+#define SCAN_CIB_NMP 0x000001F0
|
|
+#define SCAN_CIB_NMP_SHIFT 4
|
|
+#define SCAN_CIB_NSP 0x00003E00
|
|
+#define SCAN_CIB_NSP_SHIFT 9
|
|
+#define SCAN_CIB_NMW 0x0007C000
|
|
+#define SCAN_CIB_NMW_SHIFT 14
|
|
+#define SCAN_CIB_NSW 0x00F80000
|
|
+#define SCAN_CIB_NSW_SHIFT 17
|
|
+#define SCAN_CIB_REV 0xFF000000
|
|
+#define SCAN_CIB_REV_SHIFT 24
|
|
+
|
|
+#define SCAN_ADDR_AG32 0x00000008
|
|
+#define SCAN_ADDR_SZ 0x00000030
|
|
+#define SCAN_ADDR_SZ_SHIFT 4
|
|
+#define SCAN_ADDR_SZ_4K 0x00000000
|
|
+#define SCAN_ADDR_SZ_8K 0x00000010
|
|
+#define SCAN_ADDR_SZ_16K 0x00000020
|
|
+#define SCAN_ADDR_SZ_SZD 0x00000030
|
|
+#define SCAN_ADDR_TYPE 0x000000C0
|
|
+#define SCAN_ADDR_TYPE_SLAVE 0x00000000
|
|
+#define SCAN_ADDR_TYPE_BRIDGE 0x00000040
|
|
+#define SCAN_ADDR_TYPE_SWRAP 0x00000080
|
|
+#define SCAN_ADDR_TYPE_MWRAP 0x000000C0
|
|
+#define SCAN_ADDR_PORT 0x00000F00
|
|
+#define SCAN_ADDR_PORT_SHIFT 8
|
|
+#define SCAN_ADDR_ADDR 0xFFFFF000
|
|
+
|
|
+#define SCAN_ADDR_SZ_BASE 0x00001000 /* 4KB */
|
|
+
|
|
+#define SCAN_SIZE_SZ_ALIGN 0x00000FFF
|
|
+#define SCAN_SIZE_SZ 0xFFFFF000
|
|
+#define SCAN_SIZE_SG32 0x00000008
|
|
+
|
|
+#endif /* BCMA_SCAN_H_ */
|
|
--- /dev/null
|
|
+++ b/include/linux/bcma/bcma.h
|
|
@@ -0,0 +1,298 @@
|
|
+#ifndef LINUX_BCMA_H_
|
|
+#define LINUX_BCMA_H_
|
|
+
|
|
+#include <linux/pci.h>
|
|
+#include <linux/mod_devicetable.h>
|
|
+
|
|
+#include <linux/bcma/bcma_driver_chipcommon.h>
|
|
+#include <linux/bcma/bcma_driver_pci.h>
|
|
+#include <linux/bcma/bcma_driver_mips.h>
|
|
+#include <linux/ssb/ssb.h> /* SPROM sharing */
|
|
+
|
|
+#include "bcma_regs.h"
|
|
+
|
|
+struct bcma_device;
|
|
+struct bcma_bus;
|
|
+
|
|
+enum bcma_hosttype {
|
|
+ BCMA_HOSTTYPE_PCI,
|
|
+ BCMA_HOSTTYPE_SDIO,
|
|
+ BCMA_HOSTTYPE_SOC,
|
|
+};
|
|
+
|
|
+struct bcma_chipinfo {
|
|
+ u16 id;
|
|
+ u8 rev;
|
|
+ u8 pkg;
|
|
+};
|
|
+
|
|
+enum bcma_clkmode {
|
|
+ BCMA_CLKMODE_FAST,
|
|
+ BCMA_CLKMODE_DYNAMIC,
|
|
+};
|
|
+
|
|
+struct bcma_host_ops {
|
|
+ u8 (*read8)(struct bcma_device *core, u16 offset);
|
|
+ u16 (*read16)(struct bcma_device *core, u16 offset);
|
|
+ u32 (*read32)(struct bcma_device *core, u16 offset);
|
|
+ void (*write8)(struct bcma_device *core, u16 offset, u8 value);
|
|
+ void (*write16)(struct bcma_device *core, u16 offset, u16 value);
|
|
+ void (*write32)(struct bcma_device *core, u16 offset, u32 value);
|
|
+#ifdef CONFIG_BCMA_BLOCKIO
|
|
+ void (*block_read)(struct bcma_device *core, void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width);
|
|
+ void (*block_write)(struct bcma_device *core, const void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width);
|
|
+#endif
|
|
+ /* Agent ops */
|
|
+ u32 (*aread32)(struct bcma_device *core, u16 offset);
|
|
+ void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
|
|
+};
|
|
+
|
|
+/* Core manufacturers */
|
|
+#define BCMA_MANUF_ARM 0x43B
|
|
+#define BCMA_MANUF_MIPS 0x4A7
|
|
+#define BCMA_MANUF_BCM 0x4BF
|
|
+
|
|
+/* Core class values. */
|
|
+#define BCMA_CL_SIM 0x0
|
|
+#define BCMA_CL_EROM 0x1
|
|
+#define BCMA_CL_CORESIGHT 0x9
|
|
+#define BCMA_CL_VERIF 0xB
|
|
+#define BCMA_CL_OPTIMO 0xD
|
|
+#define BCMA_CL_GEN 0xE
|
|
+#define BCMA_CL_PRIMECELL 0xF
|
|
+
|
|
+/* Core-ID values. */
|
|
+#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
|
|
+#define BCMA_CORE_INVALID 0x700
|
|
+#define BCMA_CORE_CHIPCOMMON 0x800
|
|
+#define BCMA_CORE_ILINE20 0x801
|
|
+#define BCMA_CORE_SRAM 0x802
|
|
+#define BCMA_CORE_SDRAM 0x803
|
|
+#define BCMA_CORE_PCI 0x804
|
|
+#define BCMA_CORE_MIPS 0x805
|
|
+#define BCMA_CORE_ETHERNET 0x806
|
|
+#define BCMA_CORE_V90 0x807
|
|
+#define BCMA_CORE_USB11_HOSTDEV 0x808
|
|
+#define BCMA_CORE_ADSL 0x809
|
|
+#define BCMA_CORE_ILINE100 0x80A
|
|
+#define BCMA_CORE_IPSEC 0x80B
|
|
+#define BCMA_CORE_UTOPIA 0x80C
|
|
+#define BCMA_CORE_PCMCIA 0x80D
|
|
+#define BCMA_CORE_INTERNAL_MEM 0x80E
|
|
+#define BCMA_CORE_MEMC_SDRAM 0x80F
|
|
+#define BCMA_CORE_OFDM 0x810
|
|
+#define BCMA_CORE_EXTIF 0x811
|
|
+#define BCMA_CORE_80211 0x812
|
|
+#define BCMA_CORE_PHY_A 0x813
|
|
+#define BCMA_CORE_PHY_B 0x814
|
|
+#define BCMA_CORE_PHY_G 0x815
|
|
+#define BCMA_CORE_MIPS_3302 0x816
|
|
+#define BCMA_CORE_USB11_HOST 0x817
|
|
+#define BCMA_CORE_USB11_DEV 0x818
|
|
+#define BCMA_CORE_USB20_HOST 0x819
|
|
+#define BCMA_CORE_USB20_DEV 0x81A
|
|
+#define BCMA_CORE_SDIO_HOST 0x81B
|
|
+#define BCMA_CORE_ROBOSWITCH 0x81C
|
|
+#define BCMA_CORE_PARA_ATA 0x81D
|
|
+#define BCMA_CORE_SATA_XORDMA 0x81E
|
|
+#define BCMA_CORE_ETHERNET_GBIT 0x81F
|
|
+#define BCMA_CORE_PCIE 0x820
|
|
+#define BCMA_CORE_PHY_N 0x821
|
|
+#define BCMA_CORE_SRAM_CTL 0x822
|
|
+#define BCMA_CORE_MINI_MACPHY 0x823
|
|
+#define BCMA_CORE_ARM_1176 0x824
|
|
+#define BCMA_CORE_ARM_7TDMI 0x825
|
|
+#define BCMA_CORE_PHY_LP 0x826
|
|
+#define BCMA_CORE_PMU 0x827
|
|
+#define BCMA_CORE_PHY_SSN 0x828
|
|
+#define BCMA_CORE_SDIO_DEV 0x829
|
|
+#define BCMA_CORE_ARM_CM3 0x82A
|
|
+#define BCMA_CORE_PHY_HT 0x82B
|
|
+#define BCMA_CORE_MIPS_74K 0x82C
|
|
+#define BCMA_CORE_MAC_GBIT 0x82D
|
|
+#define BCMA_CORE_DDR12_MEM_CTL 0x82E
|
|
+#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
|
|
+#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
|
|
+#define BCMA_CORE_SHARED_COMMON 0x831
|
|
+#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
|
|
+#define BCMA_CORE_SPI_HOST 0x833
|
|
+#define BCMA_CORE_I2S 0x834
|
|
+#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
|
|
+#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
|
|
+#define BCMA_CORE_DEFAULT 0xFFF
|
|
+
|
|
+#define BCMA_MAX_NR_CORES 16
|
|
+
|
|
+struct bcma_device {
|
|
+ struct bcma_bus *bus;
|
|
+ struct bcma_device_id id;
|
|
+
|
|
+ struct device dev;
|
|
+ struct device *dma_dev;
|
|
+
|
|
+ unsigned int irq;
|
|
+ bool dev_registered;
|
|
+
|
|
+ u8 core_index;
|
|
+
|
|
+ u32 addr;
|
|
+ u32 wrap;
|
|
+
|
|
+ void __iomem *io_addr;
|
|
+ void __iomem *io_wrap;
|
|
+
|
|
+ void *drvdata;
|
|
+ struct list_head list;
|
|
+};
|
|
+
|
|
+static inline void *bcma_get_drvdata(struct bcma_device *core)
|
|
+{
|
|
+ return core->drvdata;
|
|
+}
|
|
+static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
|
|
+{
|
|
+ core->drvdata = drvdata;
|
|
+}
|
|
+
|
|
+struct bcma_driver {
|
|
+ const char *name;
|
|
+ const struct bcma_device_id *id_table;
|
|
+
|
|
+ int (*probe)(struct bcma_device *dev);
|
|
+ void (*remove)(struct bcma_device *dev);
|
|
+ int (*suspend)(struct bcma_device *dev, pm_message_t state);
|
|
+ int (*resume)(struct bcma_device *dev);
|
|
+ void (*shutdown)(struct bcma_device *dev);
|
|
+
|
|
+ struct device_driver drv;
|
|
+};
|
|
+extern
|
|
+int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
|
|
+#define bcma_driver_register(drv) \
|
|
+ __bcma_driver_register(drv, THIS_MODULE)
|
|
+
|
|
+extern void bcma_driver_unregister(struct bcma_driver *drv);
|
|
+
|
|
+struct bcma_bus {
|
|
+ /* The MMIO area. */
|
|
+ void __iomem *mmio;
|
|
+
|
|
+ const struct bcma_host_ops *ops;
|
|
+
|
|
+ enum bcma_hosttype hosttype;
|
|
+ union {
|
|
+ /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
|
|
+ struct pci_dev *host_pci;
|
|
+ /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
|
|
+ struct sdio_func *host_sdio;
|
|
+ };
|
|
+
|
|
+ struct bcma_chipinfo chipinfo;
|
|
+
|
|
+ struct bcma_device *mapped_core;
|
|
+ struct list_head cores;
|
|
+ u8 nr_cores;
|
|
+ u8 init_done:1;
|
|
+
|
|
+ struct bcma_drv_cc drv_cc;
|
|
+ struct bcma_drv_pci drv_pci;
|
|
+ struct bcma_drv_mips drv_mips;
|
|
+
|
|
+ /* We decided to share SPROM struct with SSB as long as we do not need
|
|
+ * any hacks for BCMA. This simplifies drivers code. */
|
|
+ struct ssb_sprom sprom;
|
|
+};
|
|
+
|
|
+static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return core->bus->ops->read8(core, offset);
|
|
+}
|
|
+static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return core->bus->ops->read16(core, offset);
|
|
+}
|
|
+static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return core->bus->ops->read32(core, offset);
|
|
+}
|
|
+static inline
|
|
+void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
|
|
+{
|
|
+ core->bus->ops->write8(core, offset, value);
|
|
+}
|
|
+static inline
|
|
+void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
|
|
+{
|
|
+ core->bus->ops->write16(core, offset, value);
|
|
+}
|
|
+static inline
|
|
+void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
|
|
+{
|
|
+ core->bus->ops->write32(core, offset, value);
|
|
+}
|
|
+#ifdef CONFIG_BCMA_BLOCKIO
|
|
+static inline void bcma_block_read(struct bcma_device *core, void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width)
|
|
+{
|
|
+ core->bus->ops->block_read(core, buffer, count, offset, reg_width);
|
|
+}
|
|
+static inline void bcma_block_write(struct bcma_device *core,
|
|
+ const void *buffer, size_t count,
|
|
+ u16 offset, u8 reg_width)
|
|
+{
|
|
+ core->bus->ops->block_write(core, buffer, count, offset, reg_width);
|
|
+}
|
|
+#endif
|
|
+static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return core->bus->ops->aread32(core, offset);
|
|
+}
|
|
+static inline
|
|
+void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
|
|
+{
|
|
+ core->bus->ops->awrite32(core, offset, value);
|
|
+}
|
|
+
|
|
+static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
|
|
+{
|
|
+ bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
|
|
+}
|
|
+static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
|
|
+{
|
|
+ bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
|
|
+}
|
|
+static inline void bcma_maskset32(struct bcma_device *cc,
|
|
+ u16 offset, u32 mask, u32 set)
|
|
+{
|
|
+ bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
|
|
+}
|
|
+static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
|
|
+{
|
|
+ bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
|
|
+}
|
|
+static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
|
|
+{
|
|
+ bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
|
|
+}
|
|
+static inline void bcma_maskset16(struct bcma_device *cc,
|
|
+ u16 offset, u16 mask, u16 set)
|
|
+{
|
|
+ bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
|
|
+}
|
|
+
|
|
+extern bool bcma_core_is_enabled(struct bcma_device *core);
|
|
+extern void bcma_core_disable(struct bcma_device *core, u32 flags);
|
|
+extern int bcma_core_enable(struct bcma_device *core, u32 flags);
|
|
+extern void bcma_core_set_clockmode(struct bcma_device *core,
|
|
+ enum bcma_clkmode clkmode);
|
|
+extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
|
|
+ bool on);
|
|
+#define BCMA_DMA_TRANSLATION_MASK 0xC0000000
|
|
+#define BCMA_DMA_TRANSLATION_NONE 0x00000000
|
|
+#define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
|
|
+#define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */
|
|
+extern u32 bcma_core_dma_translation(struct bcma_device *core);
|
|
+
|
|
+#endif /* LINUX_BCMA_H_ */
|
|
--- /dev/null
|
|
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
|
@@ -0,0 +1,391 @@
|
|
+#ifndef LINUX_BCMA_DRIVER_CC_H_
|
|
+#define LINUX_BCMA_DRIVER_CC_H_
|
|
+
|
|
+/** ChipCommon core registers. **/
|
|
+#define BCMA_CC_ID 0x0000
|
|
+#define BCMA_CC_ID_ID 0x0000FFFF
|
|
+#define BCMA_CC_ID_ID_SHIFT 0
|
|
+#define BCMA_CC_ID_REV 0x000F0000
|
|
+#define BCMA_CC_ID_REV_SHIFT 16
|
|
+#define BCMA_CC_ID_PKG 0x00F00000
|
|
+#define BCMA_CC_ID_PKG_SHIFT 20
|
|
+#define BCMA_CC_ID_NRCORES 0x0F000000
|
|
+#define BCMA_CC_ID_NRCORES_SHIFT 24
|
|
+#define BCMA_CC_ID_TYPE 0xF0000000
|
|
+#define BCMA_CC_ID_TYPE_SHIFT 28
|
|
+#define BCMA_CC_CAP 0x0004 /* Capabilities */
|
|
+#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
|
|
+#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
|
|
+#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
|
|
+#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
|
|
+#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
|
|
+#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
|
|
+#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
|
|
+#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
|
|
+#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
|
|
+#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
|
|
+#define BCMA_CC_FLASHT_NFLASH 0x00000200
|
|
+#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
|
|
+#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
|
|
+#define BCMA_PLLTYPE_NONE 0x00000000
|
|
+#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
|
|
+#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
|
|
+#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
|
|
+#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
|
|
+#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
|
|
+#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
|
|
+#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
|
|
+#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
|
|
+#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
|
|
+#define BCMA_CC_CAP_OTPS_SHIFT 19
|
|
+#define BCMA_CC_CAP_OTPS_BASE 5
|
|
+#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
|
|
+#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
|
|
+#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
|
|
+#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
|
|
+#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
|
|
+#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
|
|
+#define BCMA_CC_CORECTL 0x0008
|
|
+#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
|
|
+#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
|
|
+#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
|
|
+#define BCMA_CC_BIST 0x000C
|
|
+#define BCMA_CC_OTPS 0x0010 /* OTP status */
|
|
+#define BCMA_CC_OTPS_PROGFAIL 0x80000000
|
|
+#define BCMA_CC_OTPS_PROTECT 0x00000007
|
|
+#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
|
|
+#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
|
|
+#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
|
|
+#define BCMA_CC_OTPC 0x0014 /* OTP control */
|
|
+#define BCMA_CC_OTPC_RECWAIT 0xFF000000
|
|
+#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
|
|
+#define BCMA_CC_OTPC_PRW_SHIFT 8
|
|
+#define BCMA_CC_OTPC_MAXFAIL 0x00000038
|
|
+#define BCMA_CC_OTPC_VSEL 0x00000006
|
|
+#define BCMA_CC_OTPC_SELVL 0x00000001
|
|
+#define BCMA_CC_OTPP 0x0018 /* OTP prog */
|
|
+#define BCMA_CC_OTPP_COL 0x000000FF
|
|
+#define BCMA_CC_OTPP_ROW 0x0000FF00
|
|
+#define BCMA_CC_OTPP_ROW_SHIFT 8
|
|
+#define BCMA_CC_OTPP_READERR 0x10000000
|
|
+#define BCMA_CC_OTPP_VALUE 0x20000000
|
|
+#define BCMA_CC_OTPP_READ 0x40000000
|
|
+#define BCMA_CC_OTPP_START 0x80000000
|
|
+#define BCMA_CC_OTPP_BUSY 0x80000000
|
|
+#define BCMA_CC_IRQSTAT 0x0020
|
|
+#define BCMA_CC_IRQMASK 0x0024
|
|
+#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
|
|
+#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
|
|
+#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
|
|
+#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
|
|
+#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
|
|
+#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
|
|
+#define BCMA_CC_JCMD_START 0x80000000
|
|
+#define BCMA_CC_JCMD_BUSY 0x80000000
|
|
+#define BCMA_CC_JCMD_PAUSE 0x40000000
|
|
+#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
|
|
+#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
|
|
+#define BCMA_CC_JCMD0_ACC_DR 0x00001000
|
|
+#define BCMA_CC_JCMD0_ACC_IR 0x00002000
|
|
+#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
|
|
+#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
|
|
+#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
|
|
+#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
|
|
+#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
|
|
+#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
|
|
+#define BCMA_CC_JCMD_ACC_DR 0x00010000
|
|
+#define BCMA_CC_JCMD_ACC_IR 0x00020000
|
|
+#define BCMA_CC_JCMD_ACC_RESET 0x00030000
|
|
+#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
|
|
+#define BCMA_CC_JCMD_ACC_PDR 0x00050000
|
|
+#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
|
|
+#define BCMA_CC_JCMD_IRW_SHIFT 8
|
|
+#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
|
|
+#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
|
|
+#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
|
|
+#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
|
|
+#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
|
|
+#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
|
|
+#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
|
|
+#define BCMA_CC_FLASHCTL 0x0040
|
|
+#define BCMA_CC_FLASHCTL_START 0x80000000
|
|
+#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
|
|
+#define BCMA_CC_FLASHADDR 0x0044
|
|
+#define BCMA_CC_FLASHDATA 0x0048
|
|
+#define BCMA_CC_BCAST_ADDR 0x0050
|
|
+#define BCMA_CC_BCAST_DATA 0x0054
|
|
+#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
|
|
+#define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
|
|
+#define BCMA_CC_GPIOIN 0x0060
|
|
+#define BCMA_CC_GPIOOUT 0x0064
|
|
+#define BCMA_CC_GPIOOUTEN 0x0068
|
|
+#define BCMA_CC_GPIOCTL 0x006C
|
|
+#define BCMA_CC_GPIOPOL 0x0070
|
|
+#define BCMA_CC_GPIOIRQ 0x0074
|
|
+#define BCMA_CC_WATCHDOG 0x0080
|
|
+#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
|
|
+#define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
|
|
+#define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
|
|
+#define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
|
|
+#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
|
|
+#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
|
|
+#define BCMA_CC_CLOCK_N 0x0090
|
|
+#define BCMA_CC_CLOCK_SB 0x0094
|
|
+#define BCMA_CC_CLOCK_PCI 0x0098
|
|
+#define BCMA_CC_CLOCK_M2 0x009C
|
|
+#define BCMA_CC_CLOCK_MIPS 0x00A0
|
|
+#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
|
|
+#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
|
|
+#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
|
|
+#define BCMA_CC_CLKDIV_OTP 0x000F0000
|
|
+#define BCMA_CC_CLKDIV_OTP_SHIFT 16
|
|
+#define BCMA_CC_CLKDIV_JTAG 0x00000F00
|
|
+#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
|
|
+#define BCMA_CC_CLKDIV_UART 0x000000FF
|
|
+#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
|
|
+#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
|
|
+#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
|
|
+#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
|
|
+#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
|
|
+#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
|
|
+#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
|
|
+#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
|
|
+#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
|
|
+#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
|
|
+#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
|
|
+#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
|
|
+#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
|
|
+#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
|
|
+#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
|
|
+#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
|
|
+#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
|
|
+#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
|
|
+#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
|
|
+#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
|
|
+#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
|
|
+#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
|
|
+#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
|
|
+#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
|
|
+#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
|
|
+#define BCMA_CC_EROM 0x00FC
|
|
+#define BCMA_CC_PCMCIA_CFG 0x0100
|
|
+#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
|
|
+#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
|
|
+#define BCMA_CC_PCMCIA_IOWAIT 0x010C
|
|
+#define BCMA_CC_IDE_CFG 0x0110
|
|
+#define BCMA_CC_IDE_MEMWAIT 0x0114
|
|
+#define BCMA_CC_IDE_ATTRWAIT 0x0118
|
|
+#define BCMA_CC_IDE_IOWAIT 0x011C
|
|
+#define BCMA_CC_PROG_CFG 0x0120
|
|
+#define BCMA_CC_PROG_WAITCNT 0x0124
|
|
+#define BCMA_CC_FLASH_CFG 0x0128
|
|
+#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
|
|
+#define BCMA_CC_FLASH_WAITCNT 0x012C
|
|
+/* 0x1E0 is defined as shared BCMA_CLKCTLST */
|
|
+#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
|
|
+#define BCMA_CC_UART0_DATA 0x0300
|
|
+#define BCMA_CC_UART0_IMR 0x0304
|
|
+#define BCMA_CC_UART0_FCR 0x0308
|
|
+#define BCMA_CC_UART0_LCR 0x030C
|
|
+#define BCMA_CC_UART0_MCR 0x0310
|
|
+#define BCMA_CC_UART0_LSR 0x0314
|
|
+#define BCMA_CC_UART0_MSR 0x0318
|
|
+#define BCMA_CC_UART0_SCRATCH 0x031C
|
|
+#define BCMA_CC_UART1_DATA 0x0400
|
|
+#define BCMA_CC_UART1_IMR 0x0404
|
|
+#define BCMA_CC_UART1_FCR 0x0408
|
|
+#define BCMA_CC_UART1_LCR 0x040C
|
|
+#define BCMA_CC_UART1_MCR 0x0410
|
|
+#define BCMA_CC_UART1_LSR 0x0414
|
|
+#define BCMA_CC_UART1_MSR 0x0418
|
|
+#define BCMA_CC_UART1_SCRATCH 0x041C
|
|
+/* PMU registers (rev >= 20) */
|
|
+#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
|
|
+#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
|
|
+#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
|
|
+#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
|
|
+#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
|
|
+#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
|
|
+#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
|
|
+#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
|
|
+#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
|
|
+#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
|
|
+#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
|
|
+#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
|
|
+#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
|
|
+#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
|
|
+#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
|
|
+#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
|
|
+#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
|
|
+#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
|
|
+#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
|
|
+#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
|
|
+#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
|
|
+#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
|
|
+#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
|
|
+#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
|
|
+#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
|
|
+#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
|
|
+#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
|
|
+#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
|
|
+#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
|
|
+#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
|
|
+#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
|
|
+#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
|
|
+#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
|
|
+#define BCMA_CC_CHIPCTL_ADDR 0x0650
|
|
+#define BCMA_CC_CHIPCTL_DATA 0x0654
|
|
+#define BCMA_CC_REGCTL_ADDR 0x0658
|
|
+#define BCMA_CC_REGCTL_DATA 0x065C
|
|
+#define BCMA_CC_PLLCTL_ADDR 0x0660
|
|
+#define BCMA_CC_PLLCTL_DATA 0x0664
|
|
+#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
|
|
+#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
|
|
+
|
|
+/* Divider allocation in 4716/47162/5356 */
|
|
+#define BCMA_CC_PMU5_MAINPLL_CPU 1
|
|
+#define BCMA_CC_PMU5_MAINPLL_MEM 2
|
|
+#define BCMA_CC_PMU5_MAINPLL_SSB 3
|
|
+
|
|
+/* PLL usage in 4716/47162 */
|
|
+#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
|
|
+
|
|
+/* PLL usage in 5356/5357 */
|
|
+#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
|
|
+#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
|
|
+
|
|
+/* 4706 PMU */
|
|
+#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
|
|
+
|
|
+/* ALP clock on pre-PMU chips */
|
|
+#define BCMA_CC_PMU_ALP_CLOCK 20000000
|
|
+/* HT clock for systems with PMU-enabled chipcommon */
|
|
+#define BCMA_CC_PMU_HT_CLOCK 80000000
|
|
+
|
|
+/* PMU rev 5 (& 6) */
|
|
+#define BCMA_CC_PPL_P1P2_OFF 0
|
|
+#define BCMA_CC_PPL_P1_MASK 0x0f000000
|
|
+#define BCMA_CC_PPL_P1_SHIFT 24
|
|
+#define BCMA_CC_PPL_P2_MASK 0x00f00000
|
|
+#define BCMA_CC_PPL_P2_SHIFT 20
|
|
+#define BCMA_CC_PPL_M14_OFF 1
|
|
+#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
|
|
+#define BCMA_CC_PPL_MDIV_WIDTH 8
|
|
+#define BCMA_CC_PPL_NM5_OFF 2
|
|
+#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
|
|
+#define BCMA_CC_PPL_NDIV_SHIFT 20
|
|
+#define BCMA_CC_PPL_FMAB_OFF 3
|
|
+#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
|
|
+#define BCMA_CC_PPL_MRAT_SHIFT 28
|
|
+#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
|
|
+#define BCMA_CC_PPL_ABRAT_SHIFT 27
|
|
+#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
|
|
+#define BCMA_CC_PPL_PLLCTL_OFF 4
|
|
+#define BCMA_CC_PPL_PCHI_OFF 5
|
|
+#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
|
|
+
|
|
+/* BCM4331 ChipControl numbers. */
|
|
+#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
|
|
+#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
|
|
+#define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
|
|
+#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
|
|
+#define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
|
|
+#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
|
|
+#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
|
|
+#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
|
|
+#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
|
|
+#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
|
|
+#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
|
|
+#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
|
|
+#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
|
|
+#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
|
|
+
|
|
+/* Data for the PMU, if available.
|
|
+ * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
|
|
+ */
|
|
+struct bcma_chipcommon_pmu {
|
|
+ u8 rev; /* PMU revision */
|
|
+ u32 crystalfreq; /* The active crystal frequency (in kHz) */
|
|
+};
|
|
+
|
|
+#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
+struct bcma_pflash {
|
|
+ u8 buswidth;
|
|
+ u32 window;
|
|
+ u32 window_size;
|
|
+};
|
|
+
|
|
+struct bcma_serial_port {
|
|
+ void *regs;
|
|
+ unsigned long clockspeed;
|
|
+ unsigned int irq;
|
|
+ unsigned int baud_base;
|
|
+ unsigned int reg_shift;
|
|
+};
|
|
+#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
|
+
|
|
+struct bcma_drv_cc {
|
|
+ struct bcma_device *core;
|
|
+ u32 status;
|
|
+ u32 capabilities;
|
|
+ u32 capabilities_ext;
|
|
+ u8 setup_done:1;
|
|
+ /* Fast Powerup Delay constant */
|
|
+ u16 fast_pwrup_delay;
|
|
+ struct bcma_chipcommon_pmu pmu;
|
|
+#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
+ struct bcma_pflash pflash;
|
|
+
|
|
+ int nr_serial_ports;
|
|
+ struct bcma_serial_port serial_ports[4];
|
|
+#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
|
+};
|
|
+
|
|
+/* Register access */
|
|
+#define bcma_cc_read32(cc, offset) \
|
|
+ bcma_read32((cc)->core, offset)
|
|
+#define bcma_cc_write32(cc, offset, val) \
|
|
+ bcma_write32((cc)->core, offset, val)
|
|
+
|
|
+#define bcma_cc_mask32(cc, offset, mask) \
|
|
+ bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
|
|
+#define bcma_cc_set32(cc, offset, set) \
|
|
+ bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
|
|
+#define bcma_cc_maskset32(cc, offset, mask, set) \
|
|
+ bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
|
|
+
|
|
+extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
|
|
+
|
|
+extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
|
|
+extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
|
|
+
|
|
+void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
|
|
+
|
|
+extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
|
|
+ u32 ticks);
|
|
+
|
|
+void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
|
+
|
|
+u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
|
|
+
|
|
+/* Chipcommon GPIO pin access. */
|
|
+u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
|
|
+u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
|
+u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
|
+u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
|
+u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
|
+u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
|
+
|
|
+/* PMU support */
|
|
+extern void bcma_pmu_init(struct bcma_drv_cc *cc);
|
|
+
|
|
+extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
|
+ u32 value);
|
|
+extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
|
|
+ u32 mask, u32 set);
|
|
+extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
|
|
+ u32 offset, u32 mask, u32 set);
|
|
+extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
|
|
+ u32 offset, u32 mask, u32 set);
|
|
+
|
|
+#endif /* LINUX_BCMA_DRIVER_CC_H_ */
|
|
--- /dev/null
|
|
+++ b/include/linux/bcma/bcma_driver_pci.h
|
|
@@ -0,0 +1,91 @@
|
|
+#ifndef LINUX_BCMA_DRIVER_PCI_H_
|
|
+#define LINUX_BCMA_DRIVER_PCI_H_
|
|
+
|
|
+#include <linux/types.h>
|
|
+
|
|
+struct pci_dev;
|
|
+
|
|
+/** PCI core registers. **/
|
|
+#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
|
|
+#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
|
|
+#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
|
|
+#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
|
|
+#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
|
|
+#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
|
|
+#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
|
|
+#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
|
|
+#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
|
|
+#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
|
|
+#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
|
|
+#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
|
|
+#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
|
|
+#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */
|
|
+#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */
|
|
+#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */
|
|
+#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
|
|
+#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
|
|
+#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */
|
|
+#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */
|
|
+#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */
|
|
+#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */
|
|
+#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */
|
|
+#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */
|
|
+#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */
|
|
+#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */
|
|
+#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
|
|
+#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
|
|
+#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
|
|
+#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
|
|
+#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
|
|
+#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
|
|
+#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
|
|
+#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
|
|
+#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
|
|
+#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF
|
|
+#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
|
|
+#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
|
|
+#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
|
|
+#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
|
|
+#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
|
|
+#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
|
|
+#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000
|
|
+#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
|
|
+#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
|
|
+#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
|
|
+#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
|
|
+#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
|
|
+#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
|
|
+#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
|
|
+#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
|
|
+#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
|
|
+
|
|
+/* SBtoPCIx */
|
|
+#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
|
|
+#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001
|
|
+#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002
|
|
+#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003
|
|
+#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
|
|
+#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */
|
|
+#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
|
|
+#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
|
|
+#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */
|
|
+#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
|
|
+#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
|
|
+
|
|
+/* PCIcore specific boardflags */
|
|
+#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
|
|
+
|
|
+struct bcma_drv_pci {
|
|
+ struct bcma_device *core;
|
|
+ u8 setup_done:1;
|
|
+};
|
|
+
|
|
+/* Register access */
|
|
+#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
|
|
+#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
|
|
+
|
|
+extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
|
|
+extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
|
|
+ struct bcma_device *core, bool enable);
|
|
+
|
|
+#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
|
|
--- /dev/null
|
|
+++ b/include/linux/bcma/bcma_regs.h
|
|
@@ -0,0 +1,59 @@
|
|
+#ifndef LINUX_BCMA_REGS_H_
|
|
+#define LINUX_BCMA_REGS_H_
|
|
+
|
|
+/* Some single registers are shared between many cores */
|
|
+/* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
|
|
+#define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
|
|
+#define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
|
|
+#define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
|
|
+#define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
|
|
+#define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
|
|
+#define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
|
|
+#define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
|
|
+#define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
|
|
+#define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
|
|
+#define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
|
|
+#define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
|
|
+#define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
|
|
+#define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
|
|
+/* Is there any BCM4328 on BCMA bus? */
|
|
+#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
|
|
+#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
|
|
+
|
|
+/* Agent registers (common for every core) */
|
|
+#define BCMA_IOCTL 0x0408 /* IO control */
|
|
+#define BCMA_IOCTL_CLK 0x0001
|
|
+#define BCMA_IOCTL_FGC 0x0002
|
|
+#define BCMA_IOCTL_CORE_BITS 0x3FFC
|
|
+#define BCMA_IOCTL_PME_EN 0x4000
|
|
+#define BCMA_IOCTL_BIST_EN 0x8000
|
|
+#define BCMA_IOST 0x0500 /* IO status */
|
|
+#define BCMA_IOST_CORE_BITS 0x0FFF
|
|
+#define BCMA_IOST_DMA64 0x1000
|
|
+#define BCMA_IOST_GATED_CLK 0x2000
|
|
+#define BCMA_IOST_BIST_ERROR 0x4000
|
|
+#define BCMA_IOST_BIST_DONE 0x8000
|
|
+#define BCMA_RESET_CTL 0x0800
|
|
+#define BCMA_RESET_CTL_RESET 0x0001
|
|
+
|
|
+/* BCMA PCI config space registers. */
|
|
+#define BCMA_PCI_PMCSR 0x44
|
|
+#define BCMA_PCI_PE 0x100
|
|
+#define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */
|
|
+#define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */
|
|
+#define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */
|
|
+#define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */
|
|
+#define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */
|
|
+#define BCMA_PCI_IRQS 0x90 /* PCI interrupts */
|
|
+#define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
|
|
+#define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
|
|
+#define BCMA_PCI_BAR0_WIN2 0xAC
|
|
+#define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
|
|
+#define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
|
|
+#define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
|
|
+#define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
|
|
+#define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
|
|
+#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
|
|
+#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
|
|
+
|
|
+#endif /* LINUX_BCMA_REGS_H_ */
|
|
--- a/include/linux/mod_devicetable.h
|
|
+++ b/include/linux/mod_devicetable.h
|
|
@@ -382,6 +382,23 @@ struct ssb_device_id {
|
|
#define SSB_ANY_ID 0xFFFF
|
|
#define SSB_ANY_REV 0xFF
|
|
|
|
+/* Broadcom's specific AMBA core, see drivers/bcma/ */
|
|
+struct bcma_device_id {
|
|
+ __u16 manuf;
|
|
+ __u16 id;
|
|
+ __u8 rev;
|
|
+ __u8 class;
|
|
+};
|
|
+#define BCMA_CORE(_manuf, _id, _rev, _class) \
|
|
+ { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
|
|
+#define BCMA_CORETABLE_END \
|
|
+ { 0, },
|
|
+
|
|
+#define BCMA_ANY_MANUF 0xFFFF
|
|
+#define BCMA_ANY_ID 0xFFFF
|
|
+#define BCMA_ANY_REV 0xFF
|
|
+#define BCMA_ANY_CLASS 0xFF
|
|
+
|
|
struct virtio_device_id {
|
|
__u32 device;
|
|
__u32 vendor;
|
|
--- a/scripts/mod/file2alias.c
|
|
+++ b/scripts/mod/file2alias.c
|
|
@@ -633,6 +633,24 @@ static int do_ssb_entry(const char *file
|
|
return 1;
|
|
}
|
|
|
|
+/* Looks like: bcma:mNidNrevNclN. */
|
|
+static int do_bcma_entry(const char *filename,
|
|
+ struct bcma_device_id *id, char *alias)
|
|
+{
|
|
+ id->manuf = TO_NATIVE(id->manuf);
|
|
+ id->id = TO_NATIVE(id->id);
|
|
+ id->rev = TO_NATIVE(id->rev);
|
|
+ id->class = TO_NATIVE(id->class);
|
|
+
|
|
+ strcpy(alias, "bcma:");
|
|
+ ADD(alias, "m", id->manuf != BCMA_ANY_MANUF, id->manuf);
|
|
+ ADD(alias, "id", id->id != BCMA_ANY_ID, id->id);
|
|
+ ADD(alias, "rev", id->rev != BCMA_ANY_REV, id->rev);
|
|
+ ADD(alias, "cl", id->class != BCMA_ANY_CLASS, id->class);
|
|
+ add_wildcard(alias);
|
|
+ return 1;
|
|
+}
|
|
+
|
|
/* Looks like: virtio:dNvN */
|
|
static int do_virtio_entry(const char *filename, struct virtio_device_id *id,
|
|
char *alias)
|
|
@@ -845,6 +863,10 @@ void handle_moddevtable(struct module *m
|
|
do_table(symval, sym->st_size,
|
|
sizeof(struct ssb_device_id), "ssb",
|
|
do_ssb_entry, mod);
|
|
+ else if (sym_is(symname, "__mod_bcma_device_table"))
|
|
+ do_table(symval, sym->st_size,
|
|
+ sizeof(struct bcma_device_id), "bcma",
|
|
+ do_bcma_entry, mod);
|
|
else if (sym_is(symname, "__mod_virtio_device_table"))
|
|
do_table(symval, sym->st_size,
|
|
sizeof(struct virtio_device_id), "virtio",
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/sprom.c
|
|
@@ -0,0 +1,247 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * SPROM reading
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+
|
|
+#include <linux/bcma/bcma.h>
|
|
+#include <linux/bcma/bcma_regs.h>
|
|
+#include <linux/pci.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/dma-mapping.h>
|
|
+#include <linux/slab.h>
|
|
+
|
|
+#define SPOFF(offset) ((offset) / sizeof(u16))
|
|
+
|
|
+/**************************************************
|
|
+ * R/W ops.
|
|
+ **************************************************/
|
|
+
|
|
+static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
|
|
+{
|
|
+ int i;
|
|
+ for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
|
|
+ sprom[i] = bcma_read16(bus->drv_cc.core,
|
|
+ offset + (i * 2));
|
|
+}
|
|
+
|
|
+/**************************************************
|
|
+ * Validation.
|
|
+ **************************************************/
|
|
+
|
|
+static inline u8 bcma_crc8(u8 crc, u8 data)
|
|
+{
|
|
+ /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
|
|
+ static const u8 t[] = {
|
|
+ 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
|
|
+ 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
|
|
+ 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
|
|
+ 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
|
|
+ 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
|
|
+ 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
|
|
+ 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
|
|
+ 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
|
|
+ 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
|
|
+ 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
|
|
+ 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
|
|
+ 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
|
|
+ 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
|
|
+ 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
|
|
+ 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
|
|
+ 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
|
|
+ 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
|
|
+ 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
|
|
+ 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
|
|
+ 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
|
|
+ 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
|
|
+ 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
|
|
+ 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
|
|
+ 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
|
|
+ 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
|
|
+ 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
|
|
+ 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
|
|
+ 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
|
|
+ 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
|
|
+ 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
|
|
+ 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
|
|
+ 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
|
|
+ };
|
|
+ return t[crc ^ data];
|
|
+}
|
|
+
|
|
+static u8 bcma_sprom_crc(const u16 *sprom)
|
|
+{
|
|
+ int word;
|
|
+ u8 crc = 0xFF;
|
|
+
|
|
+ for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
|
|
+ crc = bcma_crc8(crc, sprom[word] & 0x00FF);
|
|
+ crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
|
|
+ }
|
|
+ crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
|
|
+ crc ^= 0xFF;
|
|
+
|
|
+ return crc;
|
|
+}
|
|
+
|
|
+static int bcma_sprom_check_crc(const u16 *sprom)
|
|
+{
|
|
+ u8 crc;
|
|
+ u8 expected_crc;
|
|
+ u16 tmp;
|
|
+
|
|
+ crc = bcma_sprom_crc(sprom);
|
|
+ tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
|
|
+ expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
|
|
+ if (crc != expected_crc)
|
|
+ return -EPROTO;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcma_sprom_valid(const u16 *sprom)
|
|
+{
|
|
+ u16 revision;
|
|
+ int err;
|
|
+
|
|
+ err = bcma_sprom_check_crc(sprom);
|
|
+ if (err)
|
|
+ return err;
|
|
+
|
|
+ revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
|
|
+ if (revision != 8 && revision != 9) {
|
|
+ pr_err("Unsupported SPROM revision: %d\n", revision);
|
|
+ return -ENOENT;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/**************************************************
|
|
+ * SPROM extraction.
|
|
+ **************************************************/
|
|
+
|
|
+static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
|
|
+{
|
|
+ u16 v;
|
|
+ int i;
|
|
+
|
|
+ bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
|
|
+ SSB_SPROM_REVISION_REV;
|
|
+
|
|
+ for (i = 0; i < 3; i++) {
|
|
+ v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
|
|
+ *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
|
|
+ }
|
|
+
|
|
+ bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
|
|
+
|
|
+ bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
|
|
+ SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
|
|
+ bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
|
|
+ SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
|
|
+ bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
|
|
+ SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
|
|
+ bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
|
|
+ SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
|
|
+
|
|
+ bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
|
|
+ SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
|
|
+ bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
|
|
+ SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
|
|
+ bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
|
|
+ SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
|
|
+ bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
|
|
+ SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
|
|
+
|
|
+ bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
|
|
+ SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
|
|
+ bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
|
|
+ SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
|
|
+ bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
|
|
+ SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
|
|
+ bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
|
|
+ SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
|
|
+
|
|
+ bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
|
|
+ SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
|
|
+ bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
|
|
+ SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
|
|
+ bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
|
|
+ SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
|
|
+ bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
|
|
+ SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
|
|
+
|
|
+ bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
|
|
+ bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
|
|
+ bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
|
|
+ bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
|
|
+
|
|
+ bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
|
|
+
|
|
+ bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
|
|
+ SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
|
|
+ bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
|
|
+ SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
|
|
+ bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
|
|
+ SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
|
|
+ bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
|
|
+ SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
|
|
+ bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
|
|
+ SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
|
|
+
|
|
+ bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
|
|
+ SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
|
|
+ bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
|
|
+ SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
|
|
+ bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
|
|
+ SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
|
|
+ bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
|
|
+ SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
|
|
+ bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
|
|
+ SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
|
|
+}
|
|
+
|
|
+int bcma_sprom_get(struct bcma_bus *bus)
|
|
+{
|
|
+ u16 offset;
|
|
+ u16 *sprom;
|
|
+ int err = 0;
|
|
+
|
|
+ if (!bus->drv_cc.core)
|
|
+ return -EOPNOTSUPP;
|
|
+
|
|
+ if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
|
|
+ return -ENOENT;
|
|
+
|
|
+ sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
|
|
+ GFP_KERNEL);
|
|
+ if (!sprom)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ if (bus->chipinfo.id == 0x4331)
|
|
+ bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
|
|
+
|
|
+ /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
|
|
+ * According to brcm80211 this applies to cards with PCIe rev >= 6
|
|
+ * TODO: understand this condition and use it */
|
|
+ offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
|
|
+ BCMA_CC_SPROM_PCIE6;
|
|
+ bcma_sprom_read(bus, offset, sprom);
|
|
+
|
|
+ if (bus->chipinfo.id == 0x4331)
|
|
+ bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
|
|
+
|
|
+ err = bcma_sprom_valid(sprom);
|
|
+ if (err)
|
|
+ goto out;
|
|
+
|
|
+ bcma_sprom_extract_r8(bus, sprom);
|
|
+
|
|
+out:
|
|
+ kfree(sprom);
|
|
+ return err;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/driver_pci_host.c
|
|
@@ -0,0 +1,14 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * PCI Core in hostmode
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+#include <linux/bcma/bcma.h>
|
|
+
|
|
+void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
|
|
+{
|
|
+ pr_err("No support for PCI core in hostmode yet\n");
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/driver_mips.c
|
|
@@ -0,0 +1,256 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * Broadcom MIPS32 74K core driver
|
|
+ *
|
|
+ * Copyright 2009, Broadcom Corporation
|
|
+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
|
|
+ * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
|
|
+ * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+
|
|
+#include <linux/bcma/bcma.h>
|
|
+
|
|
+#include <linux/serial.h>
|
|
+#include <linux/serial_core.h>
|
|
+#include <linux/serial_reg.h>
|
|
+#include <linux/time.h>
|
|
+
|
|
+/* The 47162a0 hangs when reading MIPS DMP registers registers */
|
|
+static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
|
|
+{
|
|
+ return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
|
|
+ dev->id.id == BCMA_CORE_MIPS_74K;
|
|
+}
|
|
+
|
|
+/* The 5357b0 hangs when reading USB20H DMP registers */
|
|
+static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
|
|
+{
|
|
+ return (dev->bus->chipinfo.id == 0x5357 ||
|
|
+ dev->bus->chipinfo.id == 0x4749) &&
|
|
+ dev->bus->chipinfo.pkg == 11 &&
|
|
+ dev->id.id == BCMA_CORE_USB20_HOST;
|
|
+}
|
|
+
|
|
+static inline u32 mips_read32(struct bcma_drv_mips *mcore,
|
|
+ u16 offset)
|
|
+{
|
|
+ return bcma_read32(mcore->core, offset);
|
|
+}
|
|
+
|
|
+static inline void mips_write32(struct bcma_drv_mips *mcore,
|
|
+ u16 offset,
|
|
+ u32 value)
|
|
+{
|
|
+ bcma_write32(mcore->core, offset, value);
|
|
+}
|
|
+
|
|
+static const u32 ipsflag_irq_mask[] = {
|
|
+ 0,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ1,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ2,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ3,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ4,
|
|
+};
|
|
+
|
|
+static const u32 ipsflag_irq_shift[] = {
|
|
+ 0,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
|
|
+ BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
|
|
+};
|
|
+
|
|
+static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
|
|
+{
|
|
+ u32 flag;
|
|
+
|
|
+ if (bcma_core_mips_bcm47162a0_quirk(dev))
|
|
+ return dev->core_index;
|
|
+ if (bcma_core_mips_bcm5357b0_quirk(dev))
|
|
+ return dev->core_index;
|
|
+ flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
|
|
+
|
|
+ return flag & 0x1F;
|
|
+}
|
|
+
|
|
+/* Get the MIPS IRQ assignment for a specified device.
|
|
+ * If unassigned, 0 is returned.
|
|
+ */
|
|
+unsigned int bcma_core_mips_irq(struct bcma_device *dev)
|
|
+{
|
|
+ struct bcma_device *mdev = dev->bus->drv_mips.core;
|
|
+ u32 irqflag;
|
|
+ unsigned int irq;
|
|
+
|
|
+ irqflag = bcma_core_mips_irqflag(dev);
|
|
+
|
|
+ for (irq = 1; irq <= 4; irq++)
|
|
+ if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
|
|
+ (1 << irqflag))
|
|
+ return irq;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+EXPORT_SYMBOL(bcma_core_mips_irq);
|
|
+
|
|
+static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
|
|
+{
|
|
+ unsigned int oldirq = bcma_core_mips_irq(dev);
|
|
+ struct bcma_bus *bus = dev->bus;
|
|
+ struct bcma_device *mdev = bus->drv_mips.core;
|
|
+ u32 irqflag;
|
|
+
|
|
+ irqflag = bcma_core_mips_irqflag(dev);
|
|
+ BUG_ON(oldirq == 6);
|
|
+
|
|
+ dev->irq = irq + 2;
|
|
+
|
|
+ /* clear the old irq */
|
|
+ if (oldirq == 0)
|
|
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
|
|
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
|
|
+ ~(1 << irqflag));
|
|
+ else
|
|
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
|
|
+
|
|
+ /* assign the new one */
|
|
+ if (irq == 0) {
|
|
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
|
|
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
|
|
+ (1 << irqflag));
|
|
+ } else {
|
|
+ u32 oldirqflag = bcma_read32(mdev,
|
|
+ BCMA_MIPS_MIPS74K_INTMASK(irq));
|
|
+ if (oldirqflag) {
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ /* backplane irq line is in use, find out who uses
|
|
+ * it and set user to irq 0
|
|
+ */
|
|
+ list_for_each_entry_reverse(core, &bus->cores, list) {
|
|
+ if ((1 << bcma_core_mips_irqflag(core)) ==
|
|
+ oldirqflag) {
|
|
+ bcma_core_mips_set_irq(core, 0);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
|
|
+ 1 << irqflag);
|
|
+ }
|
|
+
|
|
+ pr_info("set_irq: core 0x%04x, irq %d => %d\n",
|
|
+ dev->id.id, oldirq + 2, irq + 2);
|
|
+}
|
|
+
|
|
+static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
|
|
+{
|
|
+ int i;
|
|
+ static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
|
|
+ printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
|
|
+ for (i = 0; i <= 6; i++)
|
|
+ printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
|
|
+ printk("\n");
|
|
+}
|
|
+
|
|
+static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ list_for_each_entry_reverse(core, &bus->cores, list) {
|
|
+ bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
|
|
+ }
|
|
+}
|
|
+
|
|
+u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
|
|
+{
|
|
+ struct bcma_bus *bus = mcore->core->bus;
|
|
+
|
|
+ if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
|
|
+ return bcma_pmu_get_clockcpu(&bus->drv_cc);
|
|
+
|
|
+ pr_err("No PMU available, need this to get the cpu clock\n");
|
|
+ return 0;
|
|
+}
|
|
+EXPORT_SYMBOL(bcma_cpu_clock);
|
|
+
|
|
+static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
|
|
+{
|
|
+ struct bcma_bus *bus = mcore->core->bus;
|
|
+
|
|
+ switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
|
|
+ case BCMA_CC_FLASHT_STSER:
|
|
+ case BCMA_CC_FLASHT_ATSER:
|
|
+ pr_err("Serial flash not supported.\n");
|
|
+ break;
|
|
+ case BCMA_CC_FLASHT_PARA:
|
|
+ pr_info("found parallel flash.\n");
|
|
+ bus->drv_cc.pflash.window = 0x1c000000;
|
|
+ bus->drv_cc.pflash.window_size = 0x02000000;
|
|
+
|
|
+ if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
|
|
+ BCMA_CC_FLASH_CFG_DS) == 0)
|
|
+ bus->drv_cc.pflash.buswidth = 1;
|
|
+ else
|
|
+ bus->drv_cc.pflash.buswidth = 2;
|
|
+ break;
|
|
+ default:
|
|
+ pr_err("flash not supported.\n");
|
|
+ }
|
|
+}
|
|
+
|
|
+void bcma_core_mips_init(struct bcma_drv_mips *mcore)
|
|
+{
|
|
+ struct bcma_bus *bus;
|
|
+ struct bcma_device *core;
|
|
+ bus = mcore->core->bus;
|
|
+
|
|
+ pr_info("Initializing MIPS core...\n");
|
|
+
|
|
+ if (!mcore->setup_done)
|
|
+ mcore->assigned_irqs = 1;
|
|
+
|
|
+ /* Assign IRQs to all cores on the bus */
|
|
+ list_for_each_entry_reverse(core, &bus->cores, list) {
|
|
+ int mips_irq;
|
|
+ if (core->irq)
|
|
+ continue;
|
|
+
|
|
+ mips_irq = bcma_core_mips_irq(core);
|
|
+ if (mips_irq > 4)
|
|
+ core->irq = 0;
|
|
+ else
|
|
+ core->irq = mips_irq + 2;
|
|
+ if (core->irq > 5)
|
|
+ continue;
|
|
+ switch (core->id.id) {
|
|
+ case BCMA_CORE_PCI:
|
|
+ case BCMA_CORE_PCIE:
|
|
+ case BCMA_CORE_ETHERNET:
|
|
+ case BCMA_CORE_ETHERNET_GBIT:
|
|
+ case BCMA_CORE_MAC_GBIT:
|
|
+ case BCMA_CORE_80211:
|
|
+ case BCMA_CORE_USB20_HOST:
|
|
+ /* These devices get their own IRQ line if available,
|
|
+ * the rest goes on IRQ0
|
|
+ */
|
|
+ if (mcore->assigned_irqs <= 4)
|
|
+ bcma_core_mips_set_irq(core,
|
|
+ mcore->assigned_irqs++);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ pr_info("IRQ reconfiguration done\n");
|
|
+ bcma_core_mips_dump_irq(bus);
|
|
+
|
|
+ if (mcore->setup_done)
|
|
+ return;
|
|
+
|
|
+ bcma_chipco_serial_init(&bus->drv_cc);
|
|
+ bcma_core_mips_flash_detect(mcore);
|
|
+ mcore->setup_done = true;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/bcma/host_soc.c
|
|
@@ -0,0 +1,183 @@
|
|
+/*
|
|
+ * Broadcom specific AMBA
|
|
+ * System on Chip (SoC) Host
|
|
+ *
|
|
+ * Licensed under the GNU/GPL. See COPYING for details.
|
|
+ */
|
|
+
|
|
+#include "bcma_private.h"
|
|
+#include "scan.h"
|
|
+#include <linux/bcma/bcma.h>
|
|
+#include <linux/bcma/bcma_soc.h>
|
|
+
|
|
+static u8 bcma_host_soc_read8(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return readb(core->io_addr + offset);
|
|
+}
|
|
+
|
|
+static u16 bcma_host_soc_read16(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return readw(core->io_addr + offset);
|
|
+}
|
|
+
|
|
+static u32 bcma_host_soc_read32(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return readl(core->io_addr + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_soc_write8(struct bcma_device *core, u16 offset,
|
|
+ u8 value)
|
|
+{
|
|
+ writeb(value, core->io_addr + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_soc_write16(struct bcma_device *core, u16 offset,
|
|
+ u16 value)
|
|
+{
|
|
+ writew(value, core->io_addr + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_soc_write32(struct bcma_device *core, u16 offset,
|
|
+ u32 value)
|
|
+{
|
|
+ writel(value, core->io_addr + offset);
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_BCMA_BLOCKIO
|
|
+static void bcma_host_soc_block_read(struct bcma_device *core, void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width)
|
|
+{
|
|
+ void __iomem *addr = core->io_addr + offset;
|
|
+
|
|
+ switch (reg_width) {
|
|
+ case sizeof(u8): {
|
|
+ u8 *buf = buffer;
|
|
+
|
|
+ while (count) {
|
|
+ *buf = __raw_readb(addr);
|
|
+ buf++;
|
|
+ count--;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ case sizeof(u16): {
|
|
+ __le16 *buf = buffer;
|
|
+
|
|
+ WARN_ON(count & 1);
|
|
+ while (count) {
|
|
+ *buf = (__force __le16)__raw_readw(addr);
|
|
+ buf++;
|
|
+ count -= 2;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ case sizeof(u32): {
|
|
+ __le32 *buf = buffer;
|
|
+
|
|
+ WARN_ON(count & 3);
|
|
+ while (count) {
|
|
+ *buf = (__force __le32)__raw_readl(addr);
|
|
+ buf++;
|
|
+ count -= 4;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ default:
|
|
+ WARN_ON(1);
|
|
+ }
|
|
+}
|
|
+
|
|
+static void bcma_host_soc_block_write(struct bcma_device *core,
|
|
+ const void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width)
|
|
+{
|
|
+ void __iomem *addr = core->io_addr + offset;
|
|
+
|
|
+ switch (reg_width) {
|
|
+ case sizeof(u8): {
|
|
+ const u8 *buf = buffer;
|
|
+
|
|
+ while (count) {
|
|
+ __raw_writeb(*buf, addr);
|
|
+ buf++;
|
|
+ count--;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ case sizeof(u16): {
|
|
+ const __le16 *buf = buffer;
|
|
+
|
|
+ WARN_ON(count & 1);
|
|
+ while (count) {
|
|
+ __raw_writew((__force u16)(*buf), addr);
|
|
+ buf++;
|
|
+ count -= 2;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ case sizeof(u32): {
|
|
+ const __le32 *buf = buffer;
|
|
+
|
|
+ WARN_ON(count & 3);
|
|
+ while (count) {
|
|
+ __raw_writel((__force u32)(*buf), addr);
|
|
+ buf++;
|
|
+ count -= 4;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ default:
|
|
+ WARN_ON(1);
|
|
+ }
|
|
+}
|
|
+#endif /* CONFIG_BCMA_BLOCKIO */
|
|
+
|
|
+static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
|
|
+{
|
|
+ return readl(core->io_wrap + offset);
|
|
+}
|
|
+
|
|
+static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
|
|
+ u32 value)
|
|
+{
|
|
+ writel(value, core->io_wrap + offset);
|
|
+}
|
|
+
|
|
+const struct bcma_host_ops bcma_host_soc_ops = {
|
|
+ .read8 = bcma_host_soc_read8,
|
|
+ .read16 = bcma_host_soc_read16,
|
|
+ .read32 = bcma_host_soc_read32,
|
|
+ .write8 = bcma_host_soc_write8,
|
|
+ .write16 = bcma_host_soc_write16,
|
|
+ .write32 = bcma_host_soc_write32,
|
|
+#ifdef CONFIG_BCMA_BLOCKIO
|
|
+ .block_read = bcma_host_soc_block_read,
|
|
+ .block_write = bcma_host_soc_block_write,
|
|
+#endif
|
|
+ .aread32 = bcma_host_soc_aread32,
|
|
+ .awrite32 = bcma_host_soc_awrite32,
|
|
+};
|
|
+
|
|
+int __init bcma_host_soc_register(struct bcma_soc *soc)
|
|
+{
|
|
+ struct bcma_bus *bus = &soc->bus;
|
|
+ int err;
|
|
+
|
|
+ /* iomap only first core. We have to read some register on this core
|
|
+ * to scan the bus.
|
|
+ */
|
|
+ bus->mmio = ioremap_nocache(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1);
|
|
+ if (!bus->mmio)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ /* Host specific */
|
|
+ bus->hosttype = BCMA_HOSTTYPE_SOC;
|
|
+ bus->ops = &bcma_host_soc_ops;
|
|
+
|
|
+ /* Register */
|
|
+ err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
|
|
+ if (err)
|
|
+ iounmap(bus->mmio);
|
|
+
|
|
+ return err;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/include/linux/bcma/bcma_driver_mips.h
|
|
@@ -0,0 +1,51 @@
|
|
+#ifndef LINUX_BCMA_DRIVER_MIPS_H_
|
|
+#define LINUX_BCMA_DRIVER_MIPS_H_
|
|
+
|
|
+#define BCMA_MIPS_IPSFLAG 0x0F08
|
|
+/* which sbflags get routed to mips interrupt 1 */
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
|
|
+/* which sbflags get routed to mips interrupt 2 */
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ2_SHIFT 8
|
|
+/* which sbflags get routed to mips interrupt 3 */
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ3_SHIFT 16
|
|
+/* which sbflags get routed to mips interrupt 4 */
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
|
|
+#define BCMA_MIPS_IPSFLAG_IRQ4_SHIFT 24
|
|
+
|
|
+/* MIPS 74K core registers */
|
|
+#define BCMA_MIPS_MIPS74K_CORECTL 0x0000
|
|
+#define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
|
|
+#define BCMA_MIPS_MIPS74K_BIST 0x000C
|
|
+#define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
|
|
+#define BCMA_MIPS_MIPS74K_INTMASK(int) \
|
|
+ ((int) * 4 + BCMA_MIPS_MIPS74K_INTMASK_INT0)
|
|
+#define BCMA_MIPS_MIPS74K_NMIMASK 0x002C
|
|
+#define BCMA_MIPS_MIPS74K_GPIOSEL 0x0040
|
|
+#define BCMA_MIPS_MIPS74K_GPIOOUT 0x0044
|
|
+#define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
|
|
+#define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
|
|
+
|
|
+#define BCMA_MIPS_OOBSELOUTA30 0x100
|
|
+
|
|
+struct bcma_device;
|
|
+
|
|
+struct bcma_drv_mips {
|
|
+ struct bcma_device *core;
|
|
+ u8 setup_done:1;
|
|
+ unsigned int assigned_irqs;
|
|
+};
|
|
+
|
|
+#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
+extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
|
|
+#else
|
|
+static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
|
|
+#endif
|
|
+
|
|
+extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
|
|
+
|
|
+extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
|
|
+
|
|
+#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
|
|
--- /dev/null
|
|
+++ b/include/linux/bcma/bcma_soc.h
|
|
@@ -0,0 +1,16 @@
|
|
+#ifndef LINUX_BCMA_SOC_H_
|
|
+#define LINUX_BCMA_SOC_H_
|
|
+
|
|
+#include <linux/bcma/bcma.h>
|
|
+
|
|
+struct bcma_soc {
|
|
+ struct bcma_bus bus;
|
|
+ struct bcma_device core_cc;
|
|
+ struct bcma_device core_mips;
|
|
+};
|
|
+
|
|
+int __init bcma_host_soc_register(struct bcma_soc *soc);
|
|
+
|
|
+int bcma_bus_register(struct bcma_bus *bus);
|
|
+
|
|
+#endif /* LINUX_BCMA_SOC_H_ */
|