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10f03e0475
This patch adds 802.1Q VLAN support for the ADM6996M chip. The driver is loaded for both the FC and M model. It will detect which of the two chips is connected. The FC model is initialised, but no further functionality is offered. The PHY driver will always report "100 Mbit/s, link up", for both the M and FC models. This reflects the fact that the link between switch chip and Ethernet MAC is always on[1]. Further documentation can be found in the kernel's Documentation/networking/adm6996.txt Signed-of-By: Peter Lebbing <peter@digitalbrains.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26865 3c298f89-4303-0410-b956-a3cf2f4a3e73
163 lines
5.1 KiB
C
163 lines
5.1 KiB
C
/*
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* ADM6996 switch driver
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*
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* Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
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* Copyright (c) 2010,2011 Peter Lebbing <peter@digitalbrains.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License v2 as published by the
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* Free Software Foundation
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*/
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#ifndef __ADM6996_H
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#define __ADM6996_H
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/*
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* ADM_PHY_PORTS: Number of ports with a PHY.
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* We only control ports 0 to 3, because if 4 is connected, it is most likely
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* not connected to the switch but to a separate MII and MAC for the WAN port.
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*/
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#define ADM_PHY_PORTS 4
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#define ADM_NUM_PORTS 6
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#define ADM_CPU_PORT 5
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#define ADM_NUM_VLANS 16
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#define ADM_VLAN_MAX_ID 4094
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enum admreg {
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ADM_EEPROM_BASE = 0x0,
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ADM_P0_CFG = ADM_EEPROM_BASE + 1,
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ADM_P1_CFG = ADM_EEPROM_BASE + 3,
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ADM_P2_CFG = ADM_EEPROM_BASE + 5,
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ADM_P3_CFG = ADM_EEPROM_BASE + 7,
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ADM_P4_CFG = ADM_EEPROM_BASE + 8,
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ADM_P5_CFG = ADM_EEPROM_BASE + 9,
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ADM_SYSC0 = ADM_EEPROM_BASE + 0xa,
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ADM_VLAN_PRIOMAP = ADM_EEPROM_BASE + 0xe,
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ADM_SYSC3 = ADM_EEPROM_BASE + 0x11,
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/* Input Force No Tag Enable */
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ADM_IFNTE = ADM_EEPROM_BASE + 0x20,
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ADM_VID_CHECK = ADM_EEPROM_BASE + 0x26,
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ADM_P0_PVID = ADM_EEPROM_BASE + 0x28,
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ADM_P1_PVID = ADM_EEPROM_BASE + 0x29,
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/* Output Tag Bypass Enable and P2 PVID */
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ADM_OTBE_P2_PVID = ADM_EEPROM_BASE + 0x2a,
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ADM_P3_P4_PVID = ADM_EEPROM_BASE + 0x2b,
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ADM_P5_PVID = ADM_EEPROM_BASE + 0x2c,
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ADM_EEPROM_EXT_BASE = 0x40,
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#define ADM_VLAN_FILT_L(n) (ADM_EEPROM_EXT_BASE + 2 * (n))
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#define ADM_VLAN_FILT_H(n) (ADM_EEPROM_EXT_BASE + 1 + 2 * (n))
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ADM_COUNTER_BASE = 0xa0,
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ADM_SIG0 = ADM_COUNTER_BASE + 0,
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ADM_SIG1 = ADM_COUNTER_BASE + 1,
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ADM_PHY_BASE = 0x200,
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#define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n))
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};
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/* Chip identification patterns */
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#define ADM_SIG0_MASK 0xffff
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#define ADM_SIG0_VAL 0x1023
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#define ADM_SIG1_MASK 0xffff
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#define ADM_SIG1_VAL 0x0007
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enum {
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ADM_PHYCFG_COLTST = (1 << 7), /* Enable collision test */
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ADM_PHYCFG_DPLX = (1 << 8), /* Enable full duplex */
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ADM_PHYCFG_ANEN_RST = (1 << 9), /* Restart auto negotiation (self clear) */
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ADM_PHYCFG_ISO = (1 << 10), /* Isolate PHY */
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ADM_PHYCFG_PDN = (1 << 11), /* Power down PHY */
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ADM_PHYCFG_ANEN = (1 << 12), /* Enable auto negotiation */
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ADM_PHYCFG_SPEED_100 = (1 << 13), /* Enable 100 Mbit/s */
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ADM_PHYCFG_LPBK = (1 << 14), /* Enable loopback operation */
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ADM_PHYCFG_RST = (1 << 15), /* Reset the port (self clear) */
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ADM_PHYCFG_INIT = (
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ADM_PHYCFG_RST |
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ADM_PHYCFG_SPEED_100 |
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ADM_PHYCFG_ANEN |
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ADM_PHYCFG_ANEN_RST
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)
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};
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enum {
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ADM_PORTCFG_FC = (1 << 0), /* Enable 802.x flow control */
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ADM_PORTCFG_AN = (1 << 1), /* Enable auto-negotiation */
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ADM_PORTCFG_SPEED_100 = (1 << 2), /* Enable 100 Mbit/s */
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ADM_PORTCFG_DPLX = (1 << 3), /* Enable full duplex */
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ADM_PORTCFG_OT = (1 << 4), /* Output tagged packets */
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ADM_PORTCFG_PD = (1 << 5), /* Port disable */
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ADM_PORTCFG_TV_PRIO = (1 << 6), /* 0 = VLAN based priority
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* 1 = TOS based priority */
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ADM_PORTCFG_PPE = (1 << 7), /* Port based priority enable */
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ADM_PORTCFG_PP_S = (1 << 8), /* Port based priority, 2 bits */
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ADM_PORTCFG_PVID_BASE = (1 << 10), /* Primary VLAN id, 4 bits */
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ADM_PORTCFG_FSE = (1 << 14), /* Fx select enable */
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ADM_PORTCFG_CAM = (1 << 15), /* Crossover Auto MDIX */
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ADM_PORTCFG_INIT = (
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ADM_PORTCFG_FC |
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ADM_PORTCFG_AN |
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ADM_PORTCFG_SPEED_100 |
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ADM_PORTCFG_DPLX |
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ADM_PORTCFG_CAM
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),
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ADM_PORTCFG_CPU = (
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ADM_PORTCFG_FC |
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ADM_PORTCFG_SPEED_100 |
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ADM_PORTCFG_OT |
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ADM_PORTCFG_DPLX
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),
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};
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#define ADM_PORTCFG_PPID(n) ((n & 0x3) << 8)
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#define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10)
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#define ADM_PORTCFG_PVID_MASK (0xf << 10)
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#define ADM_IFNTE_MASK (0x3f << 9)
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#define ADM_VID_CHECK_MASK (0x3f << 6)
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#define ADM_P0_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
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#define ADM_P1_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
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#define ADM_P2_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
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#define ADM_P3_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
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#define ADM_P4_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 8)
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#define ADM_P5_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
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#define ADM_P2_PVID_MASK 0xff
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#define ADM_OTBE(n) (((n) & 0x3f) << 8)
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#define ADM_OTBE_MASK (0x3f << 8)
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/* ADM_SYSC0 */
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enum {
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ADM_NTTE = (1 << 2), /* New Tag Transmit Enable */
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ADM_RVID1 = (1 << 8) /* Replace VLAN ID 1 */
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};
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/* Tag Based VLAN in ADM_SYSC3 */
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#define ADM_TBV (1 << 5)
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static const u8 adm_portcfg[] = {
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[0] = ADM_P0_CFG,
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[1] = ADM_P1_CFG,
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[2] = ADM_P2_CFG,
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[3] = ADM_P3_CFG,
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[4] = ADM_P4_CFG,
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[5] = ADM_P5_CFG,
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};
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/* Fields in ADM_VLAN_FILT_L(x) */
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#define ADM_VLAN_FILT_FID(n) (((n) & 0xf) << 12)
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#define ADM_VLAN_FILT_TAGGED(n) (((n) & 0x3f) << 6)
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#define ADM_VLAN_FILT_MEMBER(n) (((n) & 0x3f) << 0)
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#define ADM_VLAN_FILT_MEMBER_MASK 0x3f
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/* Fields in ADM_VLAN_FILT_H(x) */
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#define ADM_VLAN_FILT_VALID (1 << 15)
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#define ADM_VLAN_FILT_VID(n) (((n) & 0xfff) << 0)
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/*
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* Split the register address in phy id and register
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* it will get combined again by the mdio bus op
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*/
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#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
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#endif
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