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git://projects.qi-hardware.com/openwrt-xburst.git
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e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
121 lines
3.2 KiB
Diff
121 lines
3.2 KiB
Diff
From 9c19e86a7eccf8efd159ba213290830164f33a71 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 11 Dec 2011 17:36:42 +0100
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Subject: [PATCH 23/35] MIPS: ath79: add SoC detection code for AR934X
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Also add 'soc_is_ar934[124x]' helper functions and a Kconfig
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symbol for the AR934X SoCs.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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---
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arch/mips/ath79/Kconfig | 4 ++++
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arch/mips/ath79/setup.c | 21 ++++++++++++++++++++-
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
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arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++
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4 files changed, 49 insertions(+), 1 deletions(-)
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -69,6 +69,10 @@ config SOC_AR933X
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select USB_ARCH_HAS_EHCI
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def_bool n
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+config SOC_AR934X
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+ select USB_ARCH_HAS_EHCI
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+ def_bool n
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+
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config ATH79_DEV_GPIO_BUTTONS
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def_bool n
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--- a/arch/mips/ath79/setup.c
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+++ b/arch/mips/ath79/setup.c
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@@ -1,10 +1,11 @@
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/*
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* Atheros AR71XX/AR724X/AR913X specific setup
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*
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+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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- * Parts of this file are based on Atheros' 2.6.15 BSP
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+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type
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rev = id & AR933X_REV_ID_REVISION_MASK;
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break;
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+ case REV_ID_MAJOR_AR9341:
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+ ath79_soc = ATH79_SOC_AR9341;
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+ chip = "9341";
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+ rev = id & AR934X_REV_ID_REVISION_MASK;
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+ break;
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+
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+ case REV_ID_MAJOR_AR9342:
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+ ath79_soc = ATH79_SOC_AR9342;
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+ chip = "9342";
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+ rev = id & AR934X_REV_ID_REVISION_MASK;
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+ break;
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+
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+ case REV_ID_MAJOR_AR9344:
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+ ath79_soc = ATH79_SOC_AR9344;
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+ chip = "9344";
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+ rev = id & AR934X_REV_ID_REVISION_MASK;
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+ break;
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+
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default:
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panic("ath79: unknown SoC, id:0x%08x\n", id);
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -271,6 +271,8 @@
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#define AR724X_REV_ID_REVISION_MASK 0x3
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+#define AR934X_REV_ID_REVISION_MASK 0xf
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+
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/*
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* SPI block
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*/
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--- a/arch/mips/include/asm/mach-ath79/ath79.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79.h
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@@ -29,6 +29,9 @@ enum ath79_soc_type {
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ATH79_SOC_AR9132,
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ATH79_SOC_AR9330,
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ATH79_SOC_AR9331,
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+ ATH79_SOC_AR9341,
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+ ATH79_SOC_AR9342,
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+ ATH79_SOC_AR9344,
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};
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extern enum ath79_soc_type ath79_soc;
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@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void)
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ath79_soc == ATH79_SOC_AR9331);
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}
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+static inline int soc_is_ar9341(void)
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+{
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+ return (ath79_soc == ATH79_SOC_AR9341);
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+}
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+
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+static inline int soc_is_ar9342(void)
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+{
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+ return (ath79_soc == ATH79_SOC_AR9342);
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+}
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+
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+static inline int soc_is_ar9344(void)
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+{
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+ return (ath79_soc == ATH79_SOC_AR9344);
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+}
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+
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+static inline int soc_is_ar934x(void)
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+{
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+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
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+}
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+
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extern void __iomem *ath79_ddr_base;
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extern void __iomem *ath79_pll_base;
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extern void __iomem *ath79_reset_base;
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