mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 01:49:00 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32580 3c298f89-4303-0410-b956-a3cf2f4a3e73
838 lines
29 KiB
Diff
838 lines
29 KiB
Diff
--- a/drivers/ssb/b43_pci_bridge.c
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+++ b/drivers/ssb/b43_pci_bridge.c
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@@ -29,11 +29,14 @@ static const struct pci_device_id b43_pc
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -13,6 +13,9 @@
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#include <linux/ssb/ssb_driver_chipcommon.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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+#ifdef CONFIG_BCM47XX
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+#include <asm/mach-bcm47xx/nvram.h>
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+#endif
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#include "ssb_private.h"
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@@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
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u32 pmuctl, tmp, pllctl;
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unsigned int i;
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- if ((bus->chip_id == 0x5354) && !crystalfreq) {
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- /* The 5354 crystal freq is 25MHz */
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- crystalfreq = 25000;
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- }
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if (crystalfreq)
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e = pmu0_plltab_find_entry(crystalfreq);
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if (!e)
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@@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
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u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
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if (bus->bustype == SSB_BUSTYPE_SSB) {
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- /* TODO: The user may override the crystal frequency. */
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+#ifdef CONFIG_BCM47XX
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+ char buf[20];
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+ if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
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+ crystalfreq = simple_strtoul(buf, NULL, 0);
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+#endif
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}
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switch (bus->chip_id) {
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@@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
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ssb_pmu1_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4328:
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+ ssb_pmu0_pllinit_r0(cc, crystalfreq);
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+ break;
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case 0x5354:
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+ if (crystalfreq == 0)
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+ crystalfreq = 25000;
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ssb_pmu0_pllinit_r0(cc, crystalfreq);
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break;
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case 0x4322:
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@@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
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EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
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EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
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+
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+u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
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+ return 240000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU cpu clock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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+
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+u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ return 120000000;
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU controlclock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
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struct ssb_bus *bus = mcore->dev->bus;
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u32 pll_type, n, m, rate = 0;
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_cpu_clock(&bus->chipco);
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+
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if (bus->extif.dev) {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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} else if (bus->chipco.dev) {
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
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put_device(dev->dev);
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}
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-static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
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-{
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- if (drv)
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- get_driver(&drv->drv);
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- return drv;
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-}
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-
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-static inline void ssb_driver_put(struct ssb_driver *drv)
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-{
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- if (drv)
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- put_driver(&drv->drv);
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-}
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-
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static int ssb_device_resume(struct device *dev)
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{
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struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
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@@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
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ssb_device_put(sdev);
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continue;
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}
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- sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
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- if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
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- ssb_device_put(sdev);
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+ sdrv = drv_to_ssb_drv(sdev->dev->driver);
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+ if (SSB_WARN_ON(!sdrv->remove))
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continue;
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- }
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sdrv->remove(sdev);
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ctx->device_frozen[i] = 1;
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}
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@@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
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dev_name(sdev->dev));
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result = err;
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}
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- ssb_driver_put(sdrv);
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ssb_device_put(sdev);
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}
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@@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
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u32 plltype;
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u32 clkctl_n, clkctl_m;
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+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_controlclock(&bus->chipco);
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+
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if (ssb_extif_available(&bus->extif))
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ssb_extif_get_clockcontrol(&bus->extif, &plltype,
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&clkctl_n, &clkctl_m);
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -178,6 +178,18 @@ err_pci:
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#define SPEX(_outvar, _offset, _mask, _shift) \
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SPEX16(_outvar, _offset, _mask, _shift)
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+#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
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+ do { \
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+ SPEX(_field[0], _offset + 0, _mask, _shift); \
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+ SPEX(_field[1], _offset + 2, _mask, _shift); \
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+ SPEX(_field[2], _offset + 4, _mask, _shift); \
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+ SPEX(_field[3], _offset + 6, _mask, _shift); \
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+ SPEX(_field[4], _offset + 8, _mask, _shift); \
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+ SPEX(_field[5], _offset + 10, _mask, _shift); \
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+ SPEX(_field[6], _offset + 12, _mask, _shift); \
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+ SPEX(_field[7], _offset + 14, _mask, _shift); \
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+ } while (0)
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+
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static inline u8 ssb_crc8(u8 crc, u8 data)
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{
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@@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
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{
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int i;
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u16 v;
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- s8 gain;
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u16 loc[3];
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if (out->revision == 3) /* rev 3 moved MAC */
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@@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
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SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
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SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
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SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
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- SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
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- SSB_SPROM1_BINF_CCODE_SHIFT);
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+ if (out->revision == 1)
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+ SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
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+ SSB_SPROM1_BINF_CCODE_SHIFT);
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SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
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SSB_SPROM1_BINF_ANTA_SHIFT);
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SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
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@@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
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SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
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if (out->revision >= 2)
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SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+ SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
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+ SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
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/* Extract the antenna gain values. */
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- gain = r123_extract_antgain(out->revision, in,
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- SSB_SPROM1_AGAIN_BG,
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- SSB_SPROM1_AGAIN_BG_SHIFT);
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- out->antenna_gain.ghz24.a0 = gain;
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- out->antenna_gain.ghz24.a1 = gain;
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- out->antenna_gain.ghz24.a2 = gain;
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- out->antenna_gain.ghz24.a3 = gain;
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- gain = r123_extract_antgain(out->revision, in,
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- SSB_SPROM1_AGAIN_A,
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- SSB_SPROM1_AGAIN_A_SHIFT);
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- out->antenna_gain.ghz5.a0 = gain;
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- out->antenna_gain.ghz5.a1 = gain;
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- out->antenna_gain.ghz5.a2 = gain;
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- out->antenna_gain.ghz5.a3 = gain;
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+ out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
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+ SSB_SPROM1_AGAIN_BG,
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+ SSB_SPROM1_AGAIN_BG_SHIFT);
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+ out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
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+ SSB_SPROM1_AGAIN_A,
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+ SSB_SPROM1_AGAIN_A_SHIFT);
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}
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/* Revs 4 5 and 8 have partially shared layout */
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@@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
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SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
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SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
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SSB_SPROM4_ETHPHY_ET1A_SHIFT);
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+ SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
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if (out->revision == 4) {
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- SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
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+ SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
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+ SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
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SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
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SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
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SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
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SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
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} else {
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- SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
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+ SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
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+ SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
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SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
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SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
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SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
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@@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
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}
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/* Extract the antenna gain values. */
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- SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
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+ SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
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SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
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- SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
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+ SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
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SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
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- SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
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+ SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
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SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
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- SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
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+ SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
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SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
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- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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- sizeof(out->antenna_gain.ghz5));
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sprom_extract_r458(out, in);
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@@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
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static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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- u16 v;
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+ u16 v, o;
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+ u16 pwr_info_offset[] = {
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+ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
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+ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
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+ };
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+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
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+ ARRAY_SIZE(out->core_pwr_info));
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/* extract the MAC address */
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for (i = 0; i < 3; i++) {
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v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
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*(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
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}
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- SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
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+ SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
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+ SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
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+ SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
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SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
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SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
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SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
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@@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_
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SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
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/* Extract the antenna gain values. */
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- SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
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+ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
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SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
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- SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
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+ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
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SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
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- SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
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+ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
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SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
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- SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
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+ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
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SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
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- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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- sizeof(out->antenna_gain.ghz5));
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+
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+ /* Extract cores power info info */
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+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
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+ o = pwr_info_offset[i];
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+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
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+ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
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+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
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+ SSB_SPROM8_2G_MAXP, 0);
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+
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+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
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+
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+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
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+ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
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+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
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+ SSB_SPROM8_5G_MAXP, 0);
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+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
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+ SSB_SPROM8_5GH_MAXP, 0);
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+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
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+ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
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+
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+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
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+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
|
|
+ }
|
|
|
|
/* Extract FEM info */
|
|
SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
|
|
@@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_
|
|
SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
|
|
SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
|
|
|
|
+ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
|
|
+ SSB_SPROM8_LEDDC_ON_SHIFT);
|
|
+ SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
|
|
+ SSB_SPROM8_LEDDC_OFF_SHIFT);
|
|
+
|
|
+ SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
|
|
+ SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
|
|
+ SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
|
|
+ SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
|
|
+ SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
|
|
+ SSB_SPROM8_TXRXC_SWITCH_SHIFT);
|
|
+
|
|
+ SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
|
|
+
|
|
+ SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
|
|
+ SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
|
|
+ SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
|
|
+ SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
|
|
+
|
|
+ SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
|
|
+ SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
|
|
+ SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
|
|
+ SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
|
|
+ SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
|
|
+ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
|
|
+ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
|
|
+ SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
|
|
+ SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
|
|
+ SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
|
|
+ SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
|
|
+ SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
|
|
+ SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
|
|
+ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
|
|
+ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
|
|
+ SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
|
|
+ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
|
|
+ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
|
|
+ SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
|
|
+ SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
|
|
+
|
|
+ SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
|
|
+ SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
|
|
+ SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
|
|
+ SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
|
|
+
|
|
+ SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
|
|
+ SSB_SPROM8_THERMAL_TRESH_SHIFT);
|
|
+ SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
|
|
+ SSB_SPROM8_THERMAL_OFFSET_SHIFT);
|
|
+ SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
|
|
+ SSB_SPROM8_TEMPDELTA_PHYCAL,
|
|
+ SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
|
|
+ SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
|
|
+ SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
|
|
+ SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
|
|
+ SSB_SPROM8_TEMPDELTA_HYSTERESIS,
|
|
+ SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
|
|
sprom_extract_r458(out, in);
|
|
|
|
/* TODO - get remaining rev 8 stuff needed */
|
|
@@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
|
|
{
|
|
bi->vendor = bus->host_pci->subsystem_vendor;
|
|
bi->type = bus->host_pci->subsystem_device;
|
|
- bi->rev = bus->host_pci->revision;
|
|
}
|
|
|
|
int ssb_pci_get_invariants(struct ssb_bus *bus,
|
|
--- a/drivers/ssb/pcmcia.c
|
|
+++ b/drivers/ssb/pcmcia.c
|
|
@@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
|
|
case SSB_PCMCIA_CIS_ANTGAIN:
|
|
GOTO_ERROR_ON(tuple->TupleDataLen != 2,
|
|
"antg tpl size");
|
|
- sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
|
|
- sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a0 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a1 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a2 = tuple->TupleData[1];
|
|
+ sprom->antenna_gain.a3 = tuple->TupleData[1];
|
|
break;
|
|
case SSB_PCMCIA_CIS_BFLAGS:
|
|
GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
|
|
--- a/drivers/ssb/scan.c
|
|
+++ b/drivers/ssb/scan.c
|
|
@@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
|
|
return "ARM 1176";
|
|
case SSB_DEV_ARM_7TDMI:
|
|
return "ARM 7TDMI";
|
|
+ case SSB_DEV_ARM_CM3:
|
|
+ return "ARM Cortex M3";
|
|
}
|
|
return "UNKNOWN";
|
|
}
|
|
@@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
|
|
bus->chip_package = 0;
|
|
}
|
|
}
|
|
+ ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
|
|
+ "package 0x%02X\n", bus->chip_id, bus->chip_rev,
|
|
+ bus->chip_package);
|
|
if (!bus->nr_devices)
|
|
bus->nr_devices = chipid_to_nrcores(bus->chip_id);
|
|
if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
|
|
--- a/drivers/ssb/sdio.c
|
|
+++ b/drivers/ssb/sdio.c
|
|
@@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
|
|
case SSB_SDIO_CIS_ANTGAIN:
|
|
GOTO_ERROR_ON(tuple->size != 2,
|
|
"antg tpl size");
|
|
- sprom->antenna_gain.ghz24.a0 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz24.a1 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz24.a2 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz24.a3 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a0 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a1 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a2 = tuple->data[1];
|
|
- sprom->antenna_gain.ghz5.a3 = tuple->data[1];
|
|
+ sprom->antenna_gain.a0 = tuple->data[1];
|
|
+ sprom->antenna_gain.a1 = tuple->data[1];
|
|
+ sprom->antenna_gain.a2 = tuple->data[1];
|
|
+ sprom->antenna_gain.a3 = tuple->data[1];
|
|
break;
|
|
case SSB_SDIO_CIS_BFLAGS:
|
|
GOTO_ERROR_ON((tuple->size != 3) &&
|
|
--- a/drivers/ssb/ssb_private.h
|
|
+++ b/drivers/ssb/ssb_private.h
|
|
@@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
|
|
}
|
|
#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
|
|
|
|
+/* driver_chipcommon_pmu.c */
|
|
+extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
|
|
+extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
|
|
+
|
|
#endif /* LINUX_SSB_PRIVATE_H_ */
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -16,6 +16,12 @@ struct pcmcia_device;
|
|
struct ssb_bus;
|
|
struct ssb_driver;
|
|
|
|
+struct ssb_sprom_core_pwr_info {
|
|
+ u8 itssi_2g, itssi_5g;
|
|
+ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
|
|
+ u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
|
|
+};
|
|
+
|
|
struct ssb_sprom {
|
|
u8 revision;
|
|
u8 il0mac[6]; /* MAC address for 802.11b/g */
|
|
@@ -26,9 +32,12 @@ struct ssb_sprom {
|
|
u8 et0mdcport; /* MDIO for enet0 */
|
|
u8 et1mdcport; /* MDIO for enet1 */
|
|
u16 board_rev; /* Board revision number from SPROM. */
|
|
+ u16 board_num; /* Board number from SPROM. */
|
|
+ u16 board_type; /* Board type from SPROM. */
|
|
u8 country_code; /* Country Code */
|
|
- u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
|
|
- u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
|
|
+ char alpha2[2]; /* Country Code as two chars like EU or US */
|
|
+ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
|
|
+ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
|
|
u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
|
|
u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
|
|
u16 pa0b0;
|
|
@@ -47,10 +56,10 @@ struct ssb_sprom {
|
|
u8 gpio1; /* GPIO pin 1 */
|
|
u8 gpio2; /* GPIO pin 2 */
|
|
u8 gpio3; /* GPIO pin 3 */
|
|
- u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
|
|
- u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
|
|
- u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
|
|
- u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
|
|
+ u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
|
|
u8 itssi_a; /* Idle TSSI Target for A-PHY */
|
|
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
|
|
u8 tri2g; /* 2.4GHz TX isolation */
|
|
@@ -61,8 +70,8 @@ struct ssb_sprom {
|
|
u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
|
|
u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
|
|
u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
|
|
- u8 rxpo2g; /* 2GHz RX power offset */
|
|
- u8 rxpo5g; /* 5GHz RX power offset */
|
|
+ s8 rxpo2g; /* 2GHz RX power offset */
|
|
+ s8 rxpo5g; /* 5GHz RX power offset */
|
|
u8 rssisav2g; /* 2GHz RSSI params */
|
|
u8 rssismc2g;
|
|
u8 rssismf2g;
|
|
@@ -82,16 +91,13 @@ struct ssb_sprom {
|
|
u16 boardflags2_hi; /* Board flags (bits 48-63) */
|
|
/* TODO store board flags in a single u64 */
|
|
|
|
+ struct ssb_sprom_core_pwr_info core_pwr_info[4];
|
|
+
|
|
/* Antenna gain values for up to 4 antennas
|
|
* on each band. Values in dBm/4 (Q5.2). Negative gain means the
|
|
* loss in the connectors is bigger than the gain. */
|
|
struct {
|
|
- struct {
|
|
- s8 a0, a1, a2, a3;
|
|
- } ghz24; /* 2.4GHz band */
|
|
- struct {
|
|
- s8 a0, a1, a2, a3;
|
|
- } ghz5; /* 5GHz band */
|
|
+ s8 a0, a1, a2, a3;
|
|
} antenna_gain;
|
|
|
|
struct {
|
|
@@ -103,14 +109,85 @@ struct ssb_sprom {
|
|
} ghz5;
|
|
} fem;
|
|
|
|
- /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
|
|
+ u16 mcs2gpo[8];
|
|
+ u16 mcs5gpo[8];
|
|
+ u16 mcs5glpo[8];
|
|
+ u16 mcs5ghpo[8];
|
|
+ u8 opo;
|
|
+
|
|
+ u8 rxgainerr2ga[3];
|
|
+ u8 rxgainerr5gla[3];
|
|
+ u8 rxgainerr5gma[3];
|
|
+ u8 rxgainerr5gha[3];
|
|
+ u8 rxgainerr5gua[3];
|
|
+
|
|
+ u8 noiselvl2ga[3];
|
|
+ u8 noiselvl5gla[3];
|
|
+ u8 noiselvl5gma[3];
|
|
+ u8 noiselvl5gha[3];
|
|
+ u8 noiselvl5gua[3];
|
|
+
|
|
+ u8 regrev;
|
|
+ u8 txchain;
|
|
+ u8 rxchain;
|
|
+ u8 antswitch;
|
|
+ u16 cddpo;
|
|
+ u16 stbcpo;
|
|
+ u16 bw40po;
|
|
+ u16 bwduppo;
|
|
+
|
|
+ u8 tempthresh;
|
|
+ u8 tempoffset;
|
|
+ u16 rawtempsense;
|
|
+ u8 measpower;
|
|
+ u8 tempsense_slope;
|
|
+ u8 tempcorrx;
|
|
+ u8 tempsense_option;
|
|
+ u8 freqoffset_corr;
|
|
+ u8 iqcal_swp_dis;
|
|
+ u8 hw_iqcal_en;
|
|
+ u8 elna2g;
|
|
+ u8 elna5g;
|
|
+ u8 phycal_tempdelta;
|
|
+ u8 temps_period;
|
|
+ u8 temps_hysteresis;
|
|
+ u8 measpower1;
|
|
+ u8 measpower2;
|
|
+ u8 pcieingress_war;
|
|
+
|
|
+ /* power per rate from sromrev 9 */
|
|
+ u16 cckbw202gpo;
|
|
+ u16 cckbw20ul2gpo;
|
|
+ u32 legofdmbw202gpo;
|
|
+ u32 legofdmbw20ul2gpo;
|
|
+ u32 legofdmbw205glpo;
|
|
+ u32 legofdmbw20ul5glpo;
|
|
+ u32 legofdmbw205gmpo;
|
|
+ u32 legofdmbw20ul5gmpo;
|
|
+ u32 legofdmbw205ghpo;
|
|
+ u32 legofdmbw20ul5ghpo;
|
|
+ u32 mcsbw202gpo;
|
|
+ u32 mcsbw20ul2gpo;
|
|
+ u32 mcsbw402gpo;
|
|
+ u32 mcsbw205glpo;
|
|
+ u32 mcsbw20ul5glpo;
|
|
+ u32 mcsbw405glpo;
|
|
+ u32 mcsbw205gmpo;
|
|
+ u32 mcsbw20ul5gmpo;
|
|
+ u32 mcsbw405gmpo;
|
|
+ u32 mcsbw205ghpo;
|
|
+ u32 mcsbw20ul5ghpo;
|
|
+ u32 mcsbw405ghpo;
|
|
+ u16 mcs32po;
|
|
+ u16 legofdm40duppo;
|
|
+ u8 sar2g;
|
|
+ u8 sar5g;
|
|
};
|
|
|
|
/* Information about the PCB the circuitry is soldered on. */
|
|
struct ssb_boardinfo {
|
|
u16 vendor;
|
|
u16 type;
|
|
- u8 rev;
|
|
};
|
|
|
|
|
|
@@ -166,6 +243,7 @@ struct ssb_bus_ops {
|
|
#define SSB_DEV_MINI_MACPHY 0x823
|
|
#define SSB_DEV_ARM_1176 0x824
|
|
#define SSB_DEV_ARM_7TDMI 0x825
|
|
+#define SSB_DEV_ARM_CM3 0x82A
|
|
|
|
/* Vendor-ID values */
|
|
#define SSB_VENDOR_BROADCOM 0x4243
|
|
--- a/include/linux/ssb/ssb_driver_gige.h
|
|
+++ b/include/linux/ssb/ssb_driver_gige.h
|
|
@@ -2,6 +2,7 @@
|
|
#define LINUX_SSB_DRIVER_GIGE_H_
|
|
|
|
#include <linux/ssb/ssb.h>
|
|
+#include <linux/bug.h>
|
|
#include <linux/pci.h>
|
|
#include <linux/spinlock.h>
|
|
|
|
--- a/include/linux/ssb/ssb_regs.h
|
|
+++ b/include/linux/ssb/ssb_regs.h
|
|
@@ -228,6 +228,7 @@
|
|
#define SSB_SPROM1_AGAIN_BG_SHIFT 0
|
|
#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
|
|
#define SSB_SPROM1_AGAIN_A_SHIFT 8
|
|
+#define SSB_SPROM1_CCODE 0x0076
|
|
|
|
/* SPROM Revision 2 (inherits from rev 1) */
|
|
#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
|
|
@@ -267,6 +268,7 @@
|
|
#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
|
|
|
|
/* SPROM Revision 4 */
|
|
+#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
|
|
#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
|
|
#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
|
|
#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
|
|
@@ -389,6 +391,11 @@
|
|
#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM8_GPIOB_P3_SHIFT 8
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+#define SSB_SPROM8_LEDDC 0x009A
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+#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
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+#define SSB_SPROM8_LEDDC_ON_SHIFT 8
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+#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
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+#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
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#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
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#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
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@@ -404,6 +411,13 @@
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#define SSB_SPROM8_AGAIN2_SHIFT 0
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#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
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#define SSB_SPROM8_AGAIN3_SHIFT 8
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+#define SSB_SPROM8_TXRXC 0x00A2
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+#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
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+#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
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+#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
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+#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
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+#define SSB_SPROM8_TXRXC_SWITCH 0xff00
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+#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
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#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
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#define SSB_SPROM8_RSSISMF2G 0x000F
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#define SSB_SPROM8_RSSISMC2G 0x00F0
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@@ -430,6 +444,7 @@
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#define SSB_SPROM8_TRI5GH_SHIFT 8
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#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
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#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
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+#define SSB_SPROM8_RXPO2G_SHIFT 0
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#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
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#define SSB_SPROM8_RXPO5G_SHIFT 8
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#define SSB_SPROM8_FEM2G 0x00AE
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@@ -445,10 +460,71 @@
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#define SSB_SROM8_FEM_ANTSWLUT 0xF800
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#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
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#define SSB_SPROM8_THERMAL 0x00B2
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-#define SSB_SPROM8_MPWR_RAWTS 0x00B4
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-#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
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-#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
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-#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
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+#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
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+#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
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+#define SSB_SPROM8_THERMAL_TRESH 0xff00
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+#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
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+/* Temp sense related entries */
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+#define SSB_SPROM8_RAWTS 0x00B4
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+#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
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+#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
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+#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
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+#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
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+#define SSB_SPROM8_OPT_CORRX 0x00B6
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+#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
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+#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
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+#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
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+#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
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+#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
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+#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
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+/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
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+#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
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+#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
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+#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
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+#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
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+#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
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+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
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+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
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+#define SSB_SPROM8_TEMPDELTA 0x00BA
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+#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
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+#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
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+#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
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+#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
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+#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
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+#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
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+
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+/* There are 4 blocks with power info sharing the same layout */
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+#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
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+#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
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+#define SSB_SROM8_PWR_INFO_CORE2 0x0100
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+#define SSB_SROM8_PWR_INFO_CORE3 0x0120
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+
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+#define SSB_SROM8_2G_MAXP_ITSSI 0x00
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+#define SSB_SPROM8_2G_MAXP 0x00FF
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+#define SSB_SPROM8_2G_ITSSI 0xFF00
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+#define SSB_SPROM8_2G_ITSSI_SHIFT 8
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+#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
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+#define SSB_SROM8_2G_PA_1 0x04
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+#define SSB_SROM8_2G_PA_2 0x06
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+#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
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+#define SSB_SPROM8_5G_MAXP 0x00FF
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+#define SSB_SPROM8_5G_ITSSI 0xFF00
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+#define SSB_SPROM8_5G_ITSSI_SHIFT 8
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+#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
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+#define SSB_SPROM8_5GH_MAXP 0x00FF
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+#define SSB_SPROM8_5GL_MAXP 0xFF00
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+#define SSB_SPROM8_5GL_MAXP_SHIFT 8
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+#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
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+#define SSB_SROM8_5G_PA_1 0x0E
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+#define SSB_SROM8_5G_PA_2 0x10
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+#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
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+#define SSB_SROM8_5GL_PA_1 0x14
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+#define SSB_SROM8_5GL_PA_2 0x16
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+#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
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+#define SSB_SROM8_5GH_PA_1 0x1A
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+#define SSB_SROM8_5GH_PA_2 0x1C
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+
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+/* TODO: Make it deprecated */
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#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
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#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
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#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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@@ -473,12 +549,23 @@
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#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
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#define SSB_SPROM8_PA1HIB1 0x00DA
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#define SSB_SPROM8_PA1HIB2 0x00DC
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+
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#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
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#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
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#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
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#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
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#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
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+#define SSB_SPROM8_2G_MCSPO 0x0152
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+#define SSB_SPROM8_5G_MCSPO 0x0162
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+#define SSB_SPROM8_5GL_MCSPO 0x0172
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+#define SSB_SPROM8_5GH_MCSPO 0x0182
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+
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+#define SSB_SPROM8_CDDPO 0x0192
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+#define SSB_SPROM8_STBCPO 0x0194
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+#define SSB_SPROM8_BW40PO 0x0196
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+#define SSB_SPROM8_BWDUPPO 0x0198
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+
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/* Values for boardflags_lo read from SPROM */
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#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
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#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
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